Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 21 rejected under 35 U.S.C. 103 as being unpatentable over Arie (JP H07297211, machine-translation provided), in view of Lin (WO 2020199166, machine-translation provided).
Regarding Claim 1
FIG. 1 of Arie discloses a die bonding method, comprising: obtaining information about a quality grade of each die of a plurality of dies placed at a wafer {text: A large number of chips 20 on the wafer 18 are detected in their characteristics and positions on the wafer array in a die sort step before the die bonding step by the die bonding apparatus 10, and are classified into layers (for example, A classification) based on the characteristics. , B classification, C classification), and the control device 1. It is input as mapping information to the memory 7 or floppy dis}; picking up a first die having a first quality grade among the plurality of dies from the wafer {text: Chips 20 of the same classification are picked up from the wafer 18 of the wafer unit 21 installed on the wafer stage 11 and mounted on an island part (not shown) as a predetermined part of a lead frame (not shown) installed on the frame feeder 13}; identifying a plurality of bonding locations from a substrate according to a quality grade of the first die; and bonding the first die to a first bonding location (15A), among the plurality of bonding locations, of the substrate (15); picking up a second die having a second quality grade different from the first quality grade; and bonding the second die to a second bonding location (15B), among the plurality of bonding locations, of the substrate, wherein the first bonding location and the second bonding location are located in the same substrate, and wherein the first bonding location is different from the second bonding location, and wherein the first bonding location and the second bonding location are in different rows or columns in the plurality of bonding locations.
Arie is silent with respect to “the substrate is a printed circuit board (PCB) divided into a plurality of rows and columns, wherein dies having the same quality grade are set to be bonded on the same row or column in a plurality of bonding locations of the substrate”.
FIG. 8 of Lin discloses a similar die bonding method, wherein a first group of dies including the first die, among the plurality of dies, having the first quality grade (A) are set to be bonded on the first bonding area, and wherein a second group of dies including the second die, among the plurality of dies, having the second quality grade (B) are set to be bonded on the second bonding area; and the first bonding area is different from the second bonding area, wherein the substrate (200) is a printed circuit board (PCB) divided into a plurality of rows and columns [0037], wherein dies having the same quality grade are set to be bonded on the same row or column in a plurality of bonding locations of the substrate, and wherein the first bonding location and the second bonding location are in different rows or columns in the plurality of bonding locations.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the method of Arie, as taught by Lin. The ordinary artisan would have been motivated to modify Arie in the above manner for purpose of cost optimization (High-grade chips can be used for critical functions, while lower-grade chips handle less demanding tasks, reducing overall cost); performance scaling (Different chips can be optimized for specific functions, e.g., high-speed logic, low-power sensors, memory, without over-provisioning); space efficiency (Combining multiple chips on one substrate reduces the need for separate packages or boards) and thermal / power management (Lower-grade chips can be placed in areas with higher heat tolerance or lower power budgets).
Regarding Claim 21
FIG. 1 of Arie discloses a die bonding method, comprising: obtaining information about a quality grade of each die of a plurality of dies placed at a wafer (text: A large number of chips 20 on the wafer 18 are detected in their characteristics and positions on the wafer array in a die sort step before the die bonding step by the die bonding apparatus 10, and are classified into layers (for example, A classification) based on the characteristics. , B classification, C classification), and the control device 1. It is input as mapping information to the memory 7 or floppy dis); picking up a first die having a first quality grade among the plurality of dies from the wafer (text: Chips 20 of the same classification are picked up from the wafer 18 of the wafer unit 21 installed on the wafer stage 11 and mounted on an island part (not shown) as a predetermined part of a lead frame (not shown) installed on the frame feeder 13); identifying a plurality of bonding locations from a substrate according to a quality grade of the first die; and bonding the first die to a first bonding area (15A) within the first bonding area of the substrate (15); picking up a second die having a second quality grade different from the first quality grade; and bonding the second die to a second bonding area (15B) within the second bonding area of the substrate, wherein the first bonding area and the second area are located in the same substrate, wherein the first bonding area is different and separated from the second bonding area, wherein a first group of dies including the first die, among the plurality of dies, having the first quality grade (A-Class) are set to be bonded on the first bonding area, wherein a second group of dies including the second die, among the plurality of dies, having the second quality grade (B-Class) are set to be bonded on the second bonding area, wherein dies having the same quality grade are set to be bonded on the same bonding area among a plurality of bonding areas of the substrate including the first bonding area and the second bonding area, wherein each bonding area is composed of one or more rows and columns in a plurality of bonding locations of the substrate, and wherein the first bonding location and the second bonding location are in different bonding areas of the substrate.
Arie is silent with respect to “the substrate is a printed circuit board (PCB) divided into a plurality of rows and columns,”.
FIG. 8 of Lin discloses a similar die bonding method, wherein a first group of dies including the first die, among the plurality of dies, having the first quality grade (A) are set to be bonded on the first bonding area, and wherein a second group of dies including the second die, among the plurality of dies, having the second quality grade (B) are set to be bonded on the second bonding area; and the first bonding area is different from the second bonding area, wherein the substrate (200) is a printed circuit board (PCB) divided into a plurality of rows and columns [0037], wherein dies having the same quality grade are set to be bonded on the same row or column in a plurality of bonding locations of the substrate, and wherein the first bonding location and the second bonding location are in different rows or columns in the plurality of bonding locations.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the method of Arie, as taught by Lin. The ordinary artisan would have been motivated to modify Arie in the above manner for purpose of cost optimization (High-grade chips can be used for critical functions, while lower-grade chips handle less demanding tasks, reducing overall cost); performance scaling (Different chips can be optimized for specific functions, e.g., high-speed logic, low-power sensors, memory, without over-provisioning); space efficiency (Combining multiple chips on one substrate reduces the need for separate packages or boards) and thermal / power management (Lower-grade chips can be placed in areas with higher heat tolerance or lower power budgets).
Claims 1, 21 and 22 rejected under 35 U.S.C. 103 as being unpatentable over Kim (KR 20190097523) of record, in view of Mochizuki (KR 20130030196, machine-translation provided), in view of Miki (CN 100383940) of record.
Regarding Claim 1
FIG. 1 of Kim discloses a die bonding method, comprising: obtaining information about a quality grade of each die of a plurality of dies placed at a wafer (text: an electrical property test may be performed on the dies through an inspection apparatus such as a probe station, and the dies may be given a plurality of grades according to the results of the inspection process); picking up a first die having a first quality grade among the plurality of dies from the wafer (FIG. 2); identifying a plurality of bonding locations from a substrate according to a quality grade of the first die; and bonding the first die (12A) to a first bonding location, among the plurality of bonding locations, of the substrate; picking up a second die (12B) having a second quality grade different from the first quality grade; and bonding the second die to a second bonding location, among the plurality of bonding locations, of the substrate, wherein the first bonding location and the second bonding location are located in the same substrate, and wherein the first bonding location is different from the second bonding location (FIG. 3).
Kim is silent with respect to “a first group of dies including the first die, among the plurality of dies, having the first quality grade are set to be bonded on the first bonding area, and wherein a second group of dies including the second die, among the plurality of dies, having the second quality grade are set to be bonded on the second bonding area”; “the first bonding area is different from the second bonding area” and “the substrate is a printed circuit board (PCB) divided into a plurality of rows and columns, wherein dies having the same quality grade are set to be bonded on the same row or column in a plurality of bonding locations of the substrate, and wherein the first bonding location and the second bonding location are in different rows or columns in the plurality of bonding locations”.
FIG. 7 of Mochizuki discloses a similar die bonding method, wherein a first group of dies (D1) including the first die, among the plurality of dies, having the first quality grade are set to be bonded on the first bonding area (P1), and wherein a second group of dies (D2) including the second die, among the plurality of dies, having the second quality grade are set to be bonded on the second bonding area (P2); and the first bonding area is different from the second bonding area, wherein dies having the same quality grade are set to be bonded on the same row or column in a plurality of bonding locations of the substrate (board 7), wherein the substrate is divided into a plurality of rows and columns, wherein dies having the same quality grade are set to be bonded on the same row or column in a plurality of bonding locations of the substrate, and wherein the first bonding location and the second bonding location are in different rows or columns in the plurality of bonding locations; the first bonding location and the second bonding location are in different rows or columns in the plurality of bonding locations.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the method of Kim, as taught by Mochizuki. The ordinary artisan would have been motivated to modify Kim in the above manner for purpose of processing a wafer having a plurality of grades by using a classification control step (Abstract of Mochizuki).
Kim as modified by Mochizuki is silent with respect to the substrate (board) “is a printed circuit board (PCB)”.
FIG. 15 of Miki discloses a similar die bonding method, the substrate (150) is a printed circuit board (PCB) divided into a plurality of rows and columns (FIG. 16).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the method of Kim, as taught by Miki. The ordinary artisan would have been motivated to modify Kim in the above manner because PCB are used in nearly all electronic products today.
Regarding Claim 21
FIG. 1 of Kim discloses a die bonding method, comprising: obtaining information about a quality grade of each die of a plurality of dies placed at a wafer (text: an electrical property test may be performed on the dies through an inspection apparatus such as a probe station, and the dies may be given a plurality of grades according to the results of the inspection process); picking up a first die having a first quality grade among the plurality of dies from the wafer (FIG. 2); identifying a plurality of bonding locations from a substrate according to a quality grade of the first die; bonding the first die (12A) to a first bonding location within the first bonding area of the substrate; picking up a second die (12B) having a second quality grade different from the first quality grade; and bonding the second die to a second bonding location within the second bonding area of the substrate, wherein the first bonding area and the second bonding area are located in the same substrate, wherein the first bonding area is different and separated from the second bonding area (FIG. 3).
Kim is silent with respect to “a first group of dies including the first die, among the plurality of dies, having the first quality grade are set to be bonded on the first bonding area, wherein a second group of dies including the second die, among the plurality of dies, having the second quality grade are set to be bonded on the second bonding area” and “the substrate is a printed circuit board (PCB) divided into a plurality of rows and columns”.
FIG. 7 of Mochizuki discloses a similar die bonding method, wherein a first group of dies (D1) including the first die, among the plurality of dies, having the first quality grade are set to be bonded on the first bonding area (P1), and wherein a second group of dies (D2) including the second die, among the plurality of dies, having the second quality grade are set to be bonded on the second bonding area (P2); and the first bonding area is different from the second bonding area, wherein dies having the same quality grade are set to be bonded on the same row or column in a plurality of bonding locations of the substrate (board 7), wherein the substrate is divided into a plurality of rows and columns, wherein dies having the same quality grade are set to be bonded on the same row or column in a plurality of bonding locations of the substrate, and wherein the first bonding location and the second bonding location are in different rows or columns in the plurality of bonding locations; the first bonding location and the second bonding location are in different rows or columns in the plurality of bonding locations.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the method of Kim, as taught by Mochizuki. The ordinary artisan would have been motivated to modify Kim in the above manner for purpose of processing a wafer having a plurality of grades by using a classification control step (Abstract of Mochizuki).
Kim as modified by Mochizuki is silent with respect to the substrate (board) “is a printed circuit board (PCB)”.
FIG. 15 of Miki discloses a similar die bonding method, the substrate (150) is a printed circuit board (PCB) divided into a plurality of rows and columns (FIG. 16).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the method of Kim, as taught by Miki. The ordinary artisan would have been motivated to modify Kim in the above manner because PCB are used in nearly all electronic products today.
Regarding Claim 22
FIG. 1 of Kim discloses the size of each die, regardless of the grade, is the same. Therefore, a size of a bonding area, among the plurality of bonding areas of the substrate, set for each grade of the plurality of grades is set on the basis of a number of dies for each grade in the wafer.
Claims 6 and 7 rejected under 35 U.S.C. 103 as being unpatentable over Kim, Mochizuki and Miki, in view of Nakamura (KR 20190051067) of record.
Regarding Claim 6
Kim as modified by Mochizuki and Miki discloses Claim 1.
Kim as modified by Mochizuki and Miki is silent with respect to “stacking a second die, among the plurality of dies, on the first die on the substrate; and bonding the second die to the first die on the substrate”.
FIG. 6 of Nakamura discloses a similar die bonding method, comprising stacking a second die (10), among the plurality of dies, on the first die on the substrate (30); and bonding the second die to the first die on the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the method of Kim, as taught by Nakamura. The ordinary artisan would have been motivated to modify Kim in the above manner for purpose of miniaturizing semiconductor devices (text of Nakamura).
Regarding Claim 7
It would have been obvious to one of ordinary skill in the art that the first die and the second die have the same quality grade for purpose of, for instance, having dies with the same quality grade after dicing.
Claims 23 and 24 rejected under 35 U.S.C. 103 as being unpatentable over Kim, Mochizuki and Miki, in view of Kim8 (KR 20160051488, machine-translation provided).
Regarding Claim 23
Kim as modified by Mochizuki and Miki discloses Claim 21.
Kim as modified by Mochizuki and Miki is silent with respect to “stacking a second die, among the plurality of dies, on the first die on the substrate; and bonding the second die to the first die on the substrate”.
FIG. 1 of Kim8 discloses a similar die bonding method, comprising stacking a second die, among the plurality of dies, on the first die on the substrate; and bonding the second die to the first die on the substrate (text: the die bonding apparatus 100 may be used for manufacturing multi-chip semiconductor devices by stacking a plurality of dies on a substrate).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the method of Kim, as taught by Kim8. The ordinary artisan would have been motivated to modify Kim in the above manner for purpose of largely reducing a time consumed for the die bonding processes (Abstract of Kim8).
Regarding Claim 24
Modified Kim discloses dies having the same quality grade are set to be bonded on the same row or column in a plurality of bonding locations of the substrate. It would have been obvious to one of ordinary skill in the art that the first die and the third die have the same quality grade.
Pertinent Art
JP 2591464 discloses chips are classified into a plurality of grades according to electrical characteristics and performing die bonding of a plurality of types of chips or chips classified into a plurality of grades on a wafer. FIG. 8 of Liu (CN 113921428), WO 2020199166, CN 111201595 and TW M588348 each discloses a first group of dies including the first die, among the plurality of dies, having the first quality grade are set to be bonded on the first bonding area, and wherein a second group of dies including the second die, among the plurality of dies, having the second quality grade are set to be bonded on the second bonding area” and “the first bonding area is different from the second bonding area. Pertinent art also includes US 2015/0255421, 2020/0194613, 2015/0364218, 2009/0227048 and CN 106373914.
Response to Arguments
Applicant’s arguments with respect to Claim 1 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
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