Prosecution Insights
Last updated: April 19, 2026
Application No. 17/865,355

SYSTEMS AND METHODS FOR EMBEDDING ELECTRONIC COMPONENTS IN SUBSTRATES

Final Rejection §103§112
Filed
Jul 14, 2022
Examiner
XU, ZHIJUN
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Advanced Micro Devices, Inc.
OA Round
2 (Final)
77%
Grant Probability
Favorable
3-4
OA Rounds
3y 5m
To Grant
90%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allow Rate
43 granted / 56 resolved
+8.8% vs TC avg
Moderate +13% lift
Without
With
+12.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
43 currently pending
Career history
99
Total Applications
across all art units

Statute-Specific Performance

§103
67.5%
+27.5% vs TC avg
§102
16.6%
-23.4% vs TC avg
§112
12.9%
-27.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 56 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment The amendment filed on Oct. 3rd, 2025 has been entered. Claims 1, 3-20 remain pending in the application. Claims 11-20 are examined in this office action. Claims 1, 3-10 are withdrawn from further consideration. Claim Objections Claim 12 is objected to because of the following informalities: In claim 12, line 1, “The semiconductor substrate" should read “The . Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 14-15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Regarding claim 14, the additional instance of the passive device doubles a capacitance density are discussed in para. 0028 and fig. 4 with a same instance of the passive device. However, the additional element comprises a dummy substrate in claim 11 are discussed in para. 0031 and fig. 5 with a dummy substrate instead of same instance of the passive device. They are mutually exclusive embodiments. Therefore, this limitation is new matter. Claim 15 would also be rejected under 35 U.S.C. 112(a) because they are dependent on claim 14. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 11-16 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (US 20130105943) in view of Yu et al. (US 20180269188). Regarding claim 11, Lai teaches a substrate (fig. 2D, substrate 2a; para. 0023) comprising: a passive device (first capacitor 21; para. 0024) embedded within a cavity (cavity 200; para. 0024) of the substrate (2a); and an element (second capacitor 23; para. 0026) bonded through a bonding layer (bonding layer 22; para. 0026) to the electronic component (21) to form an electronic component aggregation (21, 22, 23); wherein the maximum thickness of the electronic component aggregation (total thickness of 21, 22, 23) is substantially equal to a thickness of the substrate core (thickness of 200). Lai fails to explicitly teach the additional element comprises a dummy substrate. However, Yu teaches the additional element (Yu: fig. 21, dummy dies 802; para. 0083, similar to 23 of Lai) comprises a dummy substrate (Yu: substrate of dummy die). Yu and Lai are considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the dummy substrate as taught by Yu. Doing so would realize a dummy die to improve the heat dissipation of the structure (Yu: para. 0085). Regarding claim 12, Lai in view of Yu teaches the semiconductor substrate of claim 11, wherein a width of the dummy substrate (Yu: fig. 21, width of 802) matches (proportional match) a width of the passive device (Yu: width of integrated circuit dies 114; para. 0089, similar to 21 of Lai), and wherein the dummy substrate (Yu: 802) increases the maximum thickness of the passive device aggregation (Yu: increases the max thickness of 802 on thermal layer 806, 114; para. 0089) by a thickness of the dummy substrate (Yu: thickness of 802). Regarding claim 13, Lai in view of Yu teaches the substrate of claim 11, wherein the dummy substrate (Yu: fig. 21, 802) is formed of dielectric or insulation material (Yu: dielectric material; para. 0086). Regarding claim 14, Lai in view of Yu further teaches the substrate of claim 13, wherein bonding the passive device (Lai: fig. 2G, 21) to the addition instance of the electronic component (Lai: 23) doubles a capacitance density (Lai: two capacitors of 21, 23 in a particular substrate area, BRI as 'double capacitance' in the substrate area) of the passive device aggregation (Lai: device of fig. 2G) in comparison to usage of a non-aggregated single-layer electronic component (Lai: fig. 1D, one capacitor of capacitor 11; para. 0006). Regarding claim 15, Lai in view of Yu further teaches the substrate of claim 14, wherein: conductive contacts (Lai: fig. 2G, first electrode pads 210a, 210b; para. 0024) are disposed on an outward face (bottom surface) of the passive device (Lai: 21) opposite the addition element (Lai: 23); and conductive contacts (Lai: second electrode pads 230a, 230b; para. 0026) are disposed on an outward face (top surface) of the addition element (Lai: 23) opposite the passive device (Lai: 21). Regarding claim 16, Lai in view of Yu further teaches the substrate of claim 11, wherein the passive device (Yu: fig. 21, 114) comprises a silicon capacitor (Yu: capacitor with silicon substrate; para. 0020). Regarding claim 20, Lai teaches a device (fig. 2G) comprising: a passive device (fig. 2D, first capacitor 21; para. 0024) embedded within a cavity (cavity 200; para. 0024) of a substrate core (cavity 200; para. 0024) of a (substrate 2a; para. 0023); and an addition element (second capacitor 23; para. 0026) bonded through a bonding layer (bonding layer 22; para. 0026) to the passive device (21) to form an electronic component aggregation (21, 22, 23); wherein the maximum thickness of the electronic component aggregation (total thickness of 21, 22, 23) is substantially equal to a thickness of the substrate core (thickness of 200). Lai fails to explicitly teach the additional element comprises a dummy substrate. However, Yu teaches the additional element (Yu: fig. 21, dummy dies 802; para. 0083, similar to 23 of Lai) comprises a dummy substrate (Yu: substrate of dummy die). Yu and Lai are considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the dummy substrate as taught by Yu. Doing so would realize a dummy die to improve the heat dissipation of the structure (Yu: para. 0085). Claim(s) 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai in view of Yu as applied to claim 11 above, and further in view of Chen et al. (US 20200395306). Regarding claim 17, Lai in view of Yu teaches the substrate of claim 11, including the passive device (Lai: fig. 2D, 21). Lai in view of Yu fails to explicitly teach the passive device has a maximum thickness of approximately 775 microns. However, Chen teaches the passive device (Chen: fig. 10I, bottom semiconductor dies 626; para. 0100, similar to 21 of Lai) has a thickness approximately between about 25 μm and about 750 μm (Chen: thickness of 626 approximately is half of substrate 302, which is between about 50 μm and about 1500 μm and has cavities; para. 0036, similar to 20 of Lai), which overlaps the thickness range a maximum thickness of approximately 775 microns. Chen, Yu and Lai are considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the thickness range from approximately between about 25 μm and about 750 μm to a maximum thickness of approximately 775 microns. Doing so would realize a substrate core structure providing structural support, and reducing package size. Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges). Regarding claim 18, Lai in view of Yu and Chen teaches the semiconductor substrate of claim 11, including the substrate core (Lai: fig. 2D, 200). Lai fails to explicitly teach the thickness of the substrate core is greater than approximately 800 microns. However, Chen teaches the thickness of the substrate core substrate core (Chen: fig. 10J, thickness of substrate 302 has cavities; para. 0036, similar to 200 of Lai) is between about 50 μm and about 1500 μm (Chen: between about 50 μm and about 1500 μm; para. 0036), which overlaps the thickness range of greater than approximately 800 microns. Chen, Yu and Lai are considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the thickness range from between about 50 μm and about 1500 μm to greater than approximately 800 microns. Doing so would realize a substrate core structure providing structural support, and reducing package size. Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges). Regarding claim 19, Lai in view of Yu and Chen teaches the substrate of claim 18, including a combined thickness of the passive device and the addition element (Chen: fig. 10I, combined thickness of semiconductor dies 626; para. 0100, similar to 21, 23 of Lai). Lai in view of Chen as applied to claim 18 above fails to explicitly teach the combined thickness is greater than approximately 800 microns. However, Chen teaches the combined thickness (Chen: fig. 10I, combined thickness of 626) is approximately between about 50 μm and about 1500 μm (Chen: combined thickness of 626 approximately as 302, which is between about 50 μm and about 1500 μm; para. 0036), which overlaps the thickness range of greater than approximately 800 microns. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the thickness range from approximately between about 50 μm and about 1500 μm to greater than approximately 800 microns. Doing so would realize a substrate core structure providing structural support, and reducing package size. Here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP Chapter 2100-Section 2144.05-Optimization of Ranges). Response to Arguments Applicant’s arguments with respect to claim(s) 11-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ZHIJUN XU/Examiner, Art Unit 2818 /BRIAN TURNER/Examiner, Art Unit 2818
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Prosecution Timeline

Jul 14, 2022
Application Filed
May 29, 2025
Non-Final Rejection — §103, §112
Sep 26, 2025
Applicant Interview (Telephonic)
Sep 26, 2025
Examiner Interview Summary
Oct 03, 2025
Response Filed
Dec 12, 2025
Final Rejection — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
77%
Grant Probability
90%
With Interview (+12.9%)
3y 5m
Median Time to Grant
Moderate
PTA Risk
Based on 56 resolved cases by this examiner. Grant probability derived from career allow rate.

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