DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 24 November 2025 has been entered.
Response to Arguments
Applicant’s arguments and amendments, see Remarks and Claims, filed 24 November 2025, with respect to the rejection(s) of the claims in the previous Office action have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Shinji Ohuchi (US 2002/0038890 A1), the details of which are presented below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4 and 21-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the same material" in line 8. There is insufficient antecedent basis for this limitation in the claim. This leaves the claim unclear as to what “the material” refers to. It should read “a same material” to establish proper antecedent basis for the limitation. For at least this reason, claims 2-4 and 21-22 are also rejected based on their dependency from claim 1. Claim 1 also recites “wherein the first portion of the first cover insulating layer and the second portion or the first cover insulating layer are made…” in lines 7-8. This appears to be a typographic error and should read “the second portion of the first cover insulating layer”. Claim 1 also recites “the same plane” in the second to last line. There is insufficient antecedent basis for this limitation in the claim, and it should read “a same plane” to establish proper antecedence. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shinji Ohuchi (US 2002/0038890 A1; hereinafter Ohuchi).
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Regarding Claim 1, Ohuchi teaches a semiconductor package (see annotated Fig. 14) comprising:
a first semiconductor chip (204 comprising transistors; ¶0032) comprising an upper surface (top of 204), a lower surface (bottom of 204), a side surface (left side of 204), and a chip pad (205; ¶0036) provided on the upper surface (top of 204);
a first cover insulating layer (207; ¶0036) includes a first portion (1P) covering the upper surface of the first semiconductor chip (top of 204) and a second portion (2P) extending from the first portion (1P), covering the side surface of the first semiconductor chip (left side of 204) and formed integrally with the first portion (1P) (as shown in annotated Fig. 14; 1P and 2P of 207 are the same integrally formed film 207), wherein the first portion (1P) of the first cover insulating layer (207) and the second portion (2P) of the first cover insulating layer (207) are made of a same material (both portions of 207 are made of a same material; ¶0036);
a first upper conductive layer (top portion of 210, labeled 210a; ¶0036) extending along an upper surface of the first cover insulating layer (top of 207) and electrically connected to the chip pad (205) of the first semiconductor chip (204) (as shown in Fig. 14);
a first side conductive layer (side portion of 210, labeled 210b) extending along a side surface of the first cover insulating layer (left side of 207) and connected to the first upper conductive layer (210a);
a second cover insulating layer (213 made of epoxy resin; ¶0044) including a third portion (3P) covering the first upper conductive layer (210a) and the first cover insulating layer (207) and a fourth portion (4P) extending from the third portion (3P), covering the first side conductive layer (210b) (as shown in annotated Fig. 14); and
a first lower conductive layer (1100; ¶0106) extending along the lower surface of the first semiconductor chip (bottom of 204) and connected to the first side conductive layer (210b) (as shown in annotated Fig. 14), and
wherein a lower surface of the second portion of the first cover insulating layer (bottom of 2P of 207) and a lower surface of the first side conductive layer (bottom of 210b) are positioned on a same plane as the lower surface of the first semiconductor chip (bottom of 204) (as shown in annotated Fig. 14).
Regarding Claim 3, Ohuchi teaches the semiconductor package of claim 1, wherein the first lower conductive layer (1100) is in contact with the lower surface of the first side conductive layer (bottom of 210b) (as shown in annotated Fig. 14).
Regarding Claim 21, Ohuchi teaches the semiconductor package of claim 1, wherein the first lower conductive layer (1100) is in direct contact with the lower surface of the first semiconductor chip (bottom of 204) (as shown in Fig. 14).
Allowable Subject Matter
Claims 2, 4, and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and wherein the 35 U.S.C. 112(b) rejections are overcome.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 2, Ohuchi teaches the semiconductor package of claim 1, wherein
a vertical height of the first side conductive layer (210b) is greater than a vertical height of the first semiconductor chip (204),
the first lower conductive layer (1100) is in contact with the lower surface of the first semiconductor chip (bottom of 204).
However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including:
a horizontal width of the first side conductive layer (210b) is greater than a horizontal width of the first upper conductive layer (210a) and a horizontal width of the first lower conductive layer (1100).
Regarding Claim 4, Ohuchi teaches the semiconductor package of claim 1.
However, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the Examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, all the limitations of the instant invention in their entirety (the individual limitations may be found just not in combination with proper motivation); further including further comprising:
a first lower insulating layer covering the first lower conductive layer and the lower surface of the first semiconductor chip; a first lower bump pad connected to the first lower conductive layer through an opening of the first lower insulating layer; a lower connection bump on the first lower bump pad; an upper bump pad connected to the first upper conductive layer through an opening of the second cover insulating layer; and an upper connection bump on the upper bump pad.
For at least this reason, claim 22 would also be allowed based on its dependency from claim 4.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN PRIDEMORE whose telephone number is (703)756-4640. The examiner can normally be reached Monday - Friday 8:00am - 4:00pm EST.
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NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898