Prosecution Insights
Last updated: April 19, 2026
Application No. 17/866,566

SEMICONDUCTOR PACKAGE WITH REDUCED CONNECTION LENGTH

Final Rejection §103
Filed
Jul 18, 2022
Examiner
BULLARD-CONNOR, GENEVIEVE GRACE
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
MediaTek Inc.
OA Round
4 (Final)
43%
Grant Probability
Moderate
5-6
OA Rounds
3y 5m
To Grant
53%
With Interview

Examiner Intelligence

Grants 43% of resolved cases
43%
Career Allow Rate
3 granted / 7 resolved
-25.1% vs TC avg
Moderate +10% lift
Without
With
+10.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
61 currently pending
Career history
68
Total Applications
across all art units

Statute-Specific Performance

§103
48.2%
+8.2% vs TC avg
§102
32.7%
-7.3% vs TC avg
§112
19.1%
-20.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 7 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claims 1 and 7 are objected to because of the following informalities: Claims 1 and 7 read “a length of the TMV” which should read as “a length of the TMVs”, or “a length of one of the plurality of the TMVs”, or the like, since the singular form of TMV does not have proper antecedent basis. Claim 7 recites twice the limitation that requires that each of the plurality of TMVs has an oval shape or a rectangular shape when viewed from above, which is redundant. Appropriate correction is required. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2, 4-8, and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2016/0093572) and Chiu et al. (“Chiu” US 2020/0194326). Regarding claim 1, Chen discloses a semiconductor package (Figure 8), comprising: a bottom package (202) comprising an application processor (AP) die (processor 202, para. [0032]) surrounded by a molding compound (402, see Figure 8); a top package (812) mounted on the bottom package (202, see Figure 8); a top re-distribution layer (RDL) structure (102) disposed between the top package (202) and the bottom package (812, see Figure 2); a plurality of through-molding vias (TMVs) (active vias 302) disposed in the molding compound (402, see Figure 8) for electrically connecting the top package (812) with the AP die (202)…wherein the TMVs (302) have a horizontal pitch along the first direction (horizontal direction in plan view of Figure 9) and a vertical pitch along the second direction (vertical direction in plan view of Figure 9), wherein the vertical pitch is greater than the horizontal pitch (see Figure 9, the vias 302 are arranged in a staggered manner such that the vias are horizontally spaced closer than they are vertically spaced)…; and a bottom re-distribution layer (RDL) structure (602), wherein the AP die (202) and the plurality of TMVs (302) are interconnected to the bottom RDL structure (602, see Figures 7 and 8). Chen does not disclose that each of the plurality of TMVs has an oval shape with a major axis and a minor axis, wherein a length of the major axis is different from a length of the minor axis, or a rectangular shape when viewed from above, wherein a length of the TMV along a first direction is different from a length of the TMV along a second direction, and wherein each of the TMVs elongates along a via-to-die direction that is perpendicular to each side of the AP die. Chiu discloses in Figure 2B, however, a plurality of TMVs (200b, groups on lateral sides S2 and S4 of the die 300) having an oval shape (see Figure 2b) with a major axis (200b1) and a minor axis (200b2), wherein a length of the major axis (200b1) is different from a length of the minor axis (200b2, see Figure 2B and para. [0017]), wherein a length of the TMV (200b) along a first direction (here the first direction is the vertical direction of the plan view of Figure 2B) is different from a length of the TMV (200b, lateral portions on S2/S4) along a second direction (here the second direction is the horizontal direction of the plan view of Figure 2B, and the length of the TMVs in the vertical/first direction is different from that in the horizontal/second direction), and wherein each of the TMVs (200b, lateral portions on S2/S4) elongates along a via-to-die direction (here this the horizontal direction from the center of the die 300 to each of the vias 200b on each side S2/S4 of the die 300, as well as the vertical direction from the center of the die 300 that extends vertically to the vias on sides S1/S2 of the die) that is perpendicular to each side of the AP die (sides S1-4, the horizontal and vertical directions are perpendicular to each side S1-S4 of the die 300, see Figure 2B). It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Chiu above into the teachings of Chen for the purpose of ensuring the reliability of the package structure (Chiu, para. [0016], [0025]). Regarding claim 2, Chen discloses wherein the top package (812) is a memory package (dies 804 of top package 812 are memory dies, para. [0032]). Regarding claim 4, Chen discloses wherein the TMVs (302) are aligned along the second direction (TMVs are aligned along the vertical direction of plan view of Figure 9, see also annotated Figure 9 below). Regarding claim 5, Chen discloses wherein the TMVs (302) are arranged in a staggered manner (see Figure 9). Regarding claim 6, Chen discloses wherein a plurality of solder balls (704) is disposed on a surface of the bottom RDL structure (602, see Figures 7 and 8). Regarding claim 7, Chen discloses a semiconductor package (Figure 8), comprising: a bottom package (600) comprising a top 2-layer substrate (602/604), a middle molding compound (402), and a bottom multi-layer substrate (102) to encapsulate an application processor (AP) die (202, see Figures 6 and 8); a top package (812) mounted on the bottom package (600, see Figure 8); a plurality of through-molding vias (TMVs) (active vias 302) disposed in the middle molding compound (402) for electrically connecting the top package (812) with the AP die (202), wherein the TMVs have a horizontal pitch along the first direction (horizontal direction in plan view of Figure 9) and a vertical pitch along the second direction (vertical direction in plan view of Figure 9), wherein the vertical pitch is greater than the horizontal pitch (see Figure 9, the vias 302 are arranged in a staggered manner such that the vias are horizontally spaced closer than they are vertically spaced). Chen does not disclose that each of the plurality of TMVs has an oval shape with a major axis and a minor axis, wherein a length of the major axis is different from a length of the minor axis, or a rectangular shape when viewed from above, wherein a length of the TMV along a first direction is different from a length of the TMV along a second direction, and wherein each of the TMVs elongates along a via-to-die direction that is perpendicular to each side of the AP die, wherein each of the plurality of TMVs has an oval shape or a rectangular shape when viewed from above. Chiu discloses in Figure 2B, however, a plurality of TMVs (200b, groups on lateral sides S2 and S4 of the die 300) having an oval shape (see Figure 2b) with a major axis (200b1) and a minor axis (200b2), wherein a length of the major axis (200b1) is different from a length of the minor axis (200b2, see Figure 2B and para. [0017]), wherein a length of the TMV (200b) along a first direction (here the first direction is the vertical direction of the plan view of Figure 2B) is different from a length of the TMV (200b, lateral portions on S2/S4) along a second direction (here the second direction is the horizontal direction of the plan view of Figure 2B, and the length of the TMVs in the vertical/first direction is different from that in the horizontal/second direction), and wherein each of the TMVs (200b, lateral portions on S2/S4) elongates along a via-to-die direction (here this the horizontal direction from the center of the die 300 to each of the vias 200b on each side S2/S4 of the die 300, as well as the vertical direction from the center of the die 300 that extends vertically to the vias on sides S1/S2 of the die) that is perpendicular to each side of the AP die (sides S1-4, the horizontal and vertical directions are perpendicular to each side S1-S4 of the die 300, see Figure 2B). It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Chiu above into the teachings of Chen for the purpose of ensuring the reliability of the package structure (Chiu, para. [0016], [0025]). Regarding claim 8, Chen discloses wherein the top package (812) is a memory package (dies 804 of top package 812 are memory dies, para. [0032]). Regarding claim 10, Chen discloses wherein the TMVs (302) are aligned along the second direction (TMVs are aligned along the vertical direction of plan view of Figure 9, see also annotated Figure 9 below). Regarding claim 11, Chen discloses wherein the TMVs (302) are arranged in a staggered manner (see Figure 9). PNG media_image1.png 680 1146 media_image1.png Greyscale PNG media_image2.png 646 707 media_image2.png Greyscale Response to Arguments Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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Prosecution Timeline

Jul 18, 2022
Application Filed
Mar 04, 2025
Non-Final Rejection — §103
May 07, 2025
Interview Requested
May 16, 2025
Applicant Interview (Telephonic)
May 16, 2025
Examiner Interview Summary
Jun 08, 2025
Response Filed
Jun 23, 2025
Final Rejection — §103
Sep 10, 2025
Interview Requested
Sep 16, 2025
Applicant Interview (Telephonic)
Sep 16, 2025
Examiner Interview Summary
Sep 25, 2025
Request for Continued Examination
Oct 03, 2025
Response after Non-Final Action
Nov 03, 2025
Non-Final Rejection — §103
Feb 04, 2026
Response Filed
Feb 18, 2026
Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12525517
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
2y 5m to grant Granted Jan 13, 2026
Study what changed to get past this examiner. Based on 1 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
43%
Grant Probability
53%
With Interview (+10.0%)
3y 5m
Median Time to Grant
High
PTA Risk
Based on 7 resolved cases by this examiner. Grant probability derived from career allow rate.

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