DETAILED ACTION The instant application having Application No. 17/867,625 filed on 7/18/2022 is presented for examination by the examiner. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. Claims 1-20 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention. As per independent Claims 1, 8 and 15, each recites a data selection circuit configured to enable different configurations of an adaptive multiplier array to perform different dot products. This limitation is considered a purely result-oriented limitation because it recites a desired result, i.e. “to enable different configurations of the adaptive multiplier array…result[ing] in the adaptive multiplier array performing a different dot product on the received data”, without reciting any steps detailing how to accomplish the result. For example, “configuring a data selection circuit ” fails to describe a way to accomplish the claimed result of enabling different configurations of the multiplier array to perform different dot product operations. Claim limitations such as this are considered purely result-oriented. Purely result-oriented limitations fail to comply with the written description requirement when the way to achieve the result is not known to those skilled in the art, i.e. when it is the inventor’s purported contribution to the art. When this is the case, the way to achieve the result must be recited in the claim in a manner that is commensurate with the supporting disclosure to satisfy the written description requirement of 35 U.S.C. § 112(a). The way to achieve the result does not necessarily need to be recited in as much detail as the preferred embodiment(s) described in the disclosure as long as those skilled in the art would understand the inventor to have invented, and been in possession of, the invention as broadly claimed. In this case, “ configuring a data selection circuit” to enable different configurations of an adaptive multiplier array is clearly the inventor’s purported contribution to the art. See e.g. Paragraphs 00 03-0006 and 0018-0019 of the instant specification. However, limitation(s) that simply recite “configur[ing]” a data selection circuit do not provide adequate disclosure within the claims themselves, and thus fails to be commensurate with the supporting disclosure in the instant specification. Therefore, the claims in question lack the specificity necessary to provide sufficient written description support under 35 U.S.C. § 112(a) such that those skilled in the art would understand the inventor to have invented, and been in possession of, the claimed invention. As per the dependent Claims 2- 7 , 9-14, and 16-20 , they are rejected for the reasons presented above, due to their dependency upon their respective base claims. Additionally per independent Claims 1, 8 and 15, as stated above, each recites configuring a data selection circuit to enable different configurations of an adaptive multiplier array to perform different dot products. However, the specification fails to describe different configurations of an adaptive multiplier array, or how configuring a data selection circuit results in a reconfigured multiplier array ( or different configuration of a multiplier array ) . The specification discloses in Paragraph 0051 that the “data selection circuit includes multiplexers that forward the data to the multiplier array 525 to support different multiplier configurations ” , and moreover that “different sets of multiplexers 520 may forward the data in a different way so that the multiplier array 525 performs different dot products or matrix multiplications on the data.” However, this fails to describe what the different configurations of the multiplier array are, what the configurations entail, how the configurations operate to perform different dot product operations, and how using multiplexers to forward data in a different way could result in a “different configuration” of e.g. a systolic array of multiplier circuits. The specification also discloses in Paragraph 0058 that the “dot products may differ according to size (number of bits of the operands), number of channels, output precision, and output matrices. FIG. 7 is a chart illustrating different multiplier array configurations”. However, the chart in Figure 7 and the corresponding description in the specification merely lists input and output matrix sizes, precisions, etc., but does not provide any example of how the multiplier array is “configured” to perform dot product operations with the various inputs and outputs. Similarly, Figure 5 shows an “adaptive multiplier array” as a black box with “multiplier configuration” black boxes inside of it. This too fails to show any actual configuration of a multiplier array, how it could be configured to perform different operations on different inputs and outputs, or how multiplexers forwarding data to the multiplier array could enable the array to become reconfigured to perform a different operation. Accordingly, the specification fails to describe configuring a data selection circuit to enable different configurations of an adaptive multiplier array to perform different dot products in sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention. As per the dependent Claims 2- 7 , 9-14, and 16-20 , they are rejected for the reasons presented above, due to their dependency upon their respective base claims. Claim Rejections - 35 USC § 102(a)(1) In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 3-4, 8, 10-11, 15, and 17-19 are rejected under 35 U.S.C. 102 (a)( 1 ) as being anticipated by Tsai et al. (US 2018/0173676 ) . As per Claim 1, Tsai discloses a n integrated circuit (IC), comprising: a data processing engine (Figure 1 , a system comprising convolution module 120) ; comprising: a data selection circuit configured to receive data, and an adaptive multiplier array connected to the data selection circuit (Figure s 3-5 and Paragraphs 0023 , 0037, 0042 and 0045-0046 , a data dispatch engine 550 receives data from memory 130, wherein the data dispatch engine is coupled to hybrid array 251 of processing elements (PEs), each PE performing a multiply-and-add operation on matrix data); wherein the data selection circuit is configured to enable different configurations of the adaptive multiplier array, wherein each of the different configurations results in the adaptive multiplier array performing a different dot product on the received data ( Abstract and Figures 1, 2B, 3-5 and Paragraphs 0021, 0025, 0029 , 0034, 0036, 0039, 0041 and 0046, the data dispatch engine 550 feeds data to the hybrid array 251 according to the mode select signal, where the hybrid array 251 performs convolution, i.e. dot product, operations in either matrix mode or filter mode according to the mode select signal, i.e. according to the data format provided by the data dispatch engine 550). As per Claim 3, Tsai discloses the IC of claim 1, wherein the adaptive multiplier array comprises a plurality of multiplication circuits that perform the different dot products as part of matrix multiplication ( Paragraphs 0005, 0032, 0036-0037 and 0045, the hybrid array selects matrix mode instead of filter mode in order to perform matrix multiplication(s), wherein each PE in the array comprises multiply-and-add circuits). As per Claim 4, Tsai discloses t he IC of claim 3, wherein the plurality of multiplication circuits is arranged in a systolic array (Figures 3-5, a 2D array of identical PE’s coupled to one another, i.e. a systolic array) . As per Claim 8, Tsai discloses an IC, comprising: a data selection circuit configured to receive data, and an adaptive multiplier array connected to the data selection circuit (Figures 1, 3-5 and Paragraphs 0023, 0037, 0042 and 0045-0046, convolution module 120 comprises data dispatch engine 550 that receives data from memory 130, wherein the data dispatch engine is coupled to hybrid array 251 of processing elements (PEs), each PE performing a multiply-and-add operation on matrix data); wherein the data selection circuit is configured to enable different configurations of the adaptive multiplier array, wherein each of the different configurations results in the adaptive multiplier array performing a different dot product on the received data (Abstract and Figures 1, 2B, 3-5 and Paragraphs 0021, 0025, 0029, 0034, 0036, 0039, 0041 and 0046, the data dispatch engine 550 feeds data to the hybrid array 251 according to the mode select signal, where the hybrid array 251 performs convolution, i.e. dot product, operations in either matrix mode or filter mode according to the mode select signal, i.e. according to the data format provided by the data dispatch engine 550). As per Claim 10, Tsai discloses the IC of claim 8, wherein the adaptive multiplier array comprises a plurality of multiplication circuits that perform the different dot products (Paragraphs 0005, 0032, 0036-0037 and 0045, the hybrid array selects matrix mode instead of filter mode in order to perform matrix multiplication(s), wherein each PE in the array comprises multiply-and-add circuits). As per Claim 11, Tsai discloses the IC of claim 10, wherein the plurality of multiplication circuits is arranged in a systolic array (Figures 3-5, a 2D array of identical PE’s coupled to one another, i.e. a systolic array). As per Claim 15, Tsai discloses a method, comprising: receiving, at a data processing engine, a first instruction to execute a first dot product ( Figures 1-2B and Paragraphs 0030 and 0032-0033, analysis module 150 receives an instruction to generate the mode select signal and activate the array to perform convolution operations); configuring a data selection circuit in the data processing engine to enable a first configuration of an adaptive multiplier array corresponding to the first dot product (Abstract and Figures 1, 2B, 3-5 and Paragraphs 0021, 0025, 0029, 0034, 0036, 0039, 0041 and 0046, in response to the mode select signal, the data dispatch engine 550 feeds data to the hybrid array 251 according to the mode select signal, where the hybrid array 251 performs convolution, i.e. dot product, operations in either matrix mode or filter mode according to the mode select signal, i.e. according to the data format provided by the data dispatch engine 550) ; receiving, at the data processing engine, a second instruction to execute a second dot product; and configuring the data selection circuit in the data processing engine to enable a second configuration of the adaptive multiplier array corresponding to the second dot product (Abstract and Figures 1, 2B, 3-5 and Paragraphs 0021, 0025, 0029, 0034, 0036, 0039, 0041 and 0046, in response to the mode select signal, the data dispatch engine 550 feeds data to the hybrid array 251 according to the mode select signal, where the hybrid array 251 performs convolution, i.e. dot product, operations in either matrix mode or filter mode according to the mode select signal, i.e. according to the data format provided by the data dispatch engine 550) . As per Claim 17 , Tsai discloses the method of claim 15 , wherein the adaptive multiplier array comprises a plurality of multiplication circuits that perform the first and second dot products (Paragraphs 0005, 0032, 0036-0037 and 0045, the hybrid array selects matrix mode instead of filter mode in order to perform matrix multiplication(s), wherein each PE in the array comprises multiply-and-add circuits). As per Claim 18 , Tsai discloses the method of claim 1 7 , wherein the plurality of multiplication circuits is arranged in a systolic array (Figures 3-5, a 2D array of identical PE’s coupled to one another, i.e. a systolic array). As per Claim 19, Tsai discloses the method of claim 15, wherein the first and second dot products are performed as part of executing a neural network ( Figure 1 and Paragraphs 0009 and 0020-0021 ). Claim Rejections - 35 USC § 102(a)(2) The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 8 and 15 are additionally rejected, and Claims 5-6 and 12-13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Liu et al. (US 2022/0035890) . As per Claim 1, Liu discloses a n integrated circuit (IC), comprising: a data processing engine (Abstract and Figures 9-11A, a matrix multiply accelerator 200 comprising processing element 250-1); comprising: a data selection circuit configured to receive data, and an adaptive multiplier array connected to the data selection circuit (Figure 11A and Paragraphs 0102-0103, data selection circuit 253 receives bitmap or index data, and causes multiplexers 251-1 through 251-4 to output data to multiplier array 254-1 through 254-4); wherein the data selection circuit is configured to enable different configurations of the adaptive multiplier array, wherein each of the different configurations results in the adaptive multiplier array performing a different dot product on the received data (Figure 11A and Paragraphs 0103 -0111, the data selection circuit 253 provides selection signal(s) to the multiplexers, which cause s the multipliers 254 and adder 256 to perform a dot product operation on the selected data inputs, i.e. a dot product is performed on different data according to the selection of the data selection circuit ). As per Claim 5 , Liu discloses t he IC of claim 1, further comprising: a plurality of data processing engines, each comprising a copy of the data selection circuit and the adaptive multiplier array (Figures 10A-11, each processing element (PE) comprises a data selection circuit, multiplexers, multipliers, and adder as shown in Figure 11A) . As per Claim 6 , Liu discloses t he IC of claim 5, wherein the plurality of data processing engines is arranged in an array (Figures 10A-B and Paragraphs 0078-0080, PE array 202) . As per Claim 8, Liu discloses an IC, comprising: a data selection circuit configured to receive data, and an adaptive multiplier array connected to the data selection circuit (Abstract and Figures 9-11A and Paragraphs 0102-0103, processing element 250-1 comprises data selection circuit 253 that receives bitmap or index data, and causes multiplexers 251-1 through 251-4 to output data to multiplier array 254-1 through 254-4); wherein the data selection circuit is configured to enable different configurations of the adaptive multiplier array, wherein each of the different configurations results in the adaptive multiplier array performing a different dot product on the received data (Figure 11A and Paragraphs 0103-0111, the data selection circuit 253 provides selection signal(s) to the multiplexers, which cause s the multipliers 254 and adder 256 to perform a dot product operation on the selected data inputs, i.e. a dot product is performed on different data according to the selection of the data selection circuit). As per Claim 12, Liu discloses t he IC of claim 8 , further comprising: a plurality of data processing engines, each comprising a copy of the data selection circuit and the adaptive multiplier array (Figures 10A-11, each processing element (PE) comprises a data selection circuit, multiplexers, multipliers, and adder as shown in Figure 11A) . As per Claim 13, Liu discloses t he IC of claim 12 , wherein the plurality of data processing engines is arranged in an array (Figures 10A-B and Paragraphs 0078-0080, PE array 202) . As per Claim 15, Liu discloses a method, comprising: receiving, at a data processing engine, a first instruction to execute a first dot product (Figures 9-10B and Paragraphs 0082-0083, the matrix multiply accelerator receives instruction(s) or commands to load the bitmap data and start the matrix multiply operation) ; configuring a data selection circuit in the data processing engine to enable a first configuration of an adaptive multiplier array corresponding to the first dot product (Figure 11A and Paragraphs 0102-0111, in response to the instruction(s), data selection circuit 253 receives bitmap or index data and provides selection signal(s) to the multiplexers, which causes the multipliers 254 and adder 256 to perform a dot product operation on the selected data inputs, i.e. a dot product is performed on different data according to the selection of the data selection circuit); receiving, at the data processing engine, a second instruction to execute a second dot product; and configuring the data selection circuit in the data processing engine to enable a second configuration of the adaptive multiplier array corresponding to the second dot product (Figure 11A and Paragraphs 0102-0111, in response to the instruction(s), data selection circuit 253 receives bitmap or index data and provides selection signal(s) to the multiplexers, which causes the multipliers 254 and adder 256 to perform a dot product operation on the selected data inputs, i.e. a dot product is performed on different data according to the selection of the data selection circuit) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 2, 9 , and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. in view of Tran (US 5,162,666) . As per Claim 2 , Liu does not explicitly disclose t he IC of claim 1, wherein the data selection circuit comprises multiplexers, wherein each of the different configurations corresponds to a different set of the multiplexers being used to forward data from the data selection circuit to the adaptive multiplier array. However, Liu discloses multi-input multiplexers, wherein each of the different configurations corresponds to a different multiplexer input being selected to forward data from the data selection circuit to the adaptive multiplier array (Figures 11A and Paragraph 0104, data selection circuit causes each multiplexer to select from among e.g. 8 inputs to forward data to the multiplier array) . Furthermore, Tran teaches that selecting from multi-input multiplexers comprises a different set of the multiplexers being used to select (i.e. forward ) data ( Figure s 2 -5 and Column 1, lines 64-68 and Column 3 , line 59 through Column 4 , line 1 3 , multiple input multiplexers are constructed of cascaded 2 -input multiplexers, i.e. selecting different multiplexer inputs uses a different set of 2 -input multiplexer s from the series-connected multiplexers ). It would have been obvious to one of ordinary skill in the art prior to the effective filing of the claimed invention to apply the multiplexer architecture as taught by Tran to the multiplexer s of Liu because it provides the structure for performing e.g. 8 -to-1 selecting of signals with minimal hardware ( Tran, Column 1, lines 54-58 and 62-63, and Column 2, lines 3-4, compact multiplexer layout and limited loading on control inputs is provided by the multiplexer circuit s). As per Claim 9, Liu does not explicitly disclose t he IC of claim 8 , wherein the data selection circuit comprises multiplexers, wherein each of the different configurations corresponds to a different set of the multiplexers being used to forward data from the data selection circuit to the adaptive multiplier array. However, Liu discloses multi-input multiplexers, wherein each of the different configurations corresponds to a different multiplexer input being selected to forward data from the data selection circuit to the adaptive multiplier array (Figures 11A and Paragraph 0104, data selection circuit causes each multiplexer to select from among e.g. 8 inputs to forward data to the multiplier array) . Furthermore, Tran teaches that selecting from multi-input multiplexers comprises a different set of the multiplexers being used to select (i.e. forward ) data ( Figure s 2 -5 and Column 1, lines 64-68 and Column 3 , line 59 through Column 4 , line 1 3 , multiple input multiplexers are constructed of cascaded 2 -input multiplexers, i.e. selecting different multiplexer inputs uses a different set of 2 -input multiplexer s from the series-connected multiplexers). It would have been obvious to one of ordinary skill in the art prior to the effective filing of the claimed invention to apply the multiplexer architecture as taught by Tran to the multiplexer s of Liu because it provides the structure for performing e.g. 8 -to-1 selecting of signals with minimal hardware ( Tran, Column 1, lines 54-58 and 62-63, and Column 2, lines 3-4, compact multiplexer layout and limited loading on control inputs is provided by the multiplexer circuit s). As per Claim 16, Liu does not explicitly disclose t he method of claim 1 5 , wherein the data selection circuit comprises multiplexers, wherein each of the different configurations corresponds to a different set of the multiplexers being used to forward data from the data selection circuit to the adaptive multiplier array. However, Liu discloses multi-input multiplexers, wherein each of the different configurations corresponds to a different multiplexer input being selected to forward data from the data selection circuit to the adaptive multiplier array (Figures 11A and Paragraph 0104, data selection circuit causes each multiplexer to select from among e.g. 8 inputs to forward data to the multiplier array) . Furthermore, Tran teaches that selecting from multi-input multiplexers comprises a different set of the multiplexers being used to select (i.e. forward ) data ( Figure s 2 -5 and Column 1, lines 64-68 and Column 3 , line 59 through Column 4 , line 1 3 , multiple input multiplexers are constructed of cascaded 2 -input multiplexers, i.e. selecting different multiplexer inputs uses a different set of 2 -input multiplexer s from the series-connected multiplexers). It would have been obvious to one of ordinary skill in the art prior to the effective filing of the claimed invention to apply the multiplexer architecture as taught by Tran to the multiplexer s of Liu because it provides the structure for performing e.g. 8 -to-1 selecting of signals with minimal hardware ( Tran, Column 1, lines 54-58 and 62-63, and Column 2, lines 3-4, compact multiplexer layout and limited loading on control inputs is provided by the multiplexer circuit s). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT MATTHEW SANDIFER whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-5175 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Mon-Fri 9:30am-6pm . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT James Trujillo can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 272-3677 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MATTHEW D SANDIFER/ Primary Examiner, Art Unit 2151