Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species I in the reply filed on April 23, 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (KR 20180000653 A) in view of Yu et al. (US 2021/0193582).
Regarding claim 1, Lee discloses a semiconductor package comprising:
a first wiring structure (W1) including a first wiring layer (142), and a second wiring layer (112a) disposed on the first wiring layer (142), and connected to a first connecting structure (160/170) placed disposed on the first wiring layer (142) [Figs. 12 and 14 (annotated below)];
a first semiconductor chip (120/121) disposed on the first wiring structure (W1) and connected to the first wiring structure (142) through a first connecting pad (122-2) disposed on a first side of the first semiconductor chip (120/121) [Figs. 12 and 14 (annotated below)];
a second wiring structure [Machine English Translation, page 11: an opening (not shown) … may be formed on the sealing material 130…a separate connection terminal or the like may be connected to the opened rewiring layer 112b…]; and
an insulating member (111) disposed between the first and second wiring structures [Figs. 12 and 14 (annotated below)], wherein the first wiring structure (W1) further includes a first signal pattern (142-2a) that is electrically connected (143-2a) to the first connecting pad (122-2) [Fig. 14], and
the first signal pattern (142-2a) redistributes the first connecting pad (122-2) to the first connecting structure (170) via the insulating member (111) [Figs. 12 and 14 (annotated below): please note that wirings 112b/113 are embedded within insulating member 111].
However, Lee does not disclose a second wiring structure disposed on the first semiconductor chip.
Yu teaches a first semiconductor chip (100), an insulating member (222), and a second wiring structure (206) disposed on the first semiconductor chip (100) [Fig. 18A].
Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to modify Lee by disposing a second wiring structure on the first semiconductor chip as taught by Yu because it helps to provide a connection path to an additional structure such as the package (300) allowing a greater degree of parallel processing capabilities [paragraph 0002 and Figure 18A].
[AltContent: textbox (111)][AltContent: arrow][AltContent: textbox (W1)][AltContent: ]
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Regarding claim 2, Lee discloses wherein the insulating member (111) further includes a connecting via (113) that penetrates at least a part of the insulating member (111), and the first signal pattern (142-2a) forms an electrical path which goes through the first wiring layer (W1) and the connecting via (113) [Figs. 12 and 14 (annotated above)].
Regarding claim 4, Lee discloses wherein the first wiring structure (W1) further includes a second signal pattern (S2) which has a path different from the first signal pattern (142-2a), is electrically connected to a second connecting pad (122) placed on the first side of the first semiconductor chip (120/121), and redistributes the second connecting pad (122) to the first connecting structure (170) [Fig. 12, annotated below].
[AltContent: arrow][AltContent: textbox (142-2a)][AltContent: textbox (S2)][AltContent: arrow][AltContent: arrow][AltContent: textbox (170)][AltContent: textbox (W1)][AltContent: ][AltContent: textbox (S2)]
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Regarding claim 5, Lee discloses wherein the first signal pattern (142-2a) has an electrical path (113) which increases by a distance corresponding to a thickness of the insulating member (111) as compared to that of the second signal pattern (S2) [Figs. 12 (annotated above) and 14 (annotated above)].
Regarding claim 18, Lee discloses a semiconductor package comprising:
a first semiconductor package, wherein the first semiconductor package includes:
a first wiring structure (W1) including a first wiring layer (142), and a second wiring layer (112a) disposed on the first wiring layer (142), and connected to a first connecting structure (160/170) disposed below the first wiring layer (142) [Figs. 12 and 14 (annotated above)];
a first semiconductor chip (120/121) disposed on the first wiring structure (W1) and connected to the first wiring structure (142) through a first connecting pad (122-2) disposed on a first side of the first semiconductor chip (120/121) [Figs. 12 and 14 (annotated above)];
a second wiring structure [Machine English Translation, page 11: an opening (not shown)…may be formed on the sealing material 130…a separate connection terminal or the like may be connected to the opened rewiring layer 112b…];
an insulating member (111) disposed between the first and second wiring structures and including a connecting via (113) [Figs. 12 and 14 (annotated below)];
wherein the first wiring structure (W1) further includes a first signal pattern (142-2a) that is electrically connected (143-2a) to the first connecting pad (122-2) [Fig. 14],
the first signal pattern (142-2a) redistributes the first connecting pad (122-2) to the first connecting structure (170) via the connecting via (113) [Figs. 12 and 14 (annotated above): please note that wirings 112b/113 are embedded within insulating member 111].
However, Lee does not disclose a second semiconductor package and a second wiring structure disposed on the first semiconductor chip.
Yu teaches a first semiconductor chip (100), an insulating member (222), a second wiring structure (206) disposed on the first semiconductor chip (100), and a second semiconductor package (300) disposed on the first semiconductor package; wherein the second semiconductor package (300) includes a second semiconductor chip (304) mounted on a third wiring structure (302) that is disposed on the first semiconductor package [Fig. 18A and paragraphs 0069-0070],
Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to modify Lee by including a second wiring structure and a second semiconductor package as taught by Yu because it helps to allow a greater degree of parallel processing capabilities [paragraph 0002].
Regarding claim 20, Lee discloses wherein the first wiring structure (W1) further includes:
a second signal pattern (S2) which is electrically connected to a second connecting pad (122) disposed on the first side of the first semiconductor chip (120/121), and has a path different from that of the first signal pattern (142-2a) [Fig. 12, annotated above], and
the first signal pattern (142-2a) has an electrical path which increases by a distance corresponding to a thickness of the connecting via (113), as compared with that of the second signal pattern (S2) [Figs. 12 (annotated above) and 14 (annotated above)].
Allowable Subject Matter
Claims 11 and 14-17 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
In regard to claim 11, the prior art fails to teach, disclose, or suggest, either alone or in combination, the first signal pattern redistributes the first connecting pad to the first connecting structure via the mold layer and the second wiring structure as instantly claimed, and in combination with the additional limitations.
Claims 3, 6-9 and 19 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jose R Diaz/Primary Examiner, Art Unit 2815
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