Prosecution Insights
Last updated: April 19, 2026
Application No. 17/868,308

SEMICONDUCTOR PACKAGE

Final Rejection §102§103§112
Filed
Jul 19, 2022
Examiner
BELL, LAUREN R
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
2 (Final)
40%
Grant Probability
At Risk
3-4
OA Rounds
3y 7m
To Grant
70%
With Interview

Examiner Intelligence

Grants only 40% of cases
40%
Career Allow Rate
148 granted / 375 resolved
-28.5% vs TC avg
Strong +31% interview lift
Without
With
+30.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
61 currently pending
Career history
436
Total Applications
across all art units

Statute-Specific Performance

§103
42.1%
+2.1% vs TC avg
§102
19.7%
-20.3% vs TC avg
§112
33.1%
-6.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 375 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Election/Restrictions Applicant’s election without traverse of Species 1 (Fig. 3) in the reply filed on 1/30/2025 is acknowledged. Claims 10 and 17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1/30/2025. Specifically, each of claim 10 and 17 require “the top surface of the second dam portion has a curved surface shape, and the second length of the second dam portion gradually decreases in a direction away from the side surface of the first semiconductor chip,” which is a feature shown in Species 3 (Fig. 4B). Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 7, 19 and 15 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claims 7 and 19, the term “about” is a relative term which renders the claim indefinite. The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Regarding claim 15, the limitation “an outer surface of the first dam portion,” is unclear as to how it is related to the “outer side of the first dam portion” recited in claim 13. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 5-6, 8-9, 11-13, 15-16, and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 2021/0111160; herein “Kim”). Regarding claim 1, Kim discloses in Fig. 1A-C and related text a semiconductor package comprising: a package substrate (510, see [0041]); a first semiconductor chip (e.g. 100 or 200, see [0018]) disposed on the package substrate; a second semiconductor chip (400, see [0018]) stacked on the first semiconductor chip; a dam structure (600, see [0048]) disposed on the package substrate and surrounding the first semiconductor chip and the second semiconductor chip, the dam structure including a first dam portion comprising an inner surface having a first length in a vertical direction and facing a side surface of the first semiconductor chip, and an outer surface opposing the inner surface (see annotated Fig. 1C below for one example interpretation of “first dam portion”), and a second dam portion connected to the first dam portion and extending from the outer surface of the first dam portion, and having a second length less than the first length in the vertical direction (see annotated Fig. 1C below for one example interpretation of “first dam portion”); an adhesive layer (150/160, see [0020]) disposed on the package substrate, the adhesive layer including a first adhesive portion disposed between the first semiconductor chip and the package substrate and overlapping the first semiconductor chip in the vertical direction (e.g. portion of 150/160 between 100/200 and 510), a second adhesive portion disposed on an outer side of the first semiconductor chip and comprising at least a part contacting a top surface of the first dam portion (e.g. portion of 150/160 between 600 and 100/200; note that the portion contacts the edge of the top surface), and a third adhesive portion (e.g. portion of 150/160 between 400 and 300) disposed between the first semiconductor chip and the second semiconductor chip and overlapping the second semiconductor chip in the vertical direction; and a molding layer (700, see [0053]) disposed on the package substrate and contacting a top surface of the second dam portion. PNG media_image1.png 450 696 media_image1.png Greyscale Regarding claim 5, Kim further discloses the molding layer (700) contacts the outer surface of the first dam portion (at the top edge of the outer surface) and the top surface of the second dam portion (see annotated Fig. 1C above), and the adhesive layer (150/160) contacts the top surface of the first dam portion and the inner surface of the first dam portion (see annotated Fig. 1C above). Regarding claim 6, Kim further discloses a side surface of the molding layer (700) and an outer surface of the second dam portion are disposed on the same plane (see annotated Fig. 1C above), and , the adhesive layer (150/160) does not overlap the second dam portion in the vertical direction (see annotated Fig. 1C above). Regarding claim 8, Kim further discloses wherein the top surface of the first dam portion (600) is disposed at a level lower than a top surface of the first semiconductor chip (200) in the vertical direction. Regarding claim 9, Kim further discloses wherein the top surface of the second dam portion has a planar shape extending in a horizontal direction perpendicular to the vertical direction (see annotated Fig. 1C above). Regarding claim 11, Kim further discloses wherein the first semiconductor chip includes a first semiconductor substrate (e.g. 110, see [0024]) comprising a first active layer (120, see [0024]), a first lower chip pad (142, see [0024]) disposed on a bottom surface of the first semiconductor substrate, a chip through electrode (130, see [0025]) passing through at least a part of the first semiconductor substrate in the vertical direction and connected to the first active layer, a first upper chip pad (144, see [0031]) disposed on a top surface of the first semiconductor substrate and connected to the chip through electrode, and a first chip connection terminal (170, see [0019]) disposed between the first lower chip pad and the package substrate (510), and wherein the second semiconductor chip includes a second semiconductor substrate (410) comprising a second active layer (420), a second lower chip pad (442) disposed on a bottom surface of the second semiconductor substrate, and a second chip connection terminal (470) disposed between the second lower chip (442) pad and the (144) first upper chip pad. Regarding claim 12, Kim further discloses the first adhesive portion (portion of 150/160 between 100 and 510) surrounds the first chip connection terminal (170), and the third adhesive portion (portion of 150/160 between 300 and 400) surrounds the second chip connection terminal (470). Regarding claim 13, Kim substantially discloses the invention in the same manner and for the same reasons as applied to claim 1 above. Regarding claim 15, Kim further discloses the invention in the same manner and for the same reasons as applied to claim 5 above. Regarding claim 16, Kim further discloses the invention in the same manner and for the same reasons as applied to claim 6 above. Regarding claim 18, Kim substantially discloses the invention in the same manner and for the same reasons as applied to claims 1 and 11 above. Claim(s) 13-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shih et al. (US 6,434,024; herein “Shih). Regarding claim 13, Shih teaches in Fig. 9 and related text a semiconductor package comprising: a package substrate (200); a semiconductor chip (202, see col. 5 line 9) disposed on the package substrate; a dam structure (stepped structure of 200 serving as a dam) disposed on the package substrate and surrounding the semiconductor chip, the dam structure including a first dam portion (portion of t1, see Fig. 9) having a first length in a vertical direction, and a second dam portion (portion of t2, see fig. 7) connected to the first dam portion and extending from an outer side of the first dam portion, and having a second length less than the first length in the vertical direction; an adhesive layer (a first portion of 205, see col. 5 line 16) disposed on the package substrate, the adhesive layer including a first adhesive portion disposed between the semiconductor chip and the package substrate and overlapping the semiconductor chip in the vertical direction, and a second adhesive portion disposed on an outer side of the semiconductor chip and comprising at least a part contacting a top surface of the first dam portion; and a molding layer (a second portion of 205; note that applicant’s disclosure recites that the adhesive layer and the molding layer can be insulating polymer, see [0076] and [0081], and therefore two portions of 205 would be structurally the same) disposed on the package substrate. Regarding claim 14, Shih further discloses wherein the outer side of the first dam portion and an outer surface of the second adhesive portion are disposed on the same plane (note that one can choose first and second portions of 205 such that the claimed limitation is met). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 2, 4, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, as applied to claims 1 and 18 above, and in view of Lin et al. (US 2018/0366439; herein “Lin”). Regarding claim 2, Kim does not explicitly disclose a material of the dam structure comprises at least any one of a photo imageable dielectric (PID) material and a photosensitive polyimide (PSPI), which are capable of being subject to a photolithography process. In the same field of endeavor, Lin teaches in Fig. 9 and related text a semiconductor package comprising a dam (DS, see [0034]), wherein a material of the dam structure comprises at least any one of a photo imageable dielectric (PID) material and a photosensitive polyimide (PSPI), which are capable of being subject to a photolithography process (see [0034]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim by having a material of the dam structure comprise at least any one of a photo imageable dielectric (PID) material and a photosensitive polyimide (PSPI), which are capable of being subject to a photolithography process, as taught by Lin, because the selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also In re Leshin, 277 F.2d 197, 125. See also MPEP 2144.07. Regarding claims 4 and 20, Kim does not explicitly disclose a material of the dam structure and a material of the molding layer are the same as each other. In the same field of endeavor, Lin teaches in Fig. 9 and related text a semiconductor package comprising a dam (DS, see [0034]), wherein a material of the dam structure and a material of a molding layer are the same as each other (see [0034]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim by having a material of the dam structure and a material of the molding layer are the same as each other, as taught by Lin, because the selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also In re Leshin, 277 F.2d 197, 125. See also MPEP 2144.07. Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, as applied to claim 1 above, and in view of Saeki (US 2008/0237895; herein “Saeki”). Regarding claim 3, Kim does not disclose a material of the dam structure comprises at least any one of silicon oxide (SiO2) and an epoxy molding compound (EMC). In the same field of endeavor, Saeki teaches in Fig. 1 and related text a semiconductor package comprising a dam (16, see [0065]) wherein a material of the dam structure comprises at least any one of silicon oxide (SiO2) and an epoxy molding compound (EMC) (see [0074]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim by having a material of the dam structure comprises at least any one of silicon oxide (SiO2) and an epoxy molding compound (EMC), as taught by Saeki, for ease of manufacture. Additionally it would have been obvious because the selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also In re Leshin, 277 F.2d 197, 125. See also MPEP 2144.07. Claim(s) 7 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Kim. Regarding claims 7 and 19, Kim further discloses the first length of the first dam portion is about 8 micrometers to about 100 micrometers (note that about is interpreted broadly; further note that portions can be chosen such that the claimed limitation is met), and the top surface of the first dam portion (600) is disposed at a level lower than a top surface of the first semiconductor chip (200) in the vertical direction. In the alternative, one of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the height to be a result effective variable affecting the ability of the dam to block flow of the adhesive material. Thus, it would have been obvious to modify the device of Kim to have the “first length” within the claimed range in order to achieve a desired blocking function of the dam, and since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B and 2143. Furthermore, it has also been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936, (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LAUREN R BELL/Primary Examiner, Art Unit 2896 7/23/2025
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Prosecution Timeline

Jul 19, 2022
Application Filed
Jul 23, 2025
Non-Final Rejection — §102, §103, §112
Nov 17, 2025
Examiner Interview Summary
Nov 17, 2025
Examiner Interview (Telephonic)
Nov 24, 2025
Response Filed
Dec 18, 2025
Final Rejection — §102, §103, §112
Mar 31, 2026
Applicant Interview (Telephonic)
Mar 31, 2026
Examiner Interview Summary

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
40%
Grant Probability
70%
With Interview (+30.7%)
3y 7m
Median Time to Grant
Moderate
PTA Risk
Based on 375 resolved cases by this examiner. Grant probability derived from career allow rate.

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