Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-20 are pending in this application.
Applicant elected without traverse Species I (claims 1-20) in the reply filed on June 17, 2025.
The examiner notes that claims 1-20 are examined.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. KR10-2021-0123062, filed on September 15, 2021.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 19, 2022 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed November 12, 2025. Claims 1, 2, 4, 8, 9, 11, 16, and 18 are amended. The Examiner notes that claims 1-20 are examined.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee-007 (US 2018/0083007 A1) in view of Cho (US 2018/0366463 A1) and Lee-523 (2020/0243523 A1).
With respect to claim 1, Lee-007 teaches in Figs. 1-2:
A semiconductor device, comprising:
a substrate (substrate 100) comprising a first active pattern (first active patterns AP1) extending in a first direction (D2),
the first active pattern (AP1) being separated into a pair of first active patterns (left and right sides of the trench) by a trench (trench TR) extending in a second direction (D1) intersecting the first direction (D2);
a device isolation layer (device isolation layer ST) that fills a lower portion of the trench (TR);
a plurality of first source/drain patterns (first source/drain patterns SD1) on the first active pattern;
a first channel pattern (first channel pattern CH1) connected to the plurality of first source/drain patterns (SD1),
the first channel pattern (CH1) comprising a plurality of semiconductor patterns that are stacked and spaced apart from each other (semiconductor patterns NS1);
a first dummy gate electrode (dummy gate electrode DE on right side of trench) extending in the second direction (D1),
and being adjacent to a first sidewall (right side) of the trench (TR);
a gate electrode (gate electrode GE) spaced apart in the first direction (D2) from the first dummy gate electrode (DE on right),
the gate electrode (GE) extending in the second direction (D1) across the first channel pattern (CH1) (see Fig. 2B);
a gate capping pattern (gate capping pattern GP) on the gate electrode (GE);
Lee-007 fails to teach:
a gate contact coupled to the gate electrode;
a separation pattern extending in the second direction between the gate electrode and the first dummy gate electrode,
wherein, in the first direction, the separation pattern is between adjacent ones of the plurality of first source/drain patterns,
wherein a top surface of the separation pattern is at a same level as a top surface of the gate capping pattern.
Cho teaches:
a gate contact (gate contact patterns GCP) coupled to the gate electrode (gate metal pattern 115) (para. 42 “The gate contact patterns GCP may penetrate the interlayer insulation layer 133, the gap-fill insulation layer 131, and the capping insulation patterns 117 of the gate structures GS, and may be connected to the gate metal patterns 115”;
Lee-007 discloses the claimed invention except for a gate contact coupled to a gate electrode. Cho discloses that it is known in the art to provide a gate contact coupled to the gate electrode. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the device of Lee-007 with the gate contact of Cho, in order to electrically connect the gate structure to external circuits and control the voltage applied to the gate. See MPEP 2144.
Lee-523 teaches in Figs. 27-31:
a separation pattern (diffusion prevention pattern 350) extending in the second direction (2nd direction of Lee-523) between the gate electrode (gate structure 320) and the first dummy gate electrode (para. 104, gate structure 320 that is formed on 160 to serve as a dummy gate structure),
wherein, in the first direction (1st direction of Lee-523), the separation pattern (350) is between adjacent ones of the plurality of first source/drain patterns (source/drain layers 264),
wherein a top surface of the separation pattern (top surface of 350) is at a same level as a top surface of the gate capping pattern (gate capping pattern 330).
Lee-007/Cho discloses the claimed invention except for the separation pattern between the first/source drain patterns in the first direction and between the gate electrode and dummy gate electrode. Lee-523 teaches that it is known to include a separation pattern between the gate and dummy gate electrodes and adjacent S/D patterns in the first direction. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include the separation patterns as taught by Lee-523, since Lee-523 states in para. 104 that such a modification would reduce or prevent leakage currents from the gate electrodes. See MPEP 2144.
With respect to claim 2, Lee-523 further teaches:
and a bottom surface of the separation pattern (350 is at a level lower than bottom ends of the first source/drain patterns (264) (see Fig. 30).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lee-007 in view of Cho and Lee-523 as explained above.
With respect to claim 3, Lee-007/Cho/Lee-523 further teaches:
wherein the separation pattern (para. 105 of Lee-523, the second diffusion prevention pattern 350 may include a nitride, e.g., silicon nitride) comprises a material different from a material of the device isolation layer (para. 32 of Cho, “The third device isolation layer 107 may include, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbon nitride (SiCN) layer, a silicon carbon oxynitride (SiCON) layer, or a combination thereof”.)
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to choose from the choices of material for the separation pattern of Lee-523 and the isolation layer of Cho such that the separation pattern and isolation material are different, since it has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416.
With respect to claim 4, Lee-007 further teaches:
wherein the first dummy gate electrode (DE) comprises:
a body part;
a vertical part vertically and downwardly extending from the body part along the first sidewall of the trench (TR);
and a protruding part protruding from the vertical part toward one of the plurality of first source/drain patterns (SD1). (see annotated Fig. 2A below for body part, vertical part, and protruding part)
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With respect to claim 5, Lee-007 further teaches:
wherein a width of the vertical part is smaller than a width of the body part (see annotated Fig. 2A above.)
With respect to claim 6, Lee-007 further teaches:
a first gate spacer (gate spacer GS) on a sidewall of the gate electrode (GE) ;
a second gate spacer (blocking layer BL) on an upper sidewall of the separation pattern (110);
and a dummy gate spacer (GS on wall of DE) on a sidewall of the first dummy gate electrode (DE).
With respect to claim 7, Lee-007 further teaches:
wherein the dummy gate spacer extends along the first sidewall of the trench to contact a top surface of the device isolation layer (see Fig. 2A, portion of GS on inside wall of DE extends to the top of ST).
With respect to claim 8, Lee-007 further teaches:
wherein the gate electrode (GE) surrounds a top surface, a sidewall, and a bottom surface of each of the plurality of semiconductor patterns included in the first channel patterns (NS1).
With respect to claim 9, Lee-007 further teaches in Fig. 1, 2C, and 2D:
further comprising:
a second active pattern (active pattern AP2) extending in the first direction (D2),
and being spaced apart in the second direction (D1) from the first active pattern (AP1),
the trench (TR)separating the second active pattern into a pair of second active patterns (left and right, see Fig. 2C);
a plurality of second source/drain patterns (SD2) on the second active pattern (AP1);
and a second channel pattern (second channel pattern CH2) connected to the plurality of second source/drain patterns (SD2),
wherein each of the gate electrode (GE) and the first dummy gate electrode (DE) extends in the second direction across the second channel pattern (see Fig. 1).
With respect to claim 10, Lee-007 further teaches:
the trench (TR) comprises a second sidewall (left sidewall) that faces the first sidewall (right sidewall);
and the semiconductor device further comprises a second dummy gate electrode (DE on left) extending in the second direction (D1, see Fig. 1)),
and being adjacent to the second sidewall (See Fig. 2A).
With respect to claim 16, Lee-007 teaches:
A semiconductor device, comprising:
a substrate (substrate 100) comprising a first logic cell (portion of device to left of trench TR),
a second logic cell (portion of device to right of trench TR),
and an isolation region between the first logic cell and the second logic cell (area between first and second logic cell that includes trench TR),
the first logic cell and the second logic cell being adjacent to each other in a first direction (D2);
a trench (trench TR) on the isolation region,
the trench (TR) having a first sidewall (left) adjacent to the first logic cell (portion to left of trench) and a second sidewall (right) adjacent to the second logic cell (portion to right of trench);
a device isolation layer (device isolation layer ST) in a lower portion of the trench (TR);
a first active pattern (active pattern AP1 on left side of trench) and a second active pattern (active pattern AP1 on right side of the trench) in the first logic cell (left) and the second logic cell (right), respectively;
a plurality of first source/drain patterns (SD1 on left side of trench) and a plurality of second source/drain patterns (SD1 on right side of trench) on the first active pattern (AP1 on left) and the second active pattern (AP1 on right), respectively;
a first channel pattern (channel pattern CH1 on left side of trench) and a second channel pattern (channel pattern CH1 on right side of trench) connected to the plurality of first source/drain patterns (SD1 on left) and the plurality of second source/drain patterns (SD1 on right), respectively,
each of the first and second channel patterns comprising a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern sequentially stacked and spaced apart from each other (each instance of CH1 is made up of semiconductor pattern NS1 which is made up of three nanowires);
a first dummy gate electrode (dummy gate electrode DE on left side of trench) on the first sidewall (left) of the trench (TR),
the first dummy gate electrode (DE on left) extending in a second direction (D1) intersecting the first direction (D2);
a second dummy gate electrode (DE on right side of trench) on the second sidewall (right) of the trench (TR),
the second dummy gate electrode (DE on right) extending in the second direction (D1);
a first gate electrode (gate electrode GE on left side of trench) and a second gate electrode (gate electrode GE on right side of trench) extending in the second direction (D1) across the first channel pattern and the second channel pattern (see Fig. 2B), respectively,
each of the first and second gate electrodes comprising a first part between the substrate and the first semiconductor pattern (see Figs. 2B),
a second part between the first semiconductor pattern and the second semiconductor pattern (see Figs. 2B),
a third part between the second semiconductor pattern and the third semiconductor pattern (see Figs. 2B),
and a fourth part on the third semiconductor pattern (see Figs. 2B);
a gate dielectric layer (gate dielectric pattern GI around GE) between the first channel pattern (CH1 on left) and the first gate electrode (G) and between the second channel pattern (CH1 on right) and the second gate electrode (another of GE to left of trench);
a dummy gate dielectric layer (GI around DE) between the first channel pattern (CH1 on left) and the first dummy gate electrode (DE on left) and between the second channel pattern (CH1 on right) and the second dummy gate electrode (DE on right);
a first gate spacer (gate spacer GS on sidewalls of GE) on each of sidewalls of the first and second gate electrodes;
a dummy gate spacer (gate spacer GS on sidewalls of DE) on each of sidewalls of the first and second dummy gate electrodes;
a gate capping pattern (gate capping pattern GP) on each of top surfaces of the first and second gate electrodes;
a first separation (first interlayer dielectric 110 on left side) pattern extending in the second direction (D1) between the first gate electrode (GE on left) and the first dummy gate electrode (DE on left);
a first interlayer dielectric layer (second interlayer dielectric 120) on the gate capping pattern (GP);
an active contact penetrating (contact plug CT1) the first interlayer dielectric layer (120),
and being coupled to one of the pluralities of first and second source/drain patterns (SD1);
wherein a top surface of the first separation pattern (110 on left) is at a same level as a top surface of the gate capping pattern (GP) (see Fig. 2B or 2D).
Lee-007 fails to teach:
and a gate contact penetrating the first interlayer dielectric layer, and being coupled to one of the first and second gate electrodes,
a first separation pattern extending in the second direction between the first gate electrode and the first dummy gate electrode,
wherein, in the first direction, the first separation pattern is between adjacent ones of the plurality of first source/drain patterns;
Cho teaches:
a gate contact (gate contact patterns GCP) penetrating the first interlayer dielectric layer (interlayer insulation layer 133) and being coupled to one of the first and second gate electrodes (gate metal pattern 115) (para. 42 “The gate contact patterns GCP may penetrate the interlayer insulation layer 133, the gap-fill insulation layer 131, and the capping insulation patterns 117 of the gate structures GS, and may be connected to the gate metal patterns 115”;
Lee-007 discloses the claimed invention except for a gate contact coupled to a gate electrode. Cho discloses that it is known in the art to provide a gate contact coupled to the gate electrode. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide the device of Lee-007 with the gate contact of Cho, in order to electrically connect the gate structure to external circuits and control the voltage applied to the gate. See MPEP 2144.
Lee-523 teaches in Figs. 27-31:
a separation pattern (diffusion prevention pattern 350) extending in the second direction (2nd direction of Lee-523) between the gate electrode (gate structure 320) and the first dummy gate electrode (para. 104, gate structure 320 that is formed on 160 to serve as a dummy gate structure),
wherein, in the first direction (1st direction of Lee-523), the separation pattern (350) is between adjacent ones of the plurality of first source/drain patterns (source/drain layers 264),
Lee-007/Cho discloses the claimed invention except for the separation pattern between the first/source drain patterns in the first direction and between the gate electrode and dummy gate electrode. Lee-523 teaches that it is known to include a separation pattern between the gate and dummy gate electrodes and adjacent S/D patterns in the first direction. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include the separation patterns as taught by Lee-523, since Lee-523 states in para. 104 that such a modification would reduce or prevent leakage currents from the gate electrodes. See MPEP 2144.
With respect to claim 17, Lee-007/Cho/Lee-523 does not teach:
further comprising a second separation pattern extending in the second direction between the second gate electrode and the second dummy gate electrode.
However, it would be obvious to the ordinary artisan that the benefits of adding the separation patterns of Lee-523 between the gate electrode and dummy gate electrode would be applicable to both dummy electrodes of Lee-007. Therefore, modifying Lee-007/Cho by Lee-523 to include separation patterns on both sides of the dummy electrodes teaches:
further comprising a second separation pattern extending in the second direction between the second gate electrode and the second dummy gate electrode.
With respect to claim 18, Lee-007/Cho/Lee-523 further teaches:
in the first direction, the second separation pattern is between adjacent ones of the plurality of second source/drain patterns (the separation pattern of Lee-523 is between adjacent S/D regions. Modifying the structure as applied to claim 17 on both sides of the device of Lee-007 meets the above limitation)
With respect to claim 19, Lee-007 further teaches:
further comprising a second gate spacer (blocking layer BL) on an upper sidewall of the first separation pattern (110 on left side).
With respect to claim 20, Lee-007 further teaches:
wherein the dummy gate spacer (GS on either side of dummy gates DE) of the first dummy gate electrode (DE on left) extends along the first sidewall (left) of the trench (TR) to contact a top surface of the device isolation layer (ST.)
Claims 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee-007 (US 2018/0083007 A1) and Lee-523 (2020/0243523 A1).
With respect to claim 11, Lee-007 teaches in Fig. 1:
A semiconductor device, comprising:
a first logic cell (portion of device to left of trench) and a second logic cell (portion of device to right of trench) on a substrate (substrate 100),
the first logic cell (RG1) and the second logic cell (RG2) being spaced apart from each other in a first direction (D2);
an isolation region (region between left and right side of device that includes trench TR) between the first logic cell (left side of device) and the second logic cell (right side of device);
a first active pattern (active pattern AP1) on the first logic cell (left side of device) and a second active pattern (active pattern AP2) on the second logic cell (right side of device);
a first channel pattern (channel portion CH1) on the first active pattern (AP1), and a second channel pattern (channel portion CH2) on the second active pattern (AP2);
a trench on the isolation region (trench TR);
a first dummy gate electrode (dummy gate electrode DE on left) adjacent to a first sidewall (left) of the trench (TR) and extending in a second direction (D1) intersecting the first direction (D2);
a gate electrode (gate electrode GE) extending in the second direction (D1) on the first logic cell (left side), and being spaced apart in the first direction (D2) from the first dummy gate electrode (DE on left);
wherein a first gate spacer (blocking layer BL) is on an upper sidewall of the separation pattern (110, see Fig. 2A).
The Examiner notes that Lee-007 refers to the logic cell regions as region RG1 and RG2 which are separated in the second direction D1, not D2 (para. 25) However, the grouping of the first and second logic cell regions is arbitrary and it would be reasonable to the ordinary artisan to consider the left side of the device to be the first logic cell region and the right side of the device the second logic cell region to meet the limitations above.
Lee-007 fails to teach:
and a separation pattern between the gate electrode and the first dummy gate electrode, the separation pattern extending in the second direction,
wherein in the first logic cell, the separation pattern is between adjacent first source/drain patterns in the first direction
Lee-523 teaches in Figs. 27-31:
a separation pattern (diffusion prevention pattern 350) between the gate electrode (gate structure 320) and the first dummy gate electrode (para. 104, gate structure 320 that is formed on 160 to serve as a dummy gate structure), the separation pattern extending in the second direction (2nd direction)
wherein, in the first logic cell, the separation pattern (350) is between adjacent ones of the plurality of first source/drain patterns (source/drain layers 264) in the first direction (1st direction),
Lee-007 discloses the claimed invention except for the separation pattern between the first/source drain patterns in the first direction and between the gate electrode and dummy gate electrode. Lee-523 teaches that it is known to include a separation pattern between the gate and dummy gate electrodes and adjacent S/D patterns in the first direction. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include the separation patterns as taught by Lee-523, since Lee-523 states in para. 104 that such a modification would reduce or prevent leakage currents from the gate electrodes. See MPEP 2144.
With respect to claim 12, Lee-007 further teaches:
further comprising:
a second gate spacer (gate spacer GS on side of electrode) on a sidewall of the gate electrode (GE);
and a dummy gate spacer (gate spacer GS on side of dummy gate electrode) on a sidewall of the first dummy gate electrode (DE),
wherein the dummy gate spacer extends along the first sidewall of the trench (TR) to contact a top surface of a device isolation layer (device isolation layer ST) in a lower portion of the trench (TR). (see Fig. 2A)
With respect to claim 13, Lee-523 teaches:
and the separation pattern (350) comprises silicon nitride .
Lee-007 does not describe what material is used for device isolation layer ST.
However, both silicon nitride and silicon oxide are dielectric materials commonly used in the art as insulating layers. Lee-007 teaches the use of silicon oxide and/or silicon nitride for various dielectric components of the device including the gate dielectric GI, gate spacer GS and gate capping pattern GP (para. 32).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to make the device isolation layer with silicon oxide and the separation pattern with silicon nitride, since it has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416.
With respect to claim 14, Lee-007 further teaches:
wherein the first dummy gate electrode (DE) comprises:
a body part;
a vertical part vertically and downwardly extending from the body part along the first sidewall of the trench (TR);
and a protruding part protruding from the vertical part toward one of the first source/drain patterns (SD1). (see annotated Fig. 2A above for body part, vertical part, and protruding part. The Examiner notes that for the purpose of claim 11 and its dependent claims the first dummy gate electrode was defined as the dummy gate electrode on the left, which is mirrored from the first dummy date electrode of claim 1 and its dependents and shown in the annotated Fig. 2A below)
With respect to claim 15, Lee-007 further teaches:
wherein the trench (TR) comprises a second sidewall (right sidewall) that faces the first sidewall (left),
and the semiconductor device further comprises a second dummy gate electrode (DE on right) extending in the second direction (D1), and being adjacent to the second sidewall (right of TR).
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897