DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/20/2025 has been entered.
Claims’ Status
Claims 1-15 and 21-25 are currently pending and being examined. Claims 1-2, 8, 11, and 25 have been amended. No claims have been newly added or newly cancelled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-10, 12, 14, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2017/0256551 A1, of record) in view of Zhang et al (US 2021/0193676 A1, of record, hereafter Zhang).
Re Claim 1, Lee discloses a three-dimensional (3D) memory device (FIG. 4; [0108]-[0119]), comprising:
a memory array structure (400; [0108]) comprising a first memory array structure (430.1, see FIG. Z1 below; [0108]) and a second memory array structure (430.2, see FIG. Z1; [0108]) each comprising a plurality of conductive/dielectric layer pairs (408; [0108]); and
a staircase structure (422; [0109]) between the first memory array structure (430.1) and the second memory array structure (430.2; [0109]) in a first lateral direction (direction along L-4; [0109]), the staircase structure (422) comprising a first staircase zone (420i-j; [0109]) and a second staircase zone (420k-p; [0109]) adjacent to the first staircase zone (420i-j) in a second lateral direction (direction along W-4; [0109]) perpendicular to the first lateral direction (direction along L-4; [0109]), wherein:
the first staircase zone (420i-j) comprises at least one staircase (420i-j; [0109]), the at least one staircase (420i-j) comprising a first staircase (subset of 420i, see FIG. Z2 below, hereafter just referred to as 420i for simplicity; [0109]) and a second staircase (subset of 420j, see FIG. Z2, hereafter just referred to as 420j for simplicity; [0109]) each comprising a plurality of stairs (424; [0113]), the first staircase (420i) and the second staircase (420j) being aligned in the first lateral direction (direction along L-4; [0109]);
the second staircase zone (420k-p) comprises a bridge structure (408 below 420k-p, see FIG. Z1; [0109]) and at least one other staircase (420k-p; [0109]) arranged over the bridge structure (408 below 420k-p; [0109]) and each comprising a plurality of stairs (424; [0113]), the at least one other staircase (420k-p) is adjacent to one of the first staircase (420i) and the second staircase (420j) in the second lateral direction (direction along W-4; [0109]-[0113]), the bridge structure (408 below 420k-p) connecting the first memory array structure (430.1) and the second memory array structure (430.2);
at least one stair (424) in the at least one staircase (420i-j) that comprises the first and second staircases (420i, 420j, respectively; [0113]), and the at least one stair (424) of the at least one staircase (420i-j), in the first staircase zone (420i-j), extends in the second lateral direction (direction along W-4; [0109]-[0113], as all the stairs extend in that direction); and
each stair (424) of the first staircase (420i) is positioned at a vertical depth different from any stair (424) of the second staircase (420j; [0109], see FIG. Z2).
Lee does not explicitly disclose:
at least one stair (424) in at least one staircase (420i-j) that comprises the first and second staircases (420i, 420j, respectively) is electrically connected to the bridge structure (408 below 420k-p), and the at least one stair (424) of the at least one staircase (420i-j), in the first staircase zone (420i-j), extends in the second lateral direction (direction along W-4) to be connected with a corresponding conductive portion of the bridge structure (408 below 420k-p) in the second staircase zone (420k-p); and
each stair (424) of the first staircase (420i) is electrically connected to the second memory array structure (430.2), adjacent to the second staircase (420j), through the bridge structure (408 below 420k-p).
However, Zhang teaches a memory device (FIG. 5, with reference to FIG. 4B; [0044]-[0049]), comprising:
at least one stair in at least one staircase (408A; [0044]) that comprises the first and second staircases (408A, 408B, respectively; [0044]) is electrically connected to the bridge structure (302b; [0044]), and the at least one stair of the at least one staircase (408A), in the first staircase zone (408A-408B), extends in the second lateral direction (Y-direction; [0047]) to be connected with a corresponding conductive portion of the bridge structure (302a) in the second staircase zone (302a, staircases above bridge structure taught by Lee; FIG. 4B; [0045]-[0047], extending in the Y-direction, current flows through the gap in slit structures 426, 428 via 302b); and
each stair of the first staircase (408A) is electrically connected to the second memory array structure (406b; [0045]), adjacent to the second staircase (408B; [0044]), through the bridge structure (302b; [0045]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the limitations taught by Lee with the limitations taught by Zhang to establish connection between the first staircase (Lee: 420i) and the second memory array structure (Lee: 430.2) to allow for current flow as taught by Zhang ([0045]).
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FIG. Z1: Annotated version of FIG. 4 of Lee
FIG. Z2: Annotated version of FIG. 4 of Lee
Re Claim 2, Lee and Zhang teach the device according to Claim 1, while Lee further discloses wherein the first staircase (420i) and the second staircase (420j) are aligned in the first lateral direction (direction along L-4; [0109]) and face each other ([0109]).
Re Claim 3, Lee and Zhang teach the device according to Claim 2, while Lee further discloses wherein:
the bridge structure (408 below 420k-p) comprises a plurality of conductive/dielectric portion pairs (408; [0109]); and
each pair of the conductive/dielectric portion pairs (408) each is in contact with a conductive/dielectric layer pair (408) of a same depth ([0109]) in each of the first memory array structure (430.1; [0109]) and the second memory array structure (430.2; [0109]).
Re Claim 4, Lee and Zhang teach the device according to Claim 2, while Zhang further teaches wherein:
each stair in the first staircase (408A) and the second staircase (408B) is in contact with a respective conductive/dielectric portion pair (“word line”/“insulating” layers; [0006]) in the bridge structure (302b; [0045]); and
each stair in the first staircase (408A) and the second staircase (408B) is electrically connected to a respective conductive/dielectric layer pair (“word line”/“insulating” layers) in each of the first memory array structure (406a; [0045]) and the second memory array structure (406b; [0045]) through the respective conductive/dielectric portion pair (“word line”/“insulating” layers) of the bridge structure (302b; [0045]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the limitations taught by Lee with the limitations taught by Zhang to establish connection between the first/second staircases (Lee: 420i, 420j, respectively) and the first/second memory array structure (Lee: 430.1, 430.2, respectively) to allow for current flow as taught by Zhang ([0045]).
Re Claim 5, Lee and Zhang teach the device according to Claim 2, while Lee further discloses wherein:
the at least one other staircase (420k-p) of the second staircase zone (420k-p) comprises a third staircase (420o; [0109]) and a fourth staircase (420p; [0109]) over the bridge structure (408 below 420k-p; [0109]); and
each stair (424) in the third staircase (420o) and the fourth staircase (420p) is in contact with and electrically connected to a respective conductive/dielectric layer pair (408) in one of the first memory array structure (430.1; [0109]) and the second memory array structure (430.2; [0109]).
Re Claim 6, Lee and Zhang teach the device according to Claim 5, while Lee further discloses wherein:
the third staircase (420o) and the fourth staircase (420p) have a same number of stairs (424; [0109]); and
at a same depth in a vertical direction (direction perpendicular to L-4 and W-4; [0109]), one of the stairs (424) in the third staircase (420o) and one of the stairs in the fourth staircase (420p) are conductively connected through a conductive line (436a; [0113]), and are respectively in contact with and electrically connected to conductive/dielectric layer pairs (408) of a same depth in one of the first memory array structure (430.1; [0109]) and the second memory array structure (430.2; [0109]).
Re Claim 7, Lee and Zhang teach the device according to Claim 2, while Lee further discloses wherein:
the at least one other staircase (420k-p) of the second staircase zone (420k-p) comprises a third staircase (420o; [0109]) and a fourth staircase (420p; [0109]) over the bridge structure (408 below 420k-p; [0109]); and
in a vertical direction (direction perpendicular to L-4 and W-4), the first staircase (420i) and the second staircase (420j) are lower than each of the third staircase (420o; [0109]) and the fourth staircase (420p; [0109]).
Re Claim 8, Lee and Zhang teach the device according to Claim 7, while Lee further discloses wherein a highest stair (424) in the first staircase (420i, see FIG. Z2) is lower than a lowest stair (424) of the second staircase (420j) by one conductive/dielectric portion pair (408) of the bridge structure (408 below 420k-p; see FIG. Z2; [0109]).
Re Claim 9, Lee and Zhang teach the device according to Claim 2, while Lee further discloses wherein:
the at least one other staircase (420k-p) of the second staircase zone (420k-p) comprises a third staircase (420o; [0109]) and a fourth staircase (420p; [0109]) over the bridge structure (408 below 420k-p; [0109]); and
each stair in the first staircase (420i), the second staircase (420j), the third staircase (420o), and the fourth staircase (420p) is defined by an edge of one conductive/dielectric pair (408; [0109]).
Re Claim 10, Lee and Zhang teach the device according to Claim 2, while Lee further discloses wherein: the at least one other staircase (420k-p) of the second staircase zone (420k-p) comprises a third staircase (420o; [0109]), a fourth staircase (420p; [0109]), a fifth staircase (420m; [0109]), and a sixth staircase (420n; [0109]) over the bridge structure (408 below 420k-p; [0109]), the fifth staircase (420m) being aligned with the third staircase (420o; [0109]) in the second lateral direction (direction along W-4; [0109]), the sixth staircase (420n) being aligned with the fourth staircase (420p; [0109]) in the second lateral direction (direction along W-4; [0109]), the fifth staircase (420m) and the sixth staircase (420n) each comprising a plurality of stairs (424; [0113]).
Re Claim 12, Lee and Zhang teach the device according to Claim 10, while Lee further discloses wherein in a vertical direction,
a highest stair (424) of the third staircase (420o) and a highest stair (424) of the fourth staircase (420p) are of a same depth ([0109]);
a highest stair (424) of the fifth staircase (420m) is lower than a highest stair (424) of the third staircase (420o) by one conductive/dielectric pair (408; [0109]); and
a highest stair (424) of the sixth staircase (420n) is lower than a highest stair (424) of the fourth staircase (420p) by one conductive/dielectric pair (408; [0109]).
Re Claim 14, Lee and Zhang teach the device according to Claim 12, while Lee further discloses wherein:
in the first lateral direction (direction along L-4), the third staircase (420o) faces the fourth staircase (420p; [0109]), and the fifth staircase (420m) faces the sixth staircase (420n; [0109]); and
at a same depth in the vertical direction (direction perpendicular to L-4 and W-4), one of the stairs (424) in the third staircase (420o) and one of the stairs (424) in the fourth staircase (420p) being conductively connected through a conductive line (436a; [0113]), one of the stairs (424) in the fifth staircase (420m) and one of the stairs (424) in the sixth staircase (420n) being conductively connected through another conductive line (436a; [0113], “at least one other”).
Re Claim 21, Lee and Zhang teach the device according to Claim 1, while Zhang further teaches wherein each stair in the first staircase (408A), located at a side closer to the first memory array structure (406a) in the first lateral direction (X-direction; [0044]), is electrically connected to the second memory array structure (406b) through the bridge structure (302b) of the second staircase zone ([0045], no explicit second staircase zone in Zhang, but would be taught through combination with Lee).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the limitations taught by Lee with the limitations taught by Zhang to establish connection between the first staircase (Lee: 420i) and the second memory array structure (Lee: 430.2) to allow for current flow as taught by Zhang ([0045]).
Re Claim 22, Lee and Zhang teach the device according to Claim 1, while Lee further discloses wherein each stair (424) of the plurality of stairs (424) in the first staircase (420i) is lower than any stair (424) of the plurality of stairs (424) in the second staircase (420j; [0109], see FIG. Z2), the second staircase (420j) being aligned with and facing the first staircase (420i) in the first lateral direction (direction along L-4; [0109]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lee and Zhang as applied to Claim 10 further in view of Kim et al (US 2019/0139978 A1, of record, hereafter Kim).
Re Claim 11, Lee and Zhang teach the device according to Claim 10, but they do not explicitly disclose wherein each stair in the first staircase (Lee: 420i), the second staircase (Lee: 420j), the third staircase (Lee: 420o), the fourth staircase (Lee: 420p), the fifth staircase (Lee: 420m), and the sixth staircase (Lee: 420n) is defined by an edge of two conductive/dielectric pairs (Lee: 408).
However, Kim teaches a device (FIGS. 8-9; [0076]-[0077]) wherein each stair (SST1, SST2; [0077]) is defined by an edge of two conductive/dielectric pairs (150, 160; [0077]).
While Kim does not explicitly disclose a device in which the first through sixth staircases are defined by an edge of two conductive/dielectric pairs, one having ordinary skill in the art would recognize the teaching of having steps for each staircase (Kim: SST1, SST2) defined by an edge of two conductive/dielectric pairs (Lee: 408). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device discussed for Claim 7 with the limitations taught by Zhou to incorporate this teaching to allow sufficient space for requisite contacts, as taught by Kim ([0077]).
Allowable Subject Matter
Claims 24-25 are allowed.
Claims 13, 15, and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Re Claim 13, the prior art cannot anticipate, or render obvious the limitations of: wherein in a vertical direction, a highest stair in the first staircase is lower than a highest conductive/dielectric portion pair of the second staircase by one conductive/dielectric pair, in combination with the additionally claimed features of Claim 13.
Re Claim 15, the prior art cannot anticipate, or render obvious the limitations of: in the first lateral direction, the third staircase faces the sixth staircase, and the fourth staircase faces the fifth staircase, in combination with the additionally claimed features of Claim 15.
Re Claim 23, the prior art cannot anticipate, or render obvious the limitations of: the plurality of stairs of the first staircase and the plurality of stairs of the second staircase are arranged at alternating vertical levels in a vertical direction, in combination with the additionally claimed features of Claim 23.
Re Claim 24, the prior art cannot anticipate, or render obvious, the limitations of: a highest stair in the first staircase is lower than a highest conductive/dielectric portion pair of the second staircase by one conductive/dielectric pair, in combination with the additionally claimed features of Claim 24.
Re Claim 25, the prior art cannot anticipate, or render obvious, the limitations of: the plurality of stairs of the first staircase and the plurality of stairs of the second staircase are arranged at alternating vertical levels in a vertical direction perpendicular to the first lateral direction and the second lateral direction, in combination with the additionally claimed features of Claim 25.
Response to Arguments
Applicant’s arguments concerning the amended portions of Claim 1 that “this structure [318/418] prevents 420i-j (allegedly corresponding to the claimed “first staircase zone”) and 420k-p (allegedly corresponding to the claimed “second staircase zone”) from being adjacent to each other” (Remarks – 11/20/2025, pg. 3, para. 3) are not persuasive because the presence of openings 318/418 as described in Lee do not prevent the first staircase zone 420i-j and the second staircase zone 420k-p from being adjacent to each other, as adjacency does not necessarily require physical contact. In incorporation with Zhang, electrical connection is explicitly done through such openings (see Zhang: [0045]), therefore satisfying both amended limitations and disproving that Lee’s openings teach away from said amended limitations (see rejection of Claim 1 above).
Applicant’s request for reconsideration, see Remarks pg. 4, para. 1, filed 11/20/2025, with respect to Claim 25 has been fully considered and is persuasive. The rejection of Claim 25 has been withdrawn.
Also, to date, no specific arguments against the rejections of Claims 2-12 and 14, which depend from Claim 1, have been presented beyond they are allowable due to their dependencies from Claim 1. Therefore, the examiner offers no response at this time.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLIN RUSSELL MCCUTCHEON whose telephone number is (703)756-1897. The examiner can normally be reached Monday-Friday, 12:30-9:30 EST.
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/COLIN RUSSELL MCCUTCHEON/Examiner, Art Unit 2892
/LEX H MALSAWMA/Primary Examiner, Art Unit 2892