DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (claims 1-19) in the reply filed on November 11, 2025 is acknowledged. Claims 20-26 drawn to non-elected invention have been withdrawn from examination.
Information Disclosure Statement
The information disclosure statement (IDS) filed on July 20, 2022 and IDS filed on April 27, 2023 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDSs are considered by the examiner.
Claim Objections
Claims 3, 5, 6 and 12 are objected to because of the following informalities:
In claim 3, line 3, “a 3D-printing process” should read --a three-dimensional (3D) printing process--.
In claim 5, lines 2-3, “after forming the support structure” should read -- after providing the support structure--. Support can be found at least in lines 5-6 of the base claim 1.
In claim 6, lines 2-3, “a diameter of a semiconductor wafer by at most ±1 % of the diameter of a semiconductor wafer” should read --a diameter of the semiconductor wafer by at most ±1 % of the diameter of the semiconductor wafer--.
In claim 12, line 2, “forming a splitting region” should read --forming the splitting region--. Support can be found at least in line 3 of the intervening claim 9.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 17 recites the feature “after thinning the semiconductor wafer in lines 2-3. There is insufficient antecedent basis for the feature in the claim and base claim 1. For examination purposes, claim 17 is considered as the claim does not include the above feature.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4, 6, 8, 16 and 19 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by MaCutcheon et al. US 2014/0130969.
Regarding claim 1, MaCutcheon teaches a method for processing a semiconductor wafer (e.g., Fig. 4, [35]-[38]; also see Figs. 1-3 and the description thereof for further reference and details), the method comprising:
reducing a thickness of the semiconductor wafer (e.g., backside grinding or chemical mechanical polishing the semiconductor wafer 14 on the second side 16b of the wafer 14; [37]; [22]);
before or after reducing the thickness of the semiconductor wafer, placing a carrier structure at a first side of the semiconductor wafer (e.g., before the backside grinding or chemical mechanical polishing, placing the carrier structure 22A at the first side 16a of the wafer 14, [37]; Fig. 4(d)); and
after reducing the thickness of the semiconductor wafer, providing a support structure at a second side of the semiconductor wafer opposite to the first side (e.g., providing a support structure 22B at the second side 16b opposite to the first side 16a; [38]; Fig. 4(e)).
Regarding claim 2, MaCutcheon teaches the method of claim 1, wherein the support structure is attached to the second side of the semiconductor wafer by at least one of: gluing, bonding, adhesive bonding, laser melting, laser bonding, and soldering (e.g., attaching by the adhesive bonding of 32, [27], [28], [37]).
Regarding claim 4, MaCutcheon teaches the method of claim 1, wherein the support structure comprises at least one of glass, sapphire, silicon, ceramic, carbon, plastic, and metal (e.g., [24]).
Regarding claim 6, MaCutcheon teaches the method of claim 1, wherein an outer diameter of the support structure (e.g., 200 mm, [44]) differs from a diameter of a semiconductor wafer by at most ±1 % of the diameter of a semiconductor wafer (e.g., 200 mm, [57]).
Regarding claim 8, MaCutcheon teaches the method of claim 1, wherein a thickness of the semiconductor wafer is at most 300 µm after reducing the thickness of the semiconductor wafer (e.g., 30 µm, [57]).
Regarding claim 16, MaCutcheon teaches the method of claim 1, further comprising: removing the support structure from the second side of the semiconductor wafer (e.g., [38]; [42]).
Regarding claim 19, MaCutcheon teaches a method for processing a semiconductor wafer (e.g., Fig. 4, [35]-[38]; also see Figs. 1-3 and the description thereof for further reference and details), the method comprising:
attaching a carrier structure (e.g., 22A, Fig. 4(d)) to a front side of the semiconductor wafer (e.g., 16a of 14, Fig. 4(d); [22]); and
providing a support structure (e.g., 22B, Fig. 4(e)) at a back side of the semiconductor wafer (e.g., 16b of 14, Fig. 4(d); [22]).
Claims 1, 5, 15 and 18 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by MaCutcheon et al. US 2014/0130969.
Regarding claim 1, MaCutcheon teaches a method for processing a semiconductor wafer (e.g., Fig. 3, [34]; also see Figs. 1-3 and the description thereof for further reference and details), the method comprising:
reducing a thickness of the semiconductor wafer (e.g., reducing a thickness of the semiconductor wafer 10 including 14 thereon at the second side of the wafer opposite to the first side of the wafer at which 14’ are disposed, Fig. 3(g); [21], [22]);
before or after reducing the thickness of the semiconductor wafer, placing a carrier structure at a first side of the semiconductor wafer (e.g., before the reducing, the carrier structure 22 at the first side of the wafer, Fig. 3(f)); and
after reducing the thickness of the semiconductor wafer, providing a support structure at a second side of the semiconductor wafer opposite to the first side (e.g., providing a support structure 46 at the second side of the wafer; Fig. 3(i)).
Regarding claim 5, MaCutcheon teaches the method of claim 1, wherein a cross-sectional area of the support structure comprises an inner step (e.g., inner step of 46 in which the wafer is located, Fig. 3(i)), wherein the semiconductor wafer is located on the inner step after forming the support structure (e.g., Fig. 3(i)).
Regarding claim 15, MaCutcheon teaches the method of claim 1, further comprising: before reducing the thickness of the semiconductor wafer, forming an epitaxial semiconductor layer on the first side of the semiconductor wafer (e.g., 14 on the first side of 10, Figs. 3(a)-(b), [22]).
Regarding claim 18, MaCutcheon teaches the method of claim 1, wherein a height of the support structure varies along a circumference of the support structure (e.g., Fig. 3(i)).
Claims 1 and 9 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Kubota et al. US 2018/0334757.
Regarding claim 1, Kubota teaches a method for processing a semiconductor wafer (e.g., (e.g., Fig. 1, [48]-[84]), the method comprising:
reducing a thickness of the semiconductor wafer (e.g., reducing a thickness of the semiconductor wafer (item in Fig. 1(c), [49]); Fig. 1(e));
before or after reducing the thickness of the semiconductor wafer, placing a carrier structure at a first side of the semiconductor wafer (e.g., before the reducing, placing a carrier structure 21 at a first side of the semiconductor wafer at which 21 is attached, Fig. 1(d)); and
after reducing the thickness of the semiconductor wafer, providing a support structure at a second side of the semiconductor wafer opposite to the first side opposite to the first side (e.g., providing a support structure 11 at a second side of the semiconductor wafer opposite to the first side, Fig. 1(g)).
Regarding claim 9, Kubota teaches the method of claim 1, wherein reducing the thickness of the semiconductor wafer comprises thinning the semiconductor wafer by at least one of grinding, laser ablation, etching the semiconductor wafer (e.g., [72]), and splitting the semiconductor wafer along a splitting region (e.g., 12i, Fig. 1(e), Fig. 1(c); [68]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 7, 14 and 17 are rejected are rejected under 35 U.S.C. 103 as being unpatentable over MaCutcheon et al. US 2014/0130969.
Regarding claim 3, MaCutcheon teaches the method of claim 1 as discussed above
MaCutcheon does not explicitly teach wherein the support structure is deposited at the second side of the semiconductor wafer with a 3D-printing process.
It has been well known in the art that three-dimensional (3D) shaped structures may be formed by 3D printing processes.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of MaCutcheon to include wherein the support structure is deposited at the second side of the semiconductor wafer with a 3D-printing process for the purpose of reducing the manufacturing steps and costs for example.
Regarding claim 7, MaCutcheon teaches the method of claim 1 as discussed above.
MaCutcheon does not explicitly teach wherein, in a cross-section, the support structure has a maximum height of at most 3 mm and at least 0.1 mm and/or a maximum width of at most 50 mm and at least 3 mm.
MaCutcheon, however, recognizes that the silicon wafer 22B (considered as a support structure) has 200-mm diameter (e.g., [44]).
It has been well known in the art that a semiconductor wafer in industry standards may have 200 mm in diameter and around 300 µm in thickness, which overlaps the claimed range.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to optimize and control the method of MaCutcheon to have the claimed range for the purpose of the conventional use of the wafer for example.
Regarding claim 14, MaCutcheon teaches the method of claim 1 as discussed above.
MaCutcheon does not explicitly teach the method further comprising: forming at least a part of at least one electrical element structure on the semiconductor wafer; and/or performing electrical testing of the at least one electrical element structure formed on the semiconductor wafer while the semiconductor wafer is mechanically supported by the support structure.
MaCutcheon, however, recognizes that the device layer 14 is formed on the semiconductor wafer 10 (e.g., [21], [22]).
It has been well known in the art that device layers often refer to the functional layers of printed circuit boards or integrated circuits.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that in MaCutcheon the device layer 14 may include various small electronics devices and integrated circuits for the purpose of obtaining a complete semiconductor wafer package for example.
Regarding claim 17, MaCutcheon teaches the method of claim 1 as discussed above.
MaCutcheon does not explicitly teach wherein a maximum height of the support structure in a cross-section of the support structure is larger than a thickness of the semiconductor wafer after thinning the semiconductor wafer.
MaCutcheon, however, recognizes that the wafer 22B (considered as a support structure) has 200-mm diameter (e.g., [44]) and the wafer 14 (considered as a semiconductor wafer) has a thickness of 30 µm (e.g., [57]) after thinning the semiconductor wafer (see the 112 rejection above).
It has been well known in the art that a semiconductor wafer in industry standards may have 200 mm in diameter and around 300 µm in thickness.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to optimize and control the method of MaCutcheon to have the well-known thickness for the purpose of the conventional use of the wafer for example.
Allowable Subject Matter
Claims 10, 11 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if amended to overcome the claim objection, set forth in this Office action.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bo Bin Jang whose telephone number is (571) 270-0271. The examiner can normally be reached on M-F from 9:00 AM to 6:00 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://portal.uspto.gov/external/portal. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) OR 571-272-1000.
/BO B JANG/Primary Examiner, Art Unit 2818 January 23, 2026