DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
An amendment filed on 12/17/2025 in response to the Office Action mailed on 09/19/2025 is
being acknowledged and entered into the record. The present Final rejection is made by taking into fully consideration all the amendments.
Response to Arguments
On pages 9-11 of the remarks, filed 12/17/2025, with respect to the rejection of Claims 1, Applicant argues that the cited prior art fails to disclose “one or more front-side logic devices that are at least partly arranged in a front-side of the semiconductor layer.” Applicant further argues that the logic circuitry disclosed (see paragraph 0255 of Or-Bach) is not part of the acceptor wafer 808/9510 and the relative location of the circuitry within the wafer is not disclosed and thus fails to teach or suggest the circuitry is arranged in the front-side of the semiconductor layer. These arguments are fully considered but are not persuasive. MPEP § 2111 discusses proper claim interpretation, including giving claims their broadest reasonable interpretation in light of the specification during examination. Under broadest reasonable interpretation, the words of a claim must be given their plain meaning unless such meaning is inconsistent with the specification, and it is improper to import claim limitations from the specification into the claim. As such, the claim limitation “at least partially arranged” is broad and doesn’t describe “any relative location of circuitry within a wafer” only that there are parts of circuits on a side of a wafer. Additionally, according to the last line of paragraph 0623 of Or-Bach, the semiconductor layer 9510 is similar to semiconductor layer 808 of a different embodiment. Further, paragraph 0255 clearly mentions the acceptor wafer 808 comprises one or more logic devices. While the exact location of these logic devices is not explicitly disclosed, according to MPEP § 2144.04 (VI) under (C) Rearrangement of Parts, claims which read on the prior art except with regard to the placement of a component is unpatentable as it is an obvious matter of design choice. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice). As such, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have arranged the one or more logic devices in a front-side of the semiconductor layer. Therefore, the rejection of Claim 1 and all dependent claims has been maintained.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6, 9, 11-13, 16, 17, 20 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach et al. (US 20110084314 A1), in view of Bakeroot (EP 3627559 A1).
Regarding Claim 1, Or-Bach et al. discloses a semiconductor structure comprising:
a semiconductor layer 9510 (Fig. 95J: 9510, paragraph 0623);
one or more front-side logic devices that are at least partly arranged in a front-side of the semiconductor layer 9510 (paragraphs 0255, 0623);
Note that according to the last line of paragraph 0623, the semiconductor layer 9510 is similar to semiconductor layer 808 of a different embodiment, which comprises the one or more front-side logic devices as stated in paragraph 0255.
While the exact location of these logic devices is not explicitly disclosed, according to MPEP § 2144.04 (VI) under (C) Rearrangement of Parts, claims which read on the prior art except with regard to the placement of a component is unpatentable as it is an obvious matter of design choice. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice).
at least four epitaxial layers 9518, 9516, 9534, 9533 arranged on a back-side of the semiconductor layer 9510 (Fig. 95J: 9510, 9518, 9516, 9534, 9533, paragraphs 0622, 0623, 0625, 0631),
wherein the four epitaxial layers 9518, 9516, 9534, 9533 comprise a first epitaxial layer 9518 of a first conductivity type (n-type), a second epitaxial layer 9516 of a second conductivity type (p-type) provided on the first epitaxial layer 9518, a third epitaxial layer 9534 of the second conductivity type (p-type) provided on the second epitaxial layer 9516, and a fourth epitaxial layer 9533 of the first conductivity type (n-type) provided on the third epitaxial layer 9534 (Fig. 95J: 9518, 9516, 9534, 9533, paragraphs 0622, 0623, 0625, 0631);
and a plurality of back-side contacts 9562, 9566, 9572, 9576, 9556’, 9554’ that are exposed at a back-side surface of the fourth epitaxial layer 9533 (Fig. 95J: 9562, 9566, 9572, 9576, 9556’, 9554’, paragraph 0631), wherein the plurality of back-side contacts 9562, 9566, 9572, 9576, 9556’, 9554’ comprise:
a set of first terminal contacts 9562, 9566 electrically contacting the fourth epitaxial layer 9533 (Fig. 95J: 9562, 9566, 9533, paragraph 0631);
a set of second terminal contacts 9572, 9576 electrically contacting the second epitaxial layer 9516 (Fig. 95J: 9572, 9576, 9516, paragraph 0631);
a set of first gate contacts 9556’, 9564 extending into the third epitaxial layer 9534 (Fig. 95J: 9556’, 9534, paragraph 0631);
and a set of second gate contacts 9554’, 9574 extending into the first epitaxial layer 9518 (Fig. 95J: 9554’, 9518, paragraph 0631).
Or-Bach et al. fails to explicitly teach the set of first terminal contacts 9562, 9566 extending into the fourth epitaxial layer 9533, the set of second terminal contacts 9572, 9576 extending into the second epitaxial layer 9516.
However, Bakeroot discloses a semiconductor structure comprising a set of first terminal contacts 26 extending into the fourth epitaxial layer 20 and a set of second terminal contacts 27 extending into the second epitaxial layer 19 (Fig. 2: 27, 26, 19, 20, Fig. 1: 27, 26, 20, paragraph 0026, 0027, 0031).
Therefore, a person of ordinary skill in the art, would have combined the teachings of Or-Bach et al. and Bakeroot in order to have the set of first terminal contacts extending into the fourth epitaxial layer and the set of second terminal contacts extending into the second epitaxial layer. Doing so would ensure the contacts reach the doped regions of the respective epitaxial layers thereby realizing ohmic contact.
Regarding Claim 2, Or-Bach et al. teaches the semiconductor structure according to claim 1, wherein: the set of second terminal contacts 9572, 9576 is electrically isolated from the third epitaxial layer 9534 and the fourth epitaxial layer 9533 (an oxide layer 9550 is used for electrical isolation as shown in Fig. 95J and paragraph 0628); the set of first gate contacts 9556’, 9564 is electrically isolated from the third epitaxial layer 9534 and the fourth epitaxial layer 9533 (an oxide layer 9512 is used for electrical isolation as shown in Fig. 95J and paragraph 0630); and the set of second gate contacts 9554’, 9574 is electrically isolated from the first epitaxial layer 9518, the second epitaxial layer 9516, the third epitaxial layer 9534, and the fourth epitaxial layer 9533 (oxide layers 9511 and 9550 is used for electrical isolation as shown in Fig. 95J and paragraphs 0627, 0630).
Regarding Claim 3, Or-Bach et al. teaches the semiconductor structure according to claim 1, further comprising: a first-conductivity-type (n-type) MOS device formed by a first gate contact 9556’ of the set of first gate contacts 9556’, 9564 configured as a first gate of the first-conductivity-type MOS device and two first terminal contacts 9562, 9566 of the set of first terminal contacts 9562, 9566 configured as a first source and a first drain of the first-conductivity-type MOS device (Fig. 95J, paragraphs 0631, 0633).
Regarding Claim 6, Or-Bach et al. teaches the semiconductor structure according to claim 1, further comprising: a second-conductivity-type (p-type) MOS device formed by a second gate contact 9554’ of the set of second gate contacts 9554’, 9574 configured as a second gate of the second-conductivity type MOS device and two second terminal contacts 9572, 9576 of the set of second terminal contacts 9572, 9576 configured as a second source and a second drain of the second-conductivity-type MOS device (see below annotated Fig. 95J, paragraphs 0631, 0633).
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Annotated Fig. 95J of Or-Bach et al. (US 20110084314 A1).
Regarding Claim 9, Or-Bach et al. teaches the semiconductor structure according to claim 6, wherein the back-side surface of the fourth epitaxial layer 9533 is divided into one or more first-conductivity type areas and one or more second-conductivity-type areas by a plurality of intersecting isolation structures 9520, 9552, wherein each of the one or more first-conductivity type areas comprises one first- conductivity-type (n-type) MOS device and each of the one or more second-conductivity-type areas comprises one second-conductivity-type (p-type) MOS device (see above annotated Fig 95J, paragraph 0631).
Regarding Claim 11, Or-Bach et al. teaches the semiconductor structure according to claim 1, further comprising: one or more isolation structures 9520 extending into the first epitaxial layer 9518 and being either an isolation gates formed by second gate contact of the set of second gate contacts or being a shallow trench isolation (Fig. 95J: 9520, 9518, paragraphs 0625, 0631).
Regarding Claim 12, Or-Bach et al. teaches the semiconductor structure according to claim 11, comprising a first-conductivity-type (n-type) MOS device and a second-conductivity-type (p-type) MOS device that are separated from each other by at least one of the isolation structures 9520 (see above annotated Fig. 95J of Or-Bach et al.: 9520, paragraphs 0631, 0632).
Regarding Claim 13, Or-Bach et al. teaches the semiconductor structure according to claim 1, wherein: the fourth epitaxial layer 9533 has a higher doping concentration (doped N+) of first conductivity type (n-type) dopants than the first epitaxial layer 9518 (doped N-); and/or the second epitaxial layer 9561 has a higher doping concentration (doped P+) of second conductivity type (p-type) dopants than the third epitaxial layer 9534 (doped P-) (Fig. 95J, paragraph 0622).
Regarding Claim 16, Or-Bach et al teaches a device comprising a semiconductor structure according to claim 1 (see rejection of Claim 1 above); and further in a different embodiment, teaches one or more back-side semiconductor devices (3D-DRAM) that are coupled to the plurality of back- side contacts of the semiconductor structure (paragraph 0404).
Therefore, a person of ordinary skill in the art would have modified the teachings of Or-Bach et al. to have one or more back-side semiconductor devices that are coupled to the plurality of back- side contacts of the semiconductor structure. Doing so would enable the integration of both back-side and font-side semiconductor devices into a single electronic die, yielding a compact form factor with reduced manufacturing and assembly costs.
Regarding Claim 17, Or-Bach et al. teaches a method for fabricating a semiconductor structure, the method comprising:
forming a semiconductor layer 9510 (Fig. 95J: 9510, paragraph 0623) and four epitaxial layers 9518, 9516, 9534, 9533 on a back-side of the semiconductor layer (Fig. 95J: 9510, 9518, 9516, 9534, 9533, paragraphs 0622, 0623, 0625, 0631);
forming one or more front-side logic devices that are at least partly arranged in a front- side of the semiconductor layer 9510 (paragraphs 0255, 0623);
wherein the four epitaxial layers 9518, 9516, 9534, 9533 comprise a first epitaxial layer 9518 of a first conductivity type (n-type), a second epitaxial layer 9516 of a second conductivity type (p-type) provided on the first epitaxial layer 9518, a third epitaxial layer 9534 of the second conductivity type (p-type) provided on the second epitaxial layer 9516, and a fourth epitaxial layer 9533 of the first conductivity type (n-type) provided on the third epitaxial layer 9534 (Fig. 95J: 9518, 9516, 9534, 9533, paragraphs 0622, 0623, 0625, 0631);
and forming a plurality of back-side contacts 9562, 9566, 9572, 9576, 9556’, 9554’ that are exposed at a back-side surface of the fourth epitaxial layer 9533 (Fig. 95C-95J: 9562, 9566, 9572, 9576, 9556’, 9554’, paragraph 0631),
the plurality of back-side contacts 9562, 9566, 9572, 9576, 9556’, 9554’ comprise:
a set of first terminal contacts 9562, 9566 electrically contacting the fourth epitaxial layer 9533 (Fig. 95J: 9562, 9566, 9533, paragraph 0631);
a set of second terminal contacts 9572, 9576 electrically contacting the second epitaxial layer 9516 (Fig. 95J: 9572, 9576, 9516, paragraph 0631);
a set of first gate contacts 9556’, 9564 extending into the third epitaxial layer 9534 (Fig. 95J: 9556’, 9534, paragraph 0631);
and a set of second gate contacts 9554’, 9574 extending into the first epitaxial layer 9518 (Fig. 95J: 9554’, 9518, paragraph 0631).
Or-Bach et al. fails to explicitly teach the set of first terminal contacts 9562, 9566 extending into the fourth epitaxial layer 9533, the set of second terminal contacts 9572, 9576 extending into the second epitaxial layer 9516.
However, Bakeroot discloses a semiconductor structure comprising a set of first terminal contacts 26 extending into the fourth epitaxial layer 20 and a set of second terminal contacts 27 extending into the second epitaxial layer 19 (Fig. 2: 27, 26, 19, 20, Fig. 1: 27, 26, 20, paragraph 0026, 0027, 0031).
Therefore, a person of ordinary skill in the art, would have combined the teachings of Or-Bach et al. and Bakeroot in order to have the set of first terminal contacts extending into the fourth epitaxial layer and the set of second terminal contacts extending into the second epitaxial layer. Doing so would ensure the contacts reach the doped regions of the respective epitaxial layers thereby realizing ohmic contact.
Regarding Claim 20, Or-Bach et al. teaches the method according to claim 17, wherein forming the semiconductor layer 9510 and the four epitaxial layers 9518, 9516, 9534, 9533 on the back-side of the semiconductor layer 9510 comprises:
providing a semiconductor substrate 9500 (Fig. 95A:9500, paragraph 0622);
forming the four epitaxial layers 9503, 9504, 9506, 9508, starting with the fourth epitaxial layer 9503, on the semiconductor substrate 9500 (Fig. 95A:9500, 9503, 9504, 9506, 9508, paragraph 0622);
(Note that the epitaxial layers 9503, 9504, 9506, 9508, are later reindexed as 9533, 9534, 9516, 9508, respectively, in the finished device following processing steps shown in Fig. 95A – 95J.)
forming the semiconductor layer 9510 on the first epitaxial layer 9508 (Fig. 95C: 9510, 9508, paragraph 0625);
and thinning the semiconductor substrate 9500 to the fourth epitaxial layer 9503, which serves as an etch stop layer (paragraph 0623).
Regarding Claim 21, Or-Bach et al. teaches the semiconductor structure according to claim 1, wherein: the set of second terminal contacts 9572, 9576 extend through the fourth epitaxial layer 9533 and through the third epitaxial layer 9534, and the set of second gate contacts 9574, 9554’ extend through the fourth epitaxial layer 9533, through the third epitaxial layer 9534, and through the second epitaxial layer 9516 (Fig. 95J: 9572, 9576, 9574, 9554’, 9533, 9534, 9156).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach et al. (US 20110084314 A1), in view of Bakeroot (EP 3627559 A1), as applied to Claim 3 above, further in view of Williams et al. (US 20080061367 A1).
Regarding Claim 5, Or-Bach et al. teaches the semiconductor structure according to claim 3, wherein: the first-conductivity-type MOS device further comprises a first bulk contact formed by a second terminal contact of the set of second terminal contacts (Last line of paragraph 0631 mentions that a plurality of contacts are formed in the second epitaxial layer 9516 which are not shown in Fig. 95J).
Or-Bach et al. fails to teach a first top contact formed by a first terminal contact of the set of first terminal contacts.
However, Williams et al. teaches a semiconductor structure having a MOS device including a first top contact 291C formed by a first terminal contact of the set of first terminal contacts 291A, 291B, 291C (Fig. 9: 291A, 291B, 291C).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention would have combined the teachings of Or-Back et al. with the teachings of Williams et al. in order to come up with the claimed invention. Doing so would increase the breakdown voltage of the MOS device, as recognized by Williams et al. (paragraph 0145).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach et al. (US 20110084314 A1), in view of Bakeroot (EP 3627559 A1), as applied to Claim 6 above, further in view of Williams et al. (US 20080061367 A1).
Regarding Claim 8, Or-Bach et al. teaches the semiconductor structure according to claim 6, wherein: the second-conductivity-type MOS device further comprises a second bulk contact formed by a second terminal contact of the set of second terminal contacts (Last line of paragraph 0631 mentions that a plurality of contacts are formed in the third epitaxial layer 9516 which are not shown in Fig. 95J).
Or-Bach et al. fails to teach a second top contact formed by a first terminal contact of the set of first terminal contacts.
However, Williams et al. teaches a semiconductor structure having a MOS device including a first top contact 291C formed by a second terminal contact of the set of second terminal contacts 291A, 291B, 291C (Fig. 9: 291A, 291B, 291C).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention would have combined the teachings of Or-Back et al. with the teachings of Williams et al. in order to come up with the claimed invention. Doing so would increase the breakdown voltage of the MOS device, as recognized by Williams et al. (paragraph 0145).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach et al. (US 20110084314 A1), in view of Bakeroot (EP 3627559 A1), as applied to Claim 6 above, further in view of Yang et al. (US 20070020858 A1).
Regarding Claim 10, Or-Bach et al. fails to teach the semiconductor structure according to claim 6, further comprising: two shallow trench isolations (STIs) extending in parallel along a first direction; two isolation gates extending in parallel along a second direction, which is perpendicular to the first direction, and intersecting with the two STIs; and a first-conductivity-type area or a second-conductivity-type area formed within the two STIs and two isolation gates.
However, Yang et al. teaches a semiconductor structure comprising two shallow trench isolations (STIs) ST1, ST2 extending in parallel along a first direction; two isolation gates 30, 31 extending in parallel along a second direction, which is perpendicular to the first direction, and intersecting with the two STIs ST1, ST2; and a first-conductivity-type area or a second-conductivity-type area 1, 3, 5 formed within the two STIs ST1, ST2 and two isolation gates 30, 31 (Fig. 10: 30, 31, 32, 33, ST1, ST2, 1, 3, 5, paragraphs 0047 and 0048).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention would have combined the teachings of Or-Back et al. with the teachings of Yang et al. in order to come up with the claimed invention. Doing so would electrically isolate the MOS devices from all sides and provide insulation between transistors, as recognized by Yang et al. (paragraphs 0047, 0051).
Claims 15 is rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach et al. (US 20110084314 A1), in view of Bakeroot (EP 3627559 A1), as applied to Claim 1 above, further in view of Suh (US 20060138477 A1).
Regarding Claim 15, while Or-Bach et al teaches the semiconductor structure according to claim 1, wherein a first gate contact 9556’ of the set of first gate contacts and/or a second gate contact 9554’ of the set of second gate contacts are formed, respectively, within the third epitaxial layer 9534 and/or the first epitaxial layer 9518, it fails to explicitly teach that these gate contacts have a flat tip formed.
However, Suh teaches a MOSFET structure comprising a plurality of first gate contacts 112, 114 having a flat tip formed (Fig. 2: 112, 114, paragraph 0028).
Therefore, a person of ordinary skill in the art would have modified the teachings of Or-Bach et al. with the teachings of Suh to have a first gate contact of the set of first gate contacts and/or a second gate contact of the set of second gate contacts of Or-Bach et al. have a flat tip formed. Doing so would simplify the fabrication process without the need for additional etching steps to fabricate non-flat tips such as rounded or triangular tips.
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach et al. (US 20110084314 A1), in view of Bakeroot (EP 3627559 A1), as applied to Claim 17 above, further in view of Chen et al. (US 20220028994 A1).
Regarding Claim 18, Or-Bach et al. teaches the method according to claim 17, wherein forming the semiconductor layer 9510 and the four epitaxial layers 9518, 9516, 9534, 9533 on the back-side of the semiconductor layer 9510 comprises (Fig. 95J:
providing a semiconductor substrate 9500;
forming an etch stop layer on the semiconductor substrate 9500 (paragraph 0268);
forming the four epitaxial layers 9508, 9506, 9504, 9503, starting with the fourth epitaxial layer 9503, on the etch stop layer (Fig. 95A: 9503, 9504, 9506, 9508, paragraphs 0622, 0268);
(Note that the epitaxial layers 9503, 9504, 9506, 9508, are later reindexed as 9533, 9534, 9516, 9508, respectively, in the finished device following processing steps shown in Fig. 95A – 95J.)
forming the semiconductor layer 9510 on the first epitaxial layer 9518 (Fig. 95C: 9510, 9508, paragraph 0625);
thinning the semiconductor substrate 9500 to the etch stop layer (paragraph 0268);
Note that While Or-Bach et al. fails to explicitly teach forming an etch stop layer in the process illustrated by Fig. 95a-95J, in paragraph 0268, it is mentioned that a silicon germanium layer may be utilized as an etch stop on the donor wafer, which is equivalent to the semiconductor substrate that may be preferentially etched away until the etch stop layer is reached.
Furthermore, Or-Bach et al. fails to explicitly teach removing the etch stop layer.
However, Chen et al. teaches a method of forming a semiconductor structure, comprising forming a silicon germanium etch stop layer 17 on the semiconductor substrate 11 (Fig. 2A: 11, 17, paragraphs 0022, 0024) and removing the etch stop layer 17 later in the process (paragraph 0025).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the teachings of Or-Bach et al. with the teachings of Chen et al. and remove the etch stop layer of Or-Bach et al. Doing so would expose the backside of the semiconductor layers for back-end processing.
Regarding Claim 19, Or-Bach et al. teaches the method according to claim 18, wherein: each of the four epitaxial layers 9518, 9516, 9534, 9533 comprises silicon; and/or the etch stop layer is formed on the semiconductor substrate 9500 and comprises silicon germanium (paragraph 0268, 0622).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNA F IQBAL whose telephone number is 571-272-1587. The examiner can normally be reached M-F: 8.30 am - 5.30 pm EST.
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/HAMNA FATHIMA IQBAL/Examiner, Art Unit 2817 05/02/2026
/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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