DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in
Europe (EP 21187116.5) on July 22, 2021. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Arguments
Applicant’s arguments, see pages 1-3 of the remarks made in the pre-appeal brief filed on 08/11/2026, with respect to the 103 rejection of claim 1, have been fully considered and are persuasive. Thus, the finality of the office action dated 04/10/2026 is withdrawn and prosecution is re-opened. Further, the previous rejection of claim 1 has been withdrawn. However, upon further consideration, a new grounds of 103 rejection is made in view of previously applied prior art references and newly found prior reference of Lee and Munging et al. The combination of OR-Bach/Lee/Munding/Bakeroot teaches all of the limitations of Claim 1,as outlined in the rejection below.
On page 4 of the remarks made in the pre-appeal brief filed on 08/11/2026, with respect to the rejection of claim 21, Applicant argues that the elements 9572 and 9576 are not terminal contacts and element 9574 is not a gate contact as recited by claim 1, but are empty holes. These arguments are fully considered, but are not persuasive. While layers 9572, 9576 and 9574 are shown as empty holed in Fig. 95J, paragraph 0631 of Or-Bach clearly and expressly defines layers 9572, 9574 and 9576 as the source contact, gate contact and drain contact respectively. A person of ordinary skill in the art would have recognized that source and drain contacts are in fact terminal contacts. Therefore, Or-Bach is still relied upon to teach the pertinent limitations of Claim 21.
On page 4 of the remarks made in the pre-appeal brief filed on 08/11/2026, with respect to the rejection of claim 21, Applicant further argues that the contacts 9572 and 9576, 9574 and 9554' do not extend through the layers specified in claim 1 as the layers 9533 and 9534 appear only on the left side of the element 9520 whereas the alleged contacts 9572, 9576, 9574, and 9554' all appear on the right side of the element 9520. These arguments are fully considered, but are not persuasive. Figs. 95C-95J of Or-Bach show manufacturing steps and after each processing step the initial epitaxial layers show in Fig. 95C are renumbered. A person of ordinary skill in the art would have recognized that layers 9533, 9534, 9516 and 9518 of Fig. 95J corresponds to the initial layers 9503’, 9504, 9506 and 9508 of Fig. 95C. As such, the contacts 9572 and 9576 extend through the initials layers 9503’, 9504 of Fig. 95C, which are then renumbered as 9533 and 9534 respectively in Fig. 95J. Similarly, the contacts 9574 and 9544’ together, interpreted as the gate contact, extend through the initials layers 9503’, 9504, 9506 of Fig. 95C, which are then renumbered as 9533, 9534 and 9514 respectively in Fig. 95J. Therefore, Or-Bach is still relied upon to teach the pertinent limitations of Claim 21.
On page 5 of the remarks made in the pre-appeal brief filed on 08/11/2026, with respect to the rejection of claim 18, Applicant argues that the Examiner has not provided a reasoned explanation of why or how a POSITA would use the SiGe etch stop layer from the donor wafer of paragraph [0268] and insert it prior to growing epitaxial layer 9503 on substrate 9500 in the embodiment of Figures 95A-95J and thus, the proposed combination is based on impermissible hindsight. Applicant further argues that citing Chen et al. does not cure this deficiency because Chen is merely cited for "removing" an etch stop layer and thus Chen cannot supply the initial motivation to structurally modify Or-Bach's Figure 95A-95J process to include an etch stop layer between substrate 9500 and layer 9503. These argument are fully considered and are persuasive. The different embodiment of Or-Bach is no longer relied upon to teach the above limitations, and instead Chen et al. is relied upon to teach the above limitations and a proper rationale, as to why or how a POSITA would use an etch stop layer of Chen in the substrate of OR-Bach shown in the embodiment of Figures 95A-95J, is provided in the new rejection of Claim 18 in view of the cited references.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations are limitations not explicitly disclosed in the primary
reference but disclosed in the secondary references.
Claims 1-3, 6, 9, 11-13, 16, 17, 20 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach et al. (US 20110084314 A1), in view of Munding et al. (US 9123735 B2), Lee (US 5376814) and Bakeroot (EP 3627559 A1).
Regarding Claim 1, Or-Bach et al. discloses a semiconductor structure comprising:
a semiconductor layer 9510 (Fig. 95J: 9510, paragraph 0623);
one or more front-side logic devices that are at least partly arranged in a front-side of the semiconductor layer 9510;
at least four epitaxial layers 9518, 9516, 9534, 9533 arranged on a back-side of the semiconductor layer 9510 (Fig. 95J: 9510, 9518, 9516, 9534, 9533, paragraphs 0622, 0623, 0625, 0631),
wherein the four epitaxial layers 9518, 9516, 9534, 9533 comprise a first epitaxial layer 9518 of a first conductivity type (n-type), a second epitaxial layer 9516 of a second conductivity type (p-type) provided on the first epitaxial layer 9518, a third epitaxial layer 9534 of the second conductivity type (p-type) provided on the second epitaxial layer 9516, and a fourth epitaxial layer 9533 of the first conductivity type (n-type) provided on the third epitaxial layer 9534 (Fig. 95J: 9518, 9516, 9534, 9533, paragraphs 0622, 0623, 0625, 0631);
and a plurality of back-side contacts 9562, 9566, 9572, 9576, 9556’, 9554’ that are exposed at a back-side surface of the fourth epitaxial layer 9533 (Fig. 95J: 9562, 9566, 9572, 9576, 9556’, 9554’, paragraph 0631), wherein the plurality of back-side contacts 9562, 9566, 9572, 9576, 9556’, 9554’ comprise:
a set of first terminal contacts 9562, 9566 extending into and electrically contacting the fourth epitaxial layer 9533 (Fig. 95J: 9562, 9566, 9533, paragraph 0631);
a set of second terminal contacts 9572, 9576 electrically contacting the second epitaxial layer 9516 (Fig. 95J: 9572, 9576, 9516, paragraph 0631);
a set of first gate contacts 9556’, 9564 extending into the third epitaxial layer 9534 (Fig. 95J: 9556’, 9534, paragraph 0631);
Note that the contact 9556’, 9564 together are interpreted as a first gate contact.
and a set of second gate contacts 9554’, 9574 extending into the first epitaxial layer 9518 (Fig. 95J: 9554’, 9518, paragraph 0631).
Note that the contact 9554’, 9574 together are interpreted as a second gate contact.
Munding et al. discloses a semiconductor structure comprising the following limitations not disclosed in Or-Bach et al.:
one or more front-side logic devices 6 that are at least partly arranged in a front-side 20 of the semiconductor layer 4 (Fig. 1: 4, 6, 20, column 3, lines 34-40).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Or-Bach et al. and Munding et al. in order to have one or more front-side logic devices that are at least partly arranged in a front-side of the semiconductor layer. Doing so would allow conventional logic functionality on the front-side while leaving the backside available for additional device circuitry, enabling greater integration of devices and reduced routing congestion.
Lee discloses a semiconductor structure comprising the following limitations not disclosed in Or-Bach et al.:
a set of first gate contacts 8, 8a, and a set of second gate contacts 9, 9a (see Fig. 1: 9, 9a, Claim 1).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Or-Bach et al. and Lee in order to have a set of first gate contacts, and a set of second gate contacts. By doing so, the set of gate contacts can provide stronger electrostatic control of the channel, thereby reducing short-channel effects and allow the device to operate effectively with a thinner or more lightly doped channel.
Bakeroot discloses a semiconductor structure comprising the following limitations not disclosed in Or-Bach et al.:
a set of first terminal contacts 26 extending into the fourth epitaxial layer 20 and a set of second terminal contacts 27 extending into the second epitaxial layer 19 (Fig. 2: 27, 26, 19, 20, Fig. 1: 27, 26, 20, paragraph 0026, 0027, 0031).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Or-Bach et al. and Bakeroot in order to have the set of first terminal contacts extending into the fourth epitaxial layer and the set of second terminal contacts extending into the second epitaxial layer. Doing so would ensure the contacts reach the doped regions of the respective epitaxial layers thereby realizing ohmic contact.
Regarding Claim 2, Or-Bach et al. teaches the semiconductor structure according to claim 1, wherein: the set of second terminal contacts 9572, 9576 is electrically isolated from the third epitaxial layer 9534 and the fourth epitaxial layer 9533 (an oxide layer 9550 is used for electrical isolation as shown in Fig. 95J and paragraph 0628); the set of first gate contacts 9556’, 9564 is electrically isolated from the third epitaxial layer 9534 and the fourth epitaxial layer 9533 (an oxide layer 9512 is used for electrical isolation as shown in Fig. 95J and paragraph 0630); and the set of second gate contacts 9554’, 9574 is electrically isolated from the first epitaxial layer 9518, the second epitaxial layer 9516, the third epitaxial layer 9534, and the fourth epitaxial layer 9533 (oxide layers 9511 and 9550 is used for electrical isolation as shown in Fig. 95J and paragraphs 0627, 0630).
Regarding Claim 3, Or-Bach et al. teaches the semiconductor structure according to claim 1, further comprising: a first-conductivity-type (n-type) MOS device formed by a first gate contact 9556’ of the set of first gate contacts 9556’, 9564 configured as a first gate of the first-conductivity-type MOS device and two first terminal contacts 9562, 9566 of the set of first terminal contacts 9562, 9566 configured as a first source and a first drain of the first-conductivity-type MOS device (Fig. 95J, paragraphs 0631, 0633).
Regarding Claim 6, Or-Bach et al. teaches the semiconductor structure according to claim 1, further comprising: a second-conductivity-type (p-type) MOS device formed by a second gate contact 9554’ of the set of second gate contacts 9554’, 9574 configured as a second gate of the second-conductivity type MOS device and two second terminal contacts 9572, 9576 of the set of second terminal contacts 9572, 9576 configured as a second source and a second drain of the second-conductivity-type MOS device (see below annotated Fig. 95J, paragraphs 0631, 0633).
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Annotated Fig. 95J of Or-Bach et al. (US 20110084314 A1).
Regarding Claim 9, Or-Bach et al. teaches the semiconductor structure according to claim 6, wherein the back-side surface of the fourth epitaxial layer 9533 is divided into one or more first-conductivity type areas and one or more second-conductivity-type areas by a plurality of intersecting isolation structures 9520, 9552, wherein each of the one or more first-conductivity type areas comprises one first- conductivity-type (n-type) MOS device and each of the one or more second-conductivity-type areas comprises one second-conductivity-type (p-type) MOS device (see above annotated Fig 95J, paragraph 0631).
Regarding Claim 11, Or-Bach et al. teaches the semiconductor structure according to claim 1, further comprising: one or more isolation structures 9520 extending into the first epitaxial layer 9518 and being either an isolation gates formed by second gate contact of the set of second gate contacts or being a shallow trench isolation (Fig. 95J: 9520, 9518, paragraphs 0625, 0631).
Regarding Claim 12, Or-Bach et al. teaches the semiconductor structure according to claim 11, comprising a first-conductivity-type (n-type) MOS device and a second-conductivity-type (p-type) MOS device that are separated from each other by at least one of the isolation structures 9520 (see above annotated Fig. 95J of Or-Bach et al.: 9520, paragraphs 0631, 0632).
Regarding Claim 13, Or-Bach et al. teaches the semiconductor structure according to claim 1, wherein: the fourth epitaxial layer 9533 has a higher doping concentration (doped N+) of first conductivity type (n-type) dopants than the first epitaxial layer 9518 (doped N-); and/or the second epitaxial layer 9561 has a higher doping concentration (doped P+) of second conductivity type (p-type) dopants than the third epitaxial layer 9534 (doped P-) (Fig. 95J, paragraph 0622).
Regarding Claim 16, Or-Bach et al teaches a device comprising a semiconductor structure according to claim 1 (see rejection of Claim 1 above); and further in a different embodiment, teaches one or more back-side semiconductor devices (3D-DRAM) that are coupled to the plurality of back- side contacts of the semiconductor structure (paragraph 0404).
Therefore, a person of ordinary skill in the art would have modified the teachings of Or-Bach et al. to have one or more back-side semiconductor devices that are coupled to the plurality of back- side contacts of the semiconductor structure. Doing so would enable the integration of both back-side and font-side semiconductor devices into a single electronic die, yielding a compact form factor with reduced manufacturing and assembly costs.
Regarding Claim 17, Or-Bach et al. teaches a method for fabricating a semiconductor structure, the method comprising:
forming a semiconductor layer 9510 (Fig. 95J: 9510, paragraph 0623) and four epitaxial layers 9518, 9516, 9534, 9533 on a back-side of the semiconductor layer (Fig. 95J: 9510, 9518, 9516, 9534, 9533, paragraphs 0622, 0623, 0625, 0631);
forming one or more front-side logic devices that are at least partly arranged in a front- side of the semiconductor layer 9510 ;
wherein the four epitaxial layers 9518, 9516, 9534, 9533 comprise a first epitaxial layer 9518 of a first conductivity type (n-type), a second epitaxial layer 9516 of a second conductivity type (p-type) provided on the first epitaxial layer 9518, a third epitaxial layer 9534 of the second conductivity type (p-type) provided on the second epitaxial layer 9516, and a fourth epitaxial layer 9533 of the first conductivity type (n-type) provided on the third epitaxial layer 9534 (Fig. 95J: 9518, 9516, 9534, 9533, paragraphs 0622, 0623, 0625, 0631);
and forming a plurality of back-side contacts 9562, 9566, 9572, 9576, 9556’, 9554’ that are exposed at a back-side surface of the fourth epitaxial layer 9533 (Fig. 95C-95J: 9562, 9566, 9572, 9576, 9556’, 9554’, paragraph 0631),
the plurality of back-side contacts 9562, 9566, 9572, 9576, 9556’, 9554’ comprise:
a set of first terminal contacts 9562, 9566 extending into and electrically contacting the fourth epitaxial layer 9533 (Fig. 95J: 9562, 9566, 9533, paragraph 0631);
a set of second terminal contacts 9572, 9576 extending into and electrically contacting the second epitaxial layer 9516 (Fig. 95J: 9572, 9576, 9516, paragraph 0631);
a set of first gate contacts 9556’, 9564 extending into the third epitaxial layer 9534 (Fig. 95J: 9556’, 9534, paragraph 0631);
Note that the contact 9556’, 9564 together are interpreted as a first gate contact.
and a set of second gate contacts 9554’, 9574 extending into the first epitaxial layer 9518 (Fig. 95J: 9554’, 9518, paragraph 0631).
Note that the contact 9554’, 9574 together are interpreted as a second gate contact.
Munding et al. discloses a semiconductor structure comprising the following limitations not disclosed in Or-Bach et al.:
forming one or more front-side logic devices 6 that are at least partly arranged in a front-side 20 of the semiconductor layer 4 (Fig. 1: 4, 6, 20, column 3, lines 34-40).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Or-Bach et al. and Munding et al. in order to have one or more front-side logic devices that are at least partly arranged in a front-side of the semiconductor layer. Doing so would allow conventional logic functionality on the front-side while leaving the backside available for additional device circuitry, enabling greater integration of devices and reduced routing congestion.
Lee discloses a semiconductor structure comprising the following limitations not disclosed in Or-Bach et al.:
a set of first gate contacts 8, 8a, and a set of second gate contacts 9, 9a (see Fig. 1: 9, 9a, Claim 1).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Or-Bach et al. and Lee in order to have a set of first gate contacts, and a set of second gate contacts. By doing so, the set of gate contacts can provide stronger electrostatic control of the channel, thereby reducing short-channel effects and allow the device to operate effectively with a thinner or more lightly doped channel.
Bakeroot discloses a semiconductor structure comprising the following limitations not disclosed in Or-Bach et al.:
a set of first terminal contacts 26 extending into the fourth epitaxial layer 20 and a set of second terminal contacts 27 extending into the second epitaxial layer 19 (Fig. 2: 27, 26, 19, 20, Fig. 1: 27, 26, 20, paragraph 0026, 0027, 0031).
Therefore, a person of ordinary skill in the art, would have combined the teachings of Or-Bach et al. and Bakeroot in order to have the set of first terminal contacts extending into the fourth epitaxial layer and the set of second terminal contacts extending into the second epitaxial layer. Doing so would ensure the contacts reach the doped regions of the respective epitaxial layers thereby realizing ohmic contact.
Regarding Claim 20, Or-Bach et al. teaches the method according to claim 17, wherein forming the semiconductor layer 9510 and the four epitaxial layers 9518, 9516, 9534, 9533 on the back-side of the semiconductor layer 9510 comprises:
providing a semiconductor substrate 9500 (Fig. 95A:9500, paragraph 0622);
forming the four epitaxial layers 9503, 9504, 9506, 9508, starting with the fourth epitaxial layer 9503, on the semiconductor substrate 9500 (Fig. 95A:9500, 9503, 9504, 9506, 9508, paragraph 0622);
(Note that the epitaxial layers 9503, 9504, 9506, 9508, are later reindexed as 9533, 9534, 9516, 9508, respectively, in the finished device following processing steps shown in Fig. 95A – 95J.)
forming the semiconductor layer 9510 on the first epitaxial layer 9508 (Fig. 95C: 9510, 9508, paragraph 0625);
and thinning the semiconductor substrate 9500 to the fourth epitaxial layer 9503, which serves as an etch stop layer (paragraph 0623).
Regarding Claim 21, the combination of Or-Bach et al. and Lee teaches the semiconductor structure according to claim 1, wherein: the set of second terminal contacts 9572, 9576 extend through the fourth epitaxial layer 9503’/9533 and through the third epitaxial layer 9504/9534, and the set of second gate contacts 9574, 9554’ extend through the fourth epitaxial layer 9503’/9533, through the third epitaxial layer 9504/9534, and through the second epitaxial layer 9506/9516 (as taught by Or-Bach et al., see Fig. 95J: 9572, 9576, 9574, 9554’, 9533, 9534, 9156, Fig. 95C: 9503’, 9504, 9506).
Note that Fig. 95C shows an initial structure of the epitaxial structure shown in Fig. 95J before processing. The epitaxial layers of the initial structure are reindexed after additional processing steps. A person of ordinary skill in the art would have recognized that layers 9533, 9534, 9516 and 9518 of Fig. 95J corresponds to the initial layers 9503’, 9504, 9506 and 9508 of Fig. 95C.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach et al. (US 20110084314 A1), in view of Munding et al. (US 9123735 B2), Lee (US 5376814) and Bakeroot (EP 3627559 A1), as applied to Claim 3 above, further in view of Williams et al. (US 20080061367 A1).
Regarding Claim 5, Or-Bach et al. teaches the semiconductor structure according to claim 3, wherein: the first-conductivity-type MOS device further comprises a first bulk contact formed by a second terminal contact of the set of second terminal contacts (Last line of paragraph 0631 mentions that a plurality of contacts are formed in the second epitaxial layer 9516 which are not shown in Fig. 95J).
Or-Bach et al. fails to teach a first top contact formed by a first terminal contact of the set of first terminal contacts.
However, Williams et al. teaches a semiconductor structure having a MOS device including a first top contact 291C formed by a first terminal contact of the set of first terminal contacts 291A, 291B, 291C (Fig. 9: 291A, 291B, 291C).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention would have combined the teachings of Or-Back et al. with the teachings of Williams et al. in order to come up with the claimed invention. Doing so would increase the breakdown voltage of the MOS device, as recognized by Williams et al. (paragraph 0145).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach et al. (US 20110084314 A1), in view of Munding et al. (US 9123735 B2), Lee (US 5376814) and Bakeroot (EP 3627559 A1), as applied to Claim 6 above, further in view of Williams et al. (US 20080061367 A1).
Regarding Claim 8, Or-Bach et al. teaches the semiconductor structure according to claim 6, wherein: the second-conductivity-type MOS device further comprises a second bulk contact formed by a second terminal contact of the set of second terminal contacts (Last line of paragraph 0631 mentions that a plurality of contacts are formed in the third epitaxial layer 9516 which are not shown in Fig. 95J).
Or-Bach et al. fails to teach a second top contact formed by a first terminal contact of the set of first terminal contacts.
However, Williams et al. teaches a semiconductor structure having a MOS device including a first top contact 291C formed by a second terminal contact of the set of second terminal contacts 291A, 291B, 291C (Fig. 9: 291A, 291B, 291C).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention would have combined the teachings of Or-Back et al. with the teachings of Williams et al. in order to come up with the claimed invention. Doing so would increase the breakdown voltage of the MOS device, as recognized by Williams et al. (paragraph 0145).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach et al. (US 20110084314 A1), in view of Munding et al. (US 9123735 B2), Lee (US 5376814) and Bakeroot (EP 3627559 A1), as applied to Claim 6 above, further in view of Yang et al. (US 20070020858 A1).
Regarding Claim 10, Or-Bach et al. fails to teach the semiconductor structure according to claim 6, further comprising: two shallow trench isolations (STIs) extending in parallel along a first direction; two isolation gates extending in parallel along a second direction, which is perpendicular to the first direction, and intersecting with the two STIs; and a first-conductivity-type area or a second-conductivity-type area formed within the two STIs and two isolation gates.
However, Yang et al. teaches a semiconductor structure comprising two shallow trench isolations (STIs) ST1, ST2 extending in parallel along a first direction; two isolation gates 30, 31 extending in parallel along a second direction, which is perpendicular to the first direction, and intersecting with the two STIs ST1, ST2; and a first-conductivity-type area or a second-conductivity-type area 1, 3, 5 formed within the two STIs ST1, ST2 and two isolation gates 30, 31 (Fig. 10: 30, 31, 32, 33, ST1, ST2, 1, 3, 5, paragraphs 0047 and 0048).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention would have combined the teachings of Or-Back et al. with the teachings of Yang et al. in order to come up with the claimed invention. Doing so would electrically isolate the MOS devices from all sides and provide insulation between transistors, as recognized by Yang et al. (paragraphs 0047, 0051).
Claims 15 is rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach et al. (US 20110084314 A1), in view of Munding et al. (US 9123735 B2), Lee (US 5376814) and Bakeroot (EP 3627559 A1), as applied to Claim 1 above, further in view of Suh (US 20060138477 A1).
Regarding Claim 15, while Or-Bach et al teaches the semiconductor structure according to claim 1, wherein a first gate contact 9556’ of the set of first gate contacts and/or a second gate contact 9554’ of the set of second gate contacts are formed, respectively, within the third epitaxial layer 9534 and/or the first epitaxial layer 9518, it fails to explicitly teach that these gate contacts have a flat tip formed.
However, Suh teaches a MOSFET structure comprising a plurality of first gate contacts 112, 114 having a flat tip formed (Fig. 2: 112, 114, paragraph 0028).
Therefore, a person of ordinary skill in the art would have modified the teachings of Or-Bach et al. with the teachings of Suh to have a first gate contact of the set of first gate contacts and/or a second gate contact of the set of second gate contacts of Or-Bach et al. have a flat tip formed. Doing so would simplify the fabrication process without the need for additional etching steps to fabricate non-flat tips such as rounded or triangular tips.
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Or-Bach et al. (US 20110084314 A1), in view of Munding et al. (US 9123735 B2), Lee (US 5376814) and Bakeroot (EP 3627559 A1), as applied to Claim 17 above, further in view of Chen et al. (US 20220028994 A1).
Regarding Claim 18, Or-Bach et al. teaches the method according to claim 17, wherein forming the semiconductor layer 9510 and the four epitaxial layers 9518, 9516, 9534, 9533 on the back-side of the semiconductor layer 9510 comprises (Fig. 95J:
providing a semiconductor substrate 9500;
forming an etch stop layer on the semiconductor substrate 9500;
forming the four epitaxial layers 9508, 9506, 9504, 9503, starting with the fourth epitaxial layer 9503, on the etch stop layer (Fig. 95A: 9503, 9504, 9506, 9508, paragraphs 0622, 0268);
(Note that the epitaxial layers 9503, 9504, 9506, 9508, are later reindexed as 9533, 9534, 9516, 9508, respectively, in the finished device following processing steps shown in Fig. 95A – 95J.)
forming the semiconductor layer 9510 on the first epitaxial layer 9518 (Fig. 95C: 9510, 9508, paragraph 0625);
thinning the semiconductor substrate 9500 to the etch stop layer;
and removing the etch stop layer.
Chen et al. teaches a method of forming a semiconductor structure, comprising the following limitations not disclosed in Or-Bach et al.:
forming an etch stop layer 17 on the semiconductor substrate 11 (Fig. 2A: 11, 17, paragraphs 0022, 0024);
thinning the semiconductor substrate 11 to the etch stop layer 17 (paragraph 0024);
and removing the etch stop layer 17 (paragraph 0025).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to have combined the teachings of Or-Bach et al. with the teachings of Chen et al. in order to form an etch stop layer on the semiconductor substrate, thinning the semiconductor substrate to the etch stop layer, and remove the etch stop layer. Doing so would provide a high etch selectivity between the substrate and the etch stop layer during the thinning of substrate, as recognized by Chen et al. (paragraph 0025), consequently exposing the backside of the semiconductor layers for back-end processing.
Further, a person of ordinary skill in the art would have recognized that when the etch stop layer of Chen et al. is disposed in the epitaxial structure of Or-Bach et al., the four epitaxial layers 9508, 9506, 9504, 9503, starting with the fourth epitaxial layer 9503, can be formed on the etch stop layer.
Regarding Claim 19, Or-Bach et al. teaches the method according to claim 18, wherein: each of the four epitaxial layers 9518, 9516, 9534, 9533 comprises silicon; and/or the etch stop layer is formed on the semiconductor substrate 9500 and comprises silicon germanium (paragraph 0268, 0622).
Conclusion
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/HAMNA FATHIMA IQBAL/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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