DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed July 21st, 2022. Claims 1-20 are pending, of which claims 1-12, 14, 16, 18-20 are currently rejected. Claims 13, 15, and 17 are objected to.
Drawings
The drawings are objected to because Fig. 12 “Output Buffer 1202” should be “Weight Buffer 1202” as would be consistent with the description in instant specification ¶ 0056. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
In addition to Replacement Sheets containing the corrected drawing figure(s), applicant is required to submit a marked-up copy of each Replacement Sheet including annotations indicating the changes made to the previous version. The marked-up copy must be clearly labeled as “Annotated Sheets” and must be presented in the amendment or remarks section that explains the change(s) to the drawings. See 37 CFR 1.121(d)(1). Failure to timely submit the proposed drawing and marked-up copy will result in the abandonment of the application.
Claim Objections
Claims 19-20 are objected to because of the following informalities:
Line 7 “wherein first mux” should be “wherein a first mux”.
Claim 20 is objected to based on its dependence upon claim 19.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation “a first selector” on line 7. It is unclear if this mention of “a first selector” is the same as the mention of “a first selector” of claim 1 line 7. For examination purposes, the “first selector” of claim 2 will be construed to be the “first selector” of claim 2. Appropriate correction is required.
Because claims 3-9 depend upon claim 2, claims 3-9 are also rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6, 8, 10-14, 16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over A. Samajdar et al. ("SCALE-Sim: Systolic CNN Accelerator Simulator", 2019) (hereinafter “Samajdar”), in view of G. Causapruno et al. ("Reconfigurable Systolic Array: From Architecture to Physical Design", 2016) (hereinafter “Causapruno”), in view of Gu et al. (US 2023/0205729 A1) (hereinafter “Gu”).
As to treatment of claims, apparatus claims 18-19 will be addressed first followed by apparatus claims 1-3, 6, 8, 10, and method claims 12-14, and 16.
Regarding claim 18, Samajdar teaches:
an input buffer configured to store a plurality of input activation states (Samajdar: Pg. 1 Fig. 1 IFMAP SRAM double buffered as input buffer);
a weight buffer configured to store a plurality of weights (Samajdar: Pg. 1 Fig. 1 Filter SRAM double buffered as weight buffer);
a matrix array of processing elements arranged in a plurality of rows and a plurality of columns (Samajdar: Pg. 1 Fig. 1 plurality of processing elements configured in rows and columns),
an output buffer configured to receive outputs (Samajdar: Pg. 1 Fig. 1 OFMAP SRAM double buffered as output buffer).
Samajdar does not explicitly teach the internal structure of the PE’s with the multiplexers and memories or the accumulators after the last row of processing elements.
However, Causapruno teaches:
wherein each processing element of the matrix array of processing elements include:
a first memory configured to store an input activation state from the input buffer (Causapruno: Pg. 5 Fig. 3 Reg taking as input left_in_chain i.e., input activation, also supplied to MUX);
a second memory configured to store a weight from the weight buffer (Causapruno: Pg. 5 Fig. 3 Reg taking as input top_in_chain i.e., weight, also supplied to MUX);
a multiplier configured to multiply the weight and the input activation state and output a product (Causapruno: Fig. 3 Reconfigurable ALU taking op1 and op2 for MAC operation, further discussed in Pg. 5 Col. 2 Section A to take op1 and op2 for multiplier and providing product to adder as one input and fb signal as second input to adder);
a third memory configured to store a first sum and output the first sum to a processing element of a next row or a next column (Causapruno Pg. 5 Fig. 3 REG taking input from reconfigurable ALU i.e., first sum and outputting result to right_out_PE (next PE in row), as well as down_out_pe (next PE in column);
an adder configured to add the product and the previous sum or the first sum to output a second sum (Causapruno: Fig. 3 reconfigurable ALU and as discussed in Pg. 5 Col. 2 Section A to take op1 and op2, as well as fb to do addition operation and sum either previous or first sum to second sum).
It would be obvious before the effective filing date of the claimed invention to combine the internal structure of the processing elements as taught by Causapruno with the overall processing circuit as taught by Samajdar because both teachings are directed towards systolic architectures involving MAC operations. It is obvious to use a known technique to improve similar devices in the same way. See MPEP 2141(III)(c).
While Causapruno does not explicitly teach the first mux to output a previous sum from a processing element of a previous row or a previous column, Causapruno does each two muxes on Pg. 5 Fig. 3, the first taking as input an input activation and a previous sum from a previous column and the second taking as input a weight and a previous sum from a previous row. The two muxes are indicated below:
PNG
media_image1.png
381
447
media_image1.png
Greyscale
These two muxes however can be implemented in a dual mux form, having a 4:2 configuration. In this way the one 4:2 mux would be able to select a previous sum from a previous row or column.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to combine the two muxes to be implemented into one mux to form the first mux as claimed, since it has been held that forming in one piece an article, which has formerly been formed in two pieces and put together, involves only routine skill in the art. Howard v. Detroit Stove Works, 150 U.S. 164 (1893). The term “integral” is sufficiently broad to embrace constructions united by such means as fastening and welding. In re Hotte, 177 USPQ 326, 328 (CCPA 1973).
Samajdar in view of Causapruno does not explicitly teach a plurality of accumulators or second mux to select between a previous sum or a first sum or a third mux to select between a second sum or previous sum.
However, Gu teaches in Fig. 4C a second mux taking as input the output of MAC operation (mux taking input from register after multiplier and adder i.e., first sum as well as ACC_in i.e., previous sum) and a third mux taking as input the output of MAC operation (mux taking input from register after multiplier and adder i.e., second sum as well as Branch i.e., previous sum), as well as accumulators after a last row of PE’s to accumulate results of the PE’s (Gu: ¶ 0011; Fig. 3A memory access after Row 9 of PE’s specifically AOMEM).
It would be obvious before the effective filing date of the claimed invention to combine the processing circuit as taught by Samajdar in view of Causapruno because all teachings are directed towards systolic architectures involving MAC operations. One with ordinary skill in the art would be motivated to combine the teachings because doing so would increase the flexibility of the reconfigurability of the device as a whole (Gu: ¶ 0056).
Therefore, Samajdar in view of Causapruno in view of Gu teaches:
A processing core of an artificial intelligence (AI) accelerator, the processing core comprising:
an input buffer configured to store a plurality of input activation states;
a weight buffer configured to store a plurality of weights;
a matrix array of processing elements arranged in a plurality of rows and a plurality of columns, wherein each processing element of the matrix array of processing elements include:
a first memory configured to store an input activation state from the input buffer;
a second memory configured to store a weight from the weight buffer;
a multiplier configured to multiply the weight and the input activation state and output a product;
a first multiplexer (mux) configured to, based on a first selector, output a previous sum from a processing element of a previous row or a previous column;
a third memory configured to store a first sum and output the first sum to a processing element of a next row or a next column;
a second mux configured to, based on a second selector, output the previous sum or the first sum;
an adder configured to add the product and the previous sum or the first sum to output a second sum; and
a third mux configured to, based on a third selector, output the second sum or the prev10us sum;
a plurality of accumulators configured to receive outputs from a last row of the plurality of rows and sum one or more of the received outputs from the last row; and
an output buffer configured to receive outputs from the plurality of accumulators.
Regarding claim 19, Samajdar teaches a matrix array having a first, second, third, and fourth processing element being contained in the corresponding rows as claimed in claim 19 (Samajdar: Pg. 1 Fig. 1):
PNG
media_image2.png
292
497
media_image2.png
Greyscale
Samajdar does not explicitly teach outputting a first sun of a processing element to adjacent processing elements or a first multiplexer configured to receive a first sum from preceding processing elements.
However, Causapruno teaches a first sum being output to adjacent PE’s as inputs to the adjacent PE’s, as well as a first mux for receiving the output from preceding PE’s (Causapruno: Fig. 3 right_out_pe and down_out_pe sends result to adjacent PE’s and multiplexer as discussed with respect to claim 18 takes result from preceding processing elements signals result_left_pe and result_top_pe).
The motivation to combine with respect to claim 18 applies equally to claim 19.
Regarding claim 20, Samajdar in view of Causapruno in view of Gu teaches the processing elements of the matrix array being configured to operate in three different modes output stationary (Samajdar: Pg. 3 Col. 2 Section A paragraphs 3-5), input stationary (Samajdar: Pg. 4 Col. 2 last two paragraphs), and weight stationary mode (Samajdar: Pg. 3 Col. 2 last paragraph ad Pg. 4 Col. 1 first two paragraphs).
Regarding claim 1, Samajdar teaches a reconfigurable systolic array structure having an input buffer and a weight buffer for inputting to the rows and columns of processing elements of the reconfigurable systolic array based on different modes of operation (Pg. 1 Fig. 1 IFMAP SRAM double buffered as input activation buffer, Filter SRAM double buffered as weight buffer, both buffers being provided as inputs to the array of processing elements; Pg. 3 Section B and Pg. 4 discusses the three modes of operation of the systolic array).
Samajdar does not explicitly teach the internal structure of the various processing elements.
However Causapruno teaches:
A reconfigurable processing circuit of an artificial intelligence (AI) accelerator, the reconfigurable processing circuit comprising:
a first memory configured to store an input activation state (Causapruno: Pg. 5 Fig. 3 Reg taking as input left_in_chain i.e., input activation, also supplied to MUX);
a second memory configured to store a weight (Causapruno: Pg. 5 Fig. 3 Reg taking as input top_in_chain i.e., weight, also supplied to MUX);
a multiplier configured to multiply the weight and the input activation state and output a product (Causapruno: Fig. 3 Reconfigurable ALU taking op1 and op2 for MAC operation, further discussed in Pg. 5 Col. 2 Section A to take op1 and op2 for multiplier and providing product to adder as one input and fb signal as second input to adder);
a third memory configured to store a first sum (Causapruno Pg. 5 Fig. 3 REG taking input from reconfigurable ALU i.e., first sum and outputting result to right_out_PE (next PE in row), as well as down_out_pe (next PE in column));
an adder configured to add the product and the previous sum or the first sum to output a second sum (Causapruno: Fig. 3 reconfigurable ALU and as discussed in Pg. 5 Col. 2 Section A to take op1 and op2, as well as fb to do addition operation and sum either previous or first sum to second sum).
It would be obvious before the effective filing date of the claimed invention to combine the internal structure of the processing elements as taught by Causapruno with the overall processing circuit as taught by Samajdar because both teachings are directed towards systolic architectures involving MAC operations. It is obvious to use a known technique to improve similar devices in the same way. See MPEP 2141(III)(c).
While Causapruno does not explicitly teach the first mux to output a previous sum from a processing element of a previous row or a previous column, Causapruno does each two muxes on Pg. 5 Fig. 3, the first taking as input an input activation and a previous sum from a previous column and the second taking as input a weight and a previous sum from a previous row. The two muxes are indicated below:
These two muxes however can be implemented in a dual mux form, having a 4:2 configuration. In this way the one 4:2 mux would be able to select a previous sum from a previous row or column.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to combine the two muxes to be implemented into one mux to form the first mux as claimed, since it has been held that forming in one piece an article, which has formerly been formed in two pieces and put together, involves only routine skill in the art. Howard v. Detroit Stove Works, 150 U.S. 164 (1893). The term “integral” is sufficiently broad to embrace constructions united by such means as fastening and welding. In re Hotte, 177 USPQ 326, 328 (CCPA 1973).
Samajdar in view of Causapruno does not explicitly teach a second mux to select between a previous sum or a first sum or a third mux to select between a second sum or previous sum.
However, Gu teaches in Fig. 4C a second mux taking as input the output of MAC operation (mux taking input from register after multiplier and adder i.e., first sum as well as ACC_in i.e., previous sum) and a third mux taking as input the output of MAC operation (mux taking input from register after multiplier and adder i.e., second sum as well as Branch i.e., previous sum).
It would be obvious before the effective filing date of the claimed invention to combine the second and third mux as taught by Gu with the processing circuit as taught by Samajdar in view of Causapruno because all teachings are directed towards systolic architectures involving MAC operations. One with ordinary skill in the art would be motivated to combine the teachings because doing so would increase the flexibility of the reconfigurability of the device as a whole (Gu: ¶ 0056).
Therefore, Samajdar in view of Causapruno in view of Gu teaches:
A reconfigurable processing circuit of an artificial intelligence (AI) accelerator, the reconfigurable processing circuit comprising:
a first memory configured to store an input activation state;
a second memory configured to store a weight;
a multiplier configured to multiply the weight and the input activation state and output a product;
a first multiplexer (mux) configured to, based on a first selector, output a previous sum from a previous reconfigurable processing element;
a third memory configured to store a first sum;
a second mux configured to, based on a second selector, output the previous sum or the first sum;
an adder configured to add the product and the previous sum or the first sum to output a second sum; and
a third mux configured to, based on a third selector, output the second sum or the previous sum.
Regarding claim 2, Samajdar in view of Causapruno in view of Gu teaches a first mux configured to receive a first and second previous sum from a first and second reconfigurable processing circuit respectively and chooses between the two previous sums to be output as a previous sum, as has been discussed with respect to claim 1 with the two muxes of Causapruno (Fig. 3) that can modified to be implemented as one MUX and therefore choose between the previous sums from the different reconfigurable circuits.
The motivation to modify with respect to claim 1 also applies to claim 2.
Regarding claim 3, Samajdar in view of Causapruno in view of Gu teaches during a first mode having weights and input activations updated in every cycle (Samajdar: Pg. 3 first mode i.e., output stationary mode Col. 2 Output stationary section under Section B required operands are streamed and therefore stored in the PE (first and second memories respectively of each PE) in every cycle).
Regarding claim 6, Samajdar in view of Causapruno in view of Gu teaches in a second mode having only weights stored in each of the PE’s updated every cycle (Samajdar: second mode i.e., input stationary mode Pg. 4 Col. 1 last two paragraphs and Col. 2 first two paragraphs, inputs are pinned but weights are streamed and stored every cycle).
Regarding claim 8, Samajdar in view of Causapruno in view of Gu teaches in a third mode having only input activations stored in each of the PE’s and updated every cycle (Samajdar: third mode i.e., weight stationary mode Pg. 4 Col. 1 first two paragraphs weight stationary mode i.e., third mode).
Claim 10 recites the method practiced by the apparatus of claim 1 and is therefore rejected for the same reasons therein.
Regarding claim 11, the combination as described with respect to claim 1 teaches the systolic architecture functioning with respect to one of three operating modes, output stationary, weight stationary, and input stationary (Samajdar: Pgs. 3-4 discussion of the operation modes), the three different modes determining what inputs to the systolic array are updated within the PE’s, which therefore determines the operation of the muxes and registers (Causapruno: Fig. 3).
The motivation to combine with respect to claim 1 applies equally to claim 11.
Regarding claim 12, Samajdar teaches:
receiving, from an input buffer, an input activation state (Causapruno: Pg. 1 Fig. 1 IFMAP SRAM double buffered as input buffer, provides inputs to PE’s in array);
receiving, from a weight buffer, a weight (Causapruno: Pg. 1 Fig. 1 SRAM double buffered as weight buffer, provides weights to PE’s in array)
performing the multiplying and the adding (Causapruno: Pg. 3 Col. 1 Section A second paragraph processing elements are multiply-accumulate units taking in input activations and weights to carry out multiplying and adding).
Samajdar does not explicitly teach
storing, in a first memory, the input activation state;
storing, in a second memory, the weight.
However, Causapruno teaches:
storing, in a first memory, the input activation state (Causapruno: Fig. 3 receiving left_in_chain input activation at REG);
storing, in a second memory, the weight (Causapruno: Fig. 3 receiving top_in_chain weight at REG).
The motivation to combine with respect to claim 1 applies equally to claim 12.
Regarding claim 14, Samajdar in view of Causapruno in view of Gu teaches during a second mode (i.e., input stationary), inputs are pre-loaded (Samajdar: Pg. 4 Fig. 2 (c)), which would be saved in a first memory of each of the PE’s for MAC operations.
Regarding claim 16, Samajdar in view of Causapruno in view of Gu teaches during a third mode (i.e., weight stationary), weights are pre-loaded (Samajdar: Pg. 4 Fig. 2(b)), which would be saved in a second memory of each of the PE’s for MAC operations.
Allowable Subject Matter
Claims 4-5, 7, 9, 13, 15, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Applicant claims a reconfigurable processing circuit of an artificial intelligence (AI) accelerator as in claim 1 comprising:
a first memory configured to store an input activation state;
a second memory configured to store a weight;
a multiplier configured to multiply the weight and the input activation state and output a product;
a first multiplexer (mux) configured to, based on a first selector, output a previous sum from a previous reconfigurable processing element;
a third memory configured to store a first sum;
a second mux configured to, based on a second selector, output the previous sum or the first sum;
an adder configured to add the product and the previous sum or the first sum to output a second sum; and
a third mux configured to, based on a third selector, output the second sum or the previous sum.
Wherein claim 2 is dependent on claim 1 further comprising:
Wherein the first mux is further configured to:
receive a first previous sum from a first reconfigurable processing circuit of a first column as a first input;
receive a second previous sum from a second reconfigurable processing circuit of a different row as a second input; and
based on a first selector, output the first previous sum or the second previous sum as the previous sum.
Wherein claim 3 is dependent on claim 2 further comprising:
wherein, in a first mode, the first and second memories are further configured to respectively update the stored input activation state and the stored weight each cycle.
Wherein claim 4 is dependent on claim 3 further comprising:
Wherein in the first mode, during an accumulate operation, the second mux is further configured to output the first sum, and the third mux is further configured to output the second sum during an accumulate operation.
The specific reason for indication of allowable subject matter is the specific functionality and outputs of the second and third muxes as driven by the reconfigurable mode of the processing circuit. Samjadar in view of Causapruno in view of Gu discloses the claimed invention according to the claim mappings above. Samjadar in view of Causapruno in view of Gu does not explicitly disclose the outputs of the second and third muxes as claimed in claim 4.
Claim 5 dependent on claim 4 is therefore also allowable.
Wherein claim 6 is dependent on claim 2 further comprising:
wherein, in a second mode, only the second memory of the first and second memories is configured to update the stored weight each cycle.
Wherein claim 7 is dependent on claim 6 further comprising:
wherein, in the second mode:
the first mux is further configured to output the first previous sum as the previous sum;
the second mux is further configured to output the previous sum; and
the third mux is further configured to output the second sum.
The specific reason for indication of allowable subject matter is the specific outputs of the respective muxes as driven by the reconfigurable mode of the processing circuit. Samjadar in view of Causapruno in view of Gu discloses the claimed invention according to the claim mappings above. Samjadar in view of Causapruno in view of Gu does not explicitly disclose the outputs of the muxes with respect to the reconfigurable mode as claimed in claim 7.
Wherein claim 8 is dependent on claim 2, further comprising:
wherein, in a third mode, only the first memory of the first and second memories is configured to update the stored input activation state each cycle.
Wherein claim 9 is dependent on claim 8, further comprising:
Wherein, in the third mode:
the first mux is further configured to output the second previous sum as the previous sum;
the second mux is further configured to output the previous sum to the adder; and
the third mux is further configured to output the second sum.
The specific reason for indication of allowable subject matter is the specific outputs of the respective muxes as driven by the reconfigurable mode of the processing circuit. Samjadar in view of Causapruno in view of Gu discloses the claimed invention according to the claim mappings above. Samjadar in view of Causapruno in view of Gu does not explicitly disclose the outputs of the muxes with respect to the reconfigurable mode as claimed in claim 9.
Applicant claims a method of operating a reconfigurable processing circuit for an artificial intelligence accelerator as in claim 10 comprising:
selecting, by a first multiplexer (mux) based on a first selector, a previous sum from a previous column or a previous row of a matrix of reconfigurable processing elements of the artificial intelligence accelerator;
multiplying an input activation state and a weight to output a product;
selecting, by a second mux based on a second selector, the previous sum or a current sum;
adding the product and the selected previous sum or the selected current sum to output an updated sum;
selecting, by a third mux based on a third selector, the updated sum or the previous sum; and
outputting the selected updated sum or the selected previous sum.
Wherein claim 11 is dependent on claim 10, further comprising:
further comprising determining the first selector, the second selector, and the third selector based on one of three operating modes of the reconfigurable processing element.
Wherein claim 12 is dependent on claim 11, further comprising:
during a first mode of the three operating modes in every processing cycle:
receiving, from an input buffer, an input activation state;
storing, in a first memory the input activation state;
receiving, from a weight buffer, a weight;
storing, in a second memory, the weight; and
performing the multiplying and the adding.
Wherein claim is dependent on claim 12, further comprising:
wherein, during the first mode in every processing cycle:
selecting by the first mux includes selecting the previous sum from the previous row;
selecting by the second mux includes selecting the current sum; and
selecting by the third mux includes selecting the updated sum during an accumulate operation or selecting the previous sum during a transfer-out operation after the accumulate operation.
The specific reason for indication of allowable subject matter is the specific outputs of the respective muxes as driven by the reconfigurable mode of the processing circuit. Samjadar in view of Causapruno in view of Gu discloses the claimed invention according to the claim mappings above. Samjadar in view of Causapruno in view of Gu does not explicitly disclose the outputs of the muxes with respect to the reconfigurable mode as claimed in claim 13.
Wherein claim 14 is dependent on claim 11, further comprising:
further comprising, during a second mode of the three operating modes preloading, in a first memory, the input activation state.
Wherein claim 15 is dependent on claim 14, further comprising:
wherein, during the second mode, in every processing cycle:
selecting by the first mux includes selecting the previous sum from the previous column;
selecting by the second mux includes selecting the previous sum; and
selecting by the third mux includes selecting the updated sum.
The specific reason for indication of allowable subject matter is the specific outputs of the respective muxes as driven by the reconfigurable mode of the processing circuit. Samjadar in view of Causapruno in view of Gu discloses the claimed invention according to the claim mappings above. Samjadar in view of Causapruno in view of Gu does not explicitly disclose the outputs of the muxes with respect to the reconfigurable mode as claimed in claim 15.
Wherein claim 16 is dependent on claim 11, further comprising:
During a third mode of the three operating modes preloading, in a second memory, the weight.
Wherein claim 17 is dependent on claim 16, further comprising:
during the third mode, in every processing cycle:
selecting by the first mux includes selecting the previous sum from the previous row;
selecting by the second mux includes selecting the previous sum; and
selecting by the third mux includes selecting the updated sum.
The specific reason for indication of allowable subject matter is the specific outputs of the respective muxes as driven by the reconfigurable mode of the processing circuit. Samjadar in view of Causapruno in view of Gu discloses the claimed invention according to the claim mappings above. Samjadar in view of Causapruno in view of Gu does not explicitly disclose the outputs of the muxes with respect to the reconfigurable mode as claimed in claim 17.
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Langhammer (9207908) teaches specialized processing blocks with reconfigurable interconnections for implementing vector or dot products, FIR filters, or sum-of-products operations.
Wang (US 2021/0081211 A1) teaches an integrated circuit including configurable multiplier-accumulator circuitry with first and second memories configured as either dedicated read or write memory.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARIA DE JESUS RIVERA whose telephone number is (571)272-2793. The examiner can normally be reached Monday-Friday 7:30AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/M.D.R./Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
Prosecution Insights