DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Status of Claims
Applicant's response of 01/09/2026 has been acknowledged. Claims 1, 10 and 15 have been amended. No new matter has been added.
This office action considers claims 1-20 pending for prosecution and are examined on their merits.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been fully considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all
obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1, 2, 3, and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 20210043747 A1 – hereinafter Cheng) in view of Basker et al. (US 20170352744 A1 – hereinafter Basker), and Frougier et al. – (US 20200357911 A1 – hereinafter Frougier).
Regarding independent claim 1, Cheng teaches
(Currently Amended) A semiconductor structure ([0015] – “semiconductor
structure”), comprising:
a gate structure (Fig. 4 – [0036] – “gate electrode layer 120b combined with its corresponding gate dielectric layer 120a may be referred to as a gate stack 120 or a metal gate stack 120” – hereinafter ‘GS’) formed over a substrate (100 – Fig. 4 – [0015] – “substrate 100”);
a source/drain (S/D) structure (116 – Fig. 4 – [0030] – “source/drain (S/D) structures 116”) formed adjacent to the gate structure (120b – Fig. 4 show this);
an isolation layer below the S/D structure, wherein the isolation layer is between the substrate and the S/D structure;
a gate spacer (114 – Fig. 4 – [0029] – “sidewall spacers 114 are formed on sidewalls of the dummy gate stacks 108”) formed adjacent to the gate structure (120b – Fig. 4 show this);
an etching stop layer adjacent to the gate spacer;
a conductive cap layer (202 – Fig. 4 – [0050] – “metal cap layers 202”) formed over the gate structure (GS), and
a gate mask layer (204 – Fig. 4 – [0062] – “mask layers 204”) formed over the gate structure (GS) and the conductive cap layer (202), wherein a topmost surface of the gate mask layer is higher than a topmost surface of the etching stop layer and an entirety of the gate mask layer is higher than a top surface of the conductive (202) cap layer.
Cheng does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Basker teaches
an etching stop layer (160 – Fig. 37 – [0094] – “gate spacer layer 160 may also act as an etch stop”) adjacent to the gate spacer (160 – Fig. 37 – [0094] – “gate spacer layer 160 may also act as an etch stop” – Fig. 37 shows this),
wherein a topmost surface of the gate mask layer (230 – Fig. 37 – [0145] – “cap 230”) is higher than a topmost [[top]] surface of the etching stop layer (160) and an entirety of the gate mask layer (230) is higher than a top surface of the conductive cap layer (230 – Fig. 37 – [0145] – “protective cap 230”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the etch stop layer positioning structure as taught by Basker into Cheng.
An ordinary artisan would have been motivated to use the known technique of Basker in the manner set forth above to produce the predictable result [0094] – “to prevent or limit the lateral etching of the sacrificial gate layer 145 towards the dummy gate layer 150.”
Basker does not teach that the cap is conductive however for the cap to function the same way, the via would have to penetrate it to reach gate metal fill 220.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Cheng and Basker do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Frougier teaches
an isolation layer (105 – Fig. 1A – [0030] – “isolation layer 105”) below the S/D structure (115 – Fig. 1A – [0028] – “source/drain region 115”), wherein the isolation layer (105) is between the substrate (101 – Fig. 1A – [0029] – “substrate 101”) and the S/D structure (115 – Fig. 1A shows this);
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the isolation layer positioning structure as taught by Frougier into Cheng and Basker.
An ordinary artisan would have been motivated to use the known technique of Frougier in the manner set forth above to produce the predictable result to prevent [0026] – “with device size scaling and, particularly, as gate pitch decreases with each new technology node, the dielectric spacer material can pinch-off in the open space between adjacent gates (given the gate sidewall spacer, etc. thereon) during deposition” and provide better isolation between the adjacent gates.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 2, Cheng as modified by Basker, and Frougier, teaches claim 1 from which claim 2 depends. Cheng further teaches
(Original) The semiconductor structure as claimed in claim 1, further
comprising:
a conductive cap layer (202) formed over the gate structure (GS), wherein the conductive cap layer (202) is below the gate mask layer (204 – Fig. 4 shows this).
Regarding claim 3, Cheng as modified by Basker, and Frougier, teaches claim 2 from which claim 3 depends. Cheng further teaches
(Original) The semiconductor structure as claimed in claim 2, further
comprising:
a gate conductive via (216 – Fig. 4 – [0104] – “a conductive structure (e.g., a conductive via) 216”) formed over the conductive cap layer (202), wherein the gate
conductive via (216) passes through the gate mask layer (204 – Fig. 4 shows this) and is in direct contact with the conductive cap layer (202).
Regarding claim 4, Cheng as modified by Basker, and Frougier, teaches claim 2 from which claim 4 depends. Cheng and Frougier do not expressly disclose the limitations of claim 4.
However, in an analogous art, Basker teaches
(Original) The semiconductor structure as claimed in claim 1, wherein the
gate mask layer (230) covers a portion of the etching stop layer (160).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the gate mask and etch stop structure as taught by Basker into Cheng and Frougier.
An ordinary artisan would have been motivated to use the known technique of Basker in the manner set forth above to produce the predictable result as stated in claim 1.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Basker, Frougier, and Choi et al. (US 20230053379 A1 – hereinafter Choi).
Regarding claim 5, Cheng as modified by Basker, and Frougier, teaches claim 2 from which claim 5 depends. Cheng, Basker, and Frougier do not expressly disclose the limitations of claim 4.
However, in an analogous art, Choi teaches
(Original) The semiconductor structure as claimed in claim 1, further comprising:
a plurality of nanostructures (NS1 – Fig. 7 – {[0042] – “plurality of first sheet patterns NS1”}, {[0032] – “a nano sheet”}) formed below the gate structure (GS).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the nanostructure as taught by Choi into Cheng, Basker, and Frougier.
An ordinary artisan would have been motivated to use the known technique of Choi in the manner set forth above to produce the predictable result [0003] – “for increasing the density of a semiconductor device, a multi-gate transistor for forming a multi-channel active pattern (and/or silicon body) of a fin and/or nanowire shape on a substrate and forming a gate on a surface of the multi-channel active pattern.”
Claims 6, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Basker, Frougier, Choi, and Hsu et al. (US 20210202512 A1 – hereinafter Hsu).
Regarding claim 6, Cheng as modified by Basker, and Frougier, teaches claim 2 from which claim 6 depends. Cheng, Basker, and Frougier do not expressly disclose the limitations of claim 6.
However, in an analogous art, Choi teaches
(Original) The semiconductor structure as claimed in claim 1, further comprising:
a dielectric layer formed over the gate structure;
an S/D contact structure (170, 180 – Fig. 4 – {[0037] – “a source/drain contact 170”}, {[0134] – “The source/drain via plug 180 may directly be connected with the source/drain contact 170 by passing through the lower etch stop layer 195”}) formed over the S/D structure (150 – Fig. 4 – [0067] – “source/drain pattern 150” – here the pattern is the structure) and through the dielectric layer (191 – Fig. 4 – [0099] – “insulating layer 191”);
and an S/D mask layer (192 – Fig. 4 – [0130] – “insulating layer 192 may be disposed on the first interlayer insulating layer 191 and the gate structure GS. The second interlayer insulating layer 192 may include an insulating material. The insulating material may be (and/or include) at least one of, for example, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, a low dielectric constant material, their combination, and/or the like” – layer 192 corresponds to a S/D mask layer as it contains the same materials as the applicant’s S/D mask layer) formed over the S/D contact structure (170), wherein the S/D mask layer (192) covers a portion of the dielectric layer (192).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the S/D structure as taught by Choi into Cheng, Basker, and Frougier.
An ordinary artisan would have been motivated to use the known technique of Choi in the manner set forth above to produce the predictable result [0006] – “to provide a semiconductor device that may improve element performance and reliability”.
Cheng, Basker, Frougier, and Choi do not expressly disclose the limitations of claim 6.
However, in an analogous art, Hsu teaches
a dielectric layer (122a – Fig. 1L – [0036] – “dielectric layer 122a is disposed on the protective layer 118a above the top surface of the gate stack structure 102”) formed over the gate structure (102 – Fig. 1L – [0036] – “dielectric layer 122a is disposed on the protective layer 118a above the top surface of the gate stack structure 102”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the dielectric layer over the S/D structure as taught by Hsu into Cheng, Basker, Frougier, and Choi.
An ordinary artisan would have been motivated to use the known technique of Hsu in the manner set forth above to produce the predictable result [0038] – “to effectively reduce the channel for ions to enter the spacer wall 116b, thereby reducing the number of ions entering the spacer wall 116b. In this manner, it is possible to effectively reduce the negative effects of ions on the operation of memory, and thus improving the reliability of the memory devices.”
Regarding claim 7, Cheng as modified by Basker, Frougier, Choi, and Hsu, teaches claim 6 from which claim 7 depends. Cheng, Basker, Frougier, and Hsu do not expressly disclose the limitations of claim 7.
However, in an analogous art, Choi teaches
(Original) The semiconductor structure as claimed in claim 6, wherein the S/D contact structure (170) comprises a barrier layer (171,180a – Fig. 4 – {[0110] – “source/drain barrier layer 171”}, {[0137] – “180 may include a first via barrier layer 180a”} – 180 is connected to 170 and considered part of the contact structure), wherein the S/D mask layer (192) is formed on a sidewall (180a – Fig 4 – [0137] – “barrier layer 180a may be extended along a sidewall”) and a top surface of the barrier layer (171 – Fig. 4 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the barrier layer structure as taught by Choi into Cheng, Basker, Frougier, and Hsu.
An ordinary artisan would have been motivated to use the known technique of Choi in the manner set forth above to produce the predictable result as stated above in claim 6.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Basker, Frougier, and Hsu.
Regarding claim 8, Cheng as modified by Basker, and Frougier, teaches claim 2 from which claim 8 depends. Cheng, Basker, and Frougier do not expressly disclose the limitations of claim 8.
However, in an analogous art, Hsu teaches
(Original) The semiconductor structure as claimed in claim 1, wherein the gate mask layer (130 – Fig. 1L – [0031] – “mask layer 130 is a trapezoid with both sides curved”) has a middle portion and a sidewall portion, and the middle portion has a first height, the sidewall portion has a second height, and the first height is greater than the second height (Fig. 1L annotated shows this).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the gate mask layer height structure as taught by Hsu into Cheng, Basker, and Frougier.
An ordinary artisan would have been motivated to use the known technique of Hsu in the manner set forth above to produce the predictable result to [0003] – “provides a memory structure and a manufacturing method therefor, which can effectively reduce the negative effects of ions on the operation of memory.”
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Basker, Frougier, Choi, and Lin et al. (US 9312356 B1 – hereinafter Lin).
Regarding claim 9, Cheng as modified by Basker and Frougier, teaches claim 2 from which claim 9 depends. Cheng, Basker, and Frougier do not expressly disclose the limitations of claim 9.
However, in an analogous art, Lin teaches
(Previously Presented) The semiconductor structure as claimed in claim 1, wherein the gate mask layer (220 – Fig. 9 – [4:42-43] – “mask layer 220 has a convex surface”) has a convex top surface and a convex bottom surface ([0090] – “The concave curved surface of the gate capping pattern 145 may, for example, coincide with the concave curved surface of the first gate electrode 120” – this corresponds to the gate mask layer, from the other perspective of the middle of 145 looking towards the substrate, this is a convex bottom surface).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the gate mask structure as taught by Lin into Cheng, Basker, and Frougier.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable result to [4:44-46] – “In this way, the top surface of the gate electrode 212 may be fully protected by the first mask layer 220 without being in direct contact with the outer environment.”
Allowable Subject Matter
Claims 10 and 15 are allowed.
In reference to claim 10, the prior art of record to the examiner’s knowledge does not teach or render obvious, at least to one skilled in the art, the instant invention regarding “a bottom surface of the S/D mask layer is lower than a bottom surface of the dielectric layer and higher than a top surface of the gate structure” in combination with the other recited limitations.
Claims 11-14 depend on claim 10 and are therefore allowable.
The closest prior art of record is Choi. Choi teaches a bottom surface of the S/D mask layer (192) is lower than a bottom surface of the dielectric layer (195) and higher than a top surface of the gate structure (GS).
This specific structure of “a bottom surface of the S/D mask layer is lower than a bottom surface of the dielectric layer and higher than a top surface of the gate structure” is not taught or rendered obvious by the prior art of record. The instant application states that the beneficial effect of the S/D mask layer structure is [0018] – “Therefore, no seam or void is formed in the gate mask layer and in the S/D mask layer, and the some issue caused by the seam or void can be resolved. Accordingly, the performance of the semiconductor structure is improved.”
In reference to claim 15, the prior art of record to the examiner’s knowledge does not teach or render obvious, at least to one skilled in the art, the instant invention regarding “the conductive cap layer has a recessed top surface, and the recessed top surface is lower than a top surface of the gate spacer” in combination with the other recited limitations.
Claims 16-20 depend on claim 15 and are therefore allowable.
The closest prior art of record is Wu et al. (US 9660084 B2 – hereinafter Wu). Wu teaches “the conductive cap layer (220) has a recessed top surface, and the recessed top surface is lower than a top surface of the gate spacer”
This specific structure of “the conductive cap layer has a recessed top surface, and the recessed top surface is lower than a top surface of the gate spacer” is not taught or rendered obvious by the prior art of record. The instant application states that the beneficial effect of the conductive cap layer structure is [0063] – “The conductive cap layer 152 is configured to provide conductive interfaces between the gate structure 142 and a gate conductive via (188, FIG. 2N, formed later) to electrically connect the gate contact structure gate contact structure to the gate structure 142.”
Pertinent Art
For the benefits of the Applicant, US 20230135946 A1, US 20180301564 A1, US 9502310 B1, and US 20060154423 A1 are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including " an isolation layer below the S/D structure, wherein the isolation layer is between the substrate and the S/D structure".
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to GARY ABEL whose telephone number is (571) 272-0246. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm (Eastern).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897