DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
In light of the remarks filed on December 11, 2025, which discussed the features of the recited species (p. 2-7 of the response), the examiner hereby withdraws the election of species requirement mailed on November 12, 2025. Claims 1-20 (all pending claims) are fully examined for patentability under 37 CFR 1.104. In view of the withdrawal of the restriction requirement, applicant(s) are advised that if any claim presented in a divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application. Once the restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. See In re Ziegler, 443 F.2d 1211, 1215, 170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01.
Claim Objections
Claim 19 is objected to because of the following informalities: line 2 of the claim recites, “vertical structures,” when it should read vertical memory structures. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 14, 15, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (United States Patent Application Publication No. US 2019/0304993 A1, hereinafter “Lee”).
In reference to claim 14, Lee discloses a device which meets the claim. Fig. 1-8 of Lee disclose a semiconductor device which comprises a base (100). There is a stack structure (LES, UES) that includes a first stack region (LES) and a second stack region (UES) on the first stack region (LES) on the base (100). First (132) and second (160) separation structures penetrate through the stack structure (LES, UES) in a vertical direction, perpendicular to an upper surface of the base (100), and parallel to each other, on the base (100). Vertical memory structures (VP1, VP2) penetrate through the stack structure (LES, UES) in the vertical direction, and between the first (132) and second (160) separation structures. Bitline contact plugs (164) are electrically connected to the vertical memory structures (VP1, VP2) and are on the vertical memory structures (VP1, VP2). Each of the first (132) and second (160) separation structures extends in a first direction (D3) which is parallel to the upper surface of the base (100). Each of the first (LES) and second (UES) stack regions includes interlayer insulating layers (110) and gate electrodes (150C1, 150C2) stacked alternately and repeatedly in the vertical direction.
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Annotated fig. 5B shows that the vertical memory structures include a first vertical memory structure spaced apart from the first separation structure (132) by a first distance, a second vertical memory structure spaced apart from the first separation structure (132) by a second distance greater than the first distance, a third vertical memory structure spaced apart from the first separation structure (132) by a third distance greater than the second distance, and a fourth vertical memory structure spaced apart from the first separation structure (132) by a fourth distance greater than the third distance. The first and third vertical memory structures are arranged in a second direction (D2) perpendicular to the first direction (D3). The second and fourth vertical memory structures are arranged in the second direction (D2). In a top view, a first virtual axis passing through centers of the first and third vertical memory structures is spaced apart from a second virtual axis passing through centers of the second and fourth vertical memory structures in the first direction (D3). Each of the first to fourth vertical memory structures includes a lower vertical portion (VP1) penetrating through the first stack region (LES) and an upper vertical portion (VP2) extending from the lower vertical portion (LES) and penetrating through the second stack region (UES). In fig. 5A and 5B, Lee discloses (p. 4-5, paragraph 48) a first distance (d1) between a center of an upper region (VP2) of the upper vertical portion (UES) of the first vertical memory structure and a center of an upper region (VP2) of the upper vertical portion (UES) of the second vertical memory structure is different from a second distance (d2) between a center of an upper region (VP1) of the lower vertical portion (LES) of the first vertical memory structure and a center of an upper region (VP1) of the lower vertical portion (LES) of the second vertical memory structure.
With regard to claim 15, Lee discloses (p. 4-5, paragraph 48) that the first distance (d1) is smaller than the second distance (d2).
In reference to claim 20, Lee discloses a device which meets the claim. Fig. 1-8 of Lee disclose a data storage system which comprises a semiconductor memory device including input/output pad lines (L2). It is understood that ends of the input/output pad lines (L2) are connected to input/output pads which are themselves connected to a required external control circuit/controller that provides control signals (write, read, erase) to the semiconductor memory device. The semiconductor memory device comprises a base (100). There is a stack structure (LES, UES) that includes a first stack region (LES) and a second stack region (UES) on the first stack region (LES) on the base (100). First (132) and second (160) separation structures penetrate through the stack structure (LES, UES) in a vertical direction, perpendicular to an upper surface of the base (100), and parallel to each other, on the base (100). Vertical memory structures (VP1, VP2) penetrate through the stack structure (LES, UES) in the vertical direction, and between the first (132) and second (160) separation structures. Bitline contact plugs (164) are electrically connected to the vertical memory structures (VP1, VP2) and are on the vertical memory structures (VP1, VP2). Each of the first (132) and second (160) separation structures extends in a first direction (D3) which is parallel to the upper surface of the base (100). Each of the first (LES) and second (UES) stack regions includes interlayer insulating layers (110) and gate electrodes (150C1, 150C2) stacked alternately and repeatedly in the vertical direction.
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Annotated fig. 5B shows that the vertical memory structures include a first vertical memory structure spaced apart from the first separation structure (132) by a first distance, a second vertical memory structure spaced apart from the first separation structure (132) by a second distance greater than the first distance, a third vertical memory structure spaced apart from the first separation structure (132) by a third distance greater than the second distance, and a fourth vertical memory structure spaced apart from the first separation structure (132) by a fourth distance greater than the third distance. The first and third vertical memory structures are arranged in a second direction (D2) perpendicular to the first direction (D3). The second and fourth vertical memory structures are arranged in the second direction (D2). In a top view, a first virtual axis passing through centers of the first and third vertical memory structures is spaced apart from a second virtual axis passing through centers of the second and fourth vertical memory structures in the first direction (D3). Each of the first to fourth vertical memory structures includes a lower vertical portion (VP1) penetrating through the first stack region (LES) and an upper vertical portion (VP2) extending from the lower vertical portion (LES) and penetrating through the second stack region (UES). In fig. 5A and 5B, Lee discloses (p. 4-5, paragraph 48) a first distance (d1) between a center of an upper region (VP2) of the upper vertical portion (UES) of the first vertical memory structure and a center of an upper region (VP2) of the upper vertical portion (UES) of the second vertical memory structure is different from a second distance (d2) between a center of an upper region (VP1) of the lower vertical portion (LES) of the first vertical memory structure and a center of an upper region (VP1) of the lower vertical portion (LES) of the second vertical memory structure.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Nam et al. (USPN 9,514,827 B1, hereinafter “Nam”).
In reference to claim 17, Lee does not disclose that a maximum width of the upper region (the channel hole) of the upper vertical portion of the first vertical memory structure is greater than a maximum width of the upper region (the channel hole) of the upper vertical portion of at least one of the second to fourth vertical memory structures. However Nam discloses tailoring the width of the channel hole of a vertical memory structure in order to attain desired program and erase speeds (column 12, lines 64-67, column 13, lines 1-8). Thus Nam makes it clear that the channel width is a result effective variable. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adjust the maximum channel width of the upper region of the upper vertical portion of the first vertical memory structure to be greater than the maximum channel width of the upper region of the upper vertical portion of at least one of the second to fourth vertical memory structures, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Therefore claim 17 is not patentable over Lee and Nam.
Allowable Subject Matter
Claims 1-13 are allowed.
Claims 16 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims AND if the language of claim 19 is corrected (see above section titled Claim Objections).
The following is a statement of reasons for the indication of allowable subject matter: in the examiner’s opinion, it would not be obvious to implement a semiconductor device which comprises a stack structure including a first stack region and a second stack region on the first stack region, on a base, first and second separation structures that penetrate through the stack structure in a vertical direction, perpendicular to an upper surface of the base, and parallel to each other, on the base, and vertical structures that penetrate through the stack structure in the vertical direction, and between the first and second separation structures, such that each of the first and second stack regions includes interlayer insulating layers and gate electrodes alternately and repeatedly stacked in the vertical direction, at least one of the gate electrodes in the first stack region includes a first wordline and at least one of the gate electrodes in the second stack region includes a second wordline, the vertical structures include a first vertical memory structure and a second vertical memory structure spaced apart from the first separation structure by different lengths, each of the first and second vertical memory structures includes a lower vertical portion penetrating through the first stack region, and an upper vertical portion extending from the lower vertical portion and penetrating through the second stack region, and a first distance between a center of an upper region of the upper vertical portion of the first vertical memory structure and a center of an upper region of the upper vertical portion of the second vertical memory structure is different from a second distance between a center of an upper region of the lower vertical portion of the first vertical memory structure and a center of an upper region of the lower vertical portion of the second vertical memory structure in combination with the specific insulating core, channel layer, and dielectric structure required for the vertical structures as required by the applicant in claim 1. In the examiner’s opinion, it would also not be obvious to implement a semiconductor device which comprises a stack structure including a first stack region and a second stack region on the first stack region, on a base, first and second separation structures that penetrate through the stack structure in a vertical direction, perpendicular to an upper surface of the base, and parallel to each other, on the base, and vertical memory structures that penetrate through the stack structure in the vertical direction, and between the first and second separation structures, bitline contact plugs electrically connected to the vertical memory structures and on the vertical memory structures, each of the first and second separation structures extends in a first direction, parallel to the upper surface of the base, each of the first and second stack regions includes interlayer insulating layers and gate electrodes stacked alternately and repeatedly in the vertical direction such that each of the first and second stack regions includes interlayer insulating layers and gate electrodes alternately and repeatedly stacked in the vertical direction, having the specific distancing between first, second, third, and fourth vertical memory structures and the first separation structure, the specific distancing of centers of the upper and lower portions of the first and second vertical memory structures in combination with the specific vertical support structure and the required orientation of the upper regions of the upper and lower portions of the vertical memory structures described by the applicant in claims 16, 18, and 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN QUINTO whose telephone number is (571)272-1920. The examiner can normally be reached Monday-Friday, 9-5:30.
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/KEVIN QUINTO/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893