DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4, 9-10 and 16-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SOENO (US 20170263754).
Regarding claim 1, SOENO discloses a transistor device, comprising:
a semiconductor substrate (the substrate 18, see fig 3, para 28) having a first major surface (upper surface 18a, see fig 3, para 28),
a cell field (the element range are 12, see fig 1-3, para 29) comprising a plurality of transistor cells (each cell of the cell region 42, see fig 3, para 29), and
an edge termination region laterally surrounding the cell field (the outer peripheral region 15, see fig 1-3, para 44),
wherein the transistor cells each comprise a drift region of a first conductivity type (each cell 42 comprises a portion of the drift region 26, see fig 3, para 40),
a first body region of a second conductivity type opposing the first conductivity type on the drift region (the p- body region 24b in each cell 42, see fig 1-3, para 33),
a second body region of the second conductivity type having a different doping concentration than the first body region (the p+ body region 24a in each cell 42, see fig 1-3, para 33),
a source region of the first conductivity type on the first body region (28 can be replaced by a drain region in ohmic contact with 54 to make the device a MOSFET, see para 65, which would make n-type region 22 a source region, see fig 1-3, para 32) and
a gate electrode (gate electrode 30 of each transistor, see fig 1-3, para 30);and
an elongate source contact (source contact 55, see fig 1-3, para 48) having opposing first and second distal ends (the right and left ends of 55 along the cross-section III-III shown in fig 3, see fig 1-3),
wherein for each of the transistor cells, the elongate source contact is in contact with the source region (55 is in at least indirect contact with all of the source regions 22 by means of 51, see fig 3, para 45),
wherein for each of the transistor cells the second body region has a lateral extent such that the second body region and the second distal end of the elongate source contact are nonoverlapping (the second body regions 24a in 42 do not overlap with an end of 55 along a vertical direction, see fig 1-3, para 48 and 33) and the second body region extends laterally beyond the first distal end of the elongate source contact (24a in 42 extends in the x and y directions in an area that is beyond the edge of 55, see fig 3).
Regarding claim 2, SOENO discloses the transistor device of claim 1, wherein:
for each of the transistor cells the second body region is in contact with the first body region (24b is in direct contact with 24a in 42, see fig 3, para 33).
Regarding claim 4, SOENO discloses the transistor device of clam 1, wherein the second body region has a greater doping concentration than the first body region (24a is a p+ region which has a higher doping concentration than p- region 24b, see fig 3, para 33).
Regarding claim 9, SOENO discloses the transistor device of claim 1, wherein the cell field comprises:
a plurality of elongate trenches that extend from the first major surface into the semiconductor substrate (the plurality of trenches 40 In region 12, see fig 1-3, para 29); and
a plurality of elongate mesas between neighboring ones of the elongate trenches (the portions of 18 between each of the trenches 40, see fig 3, para 29),
wherein for each of the transistor cells, the first body region, the second body region and the source region are formed in a respective one of the elongate mesas (22, 24a and 24b are formed between the trenches 40 in region 42, see fig 3).
Regarding claim 10, SOENO discloses the transistor device of claim 9, wherein the gate electrode is positioned in the elongate trench (gate electrode 30 is located in trench 40, see fig 3, para 29 and 30).
Regarding claim 16, SOENO discloses the transistor device of claim 1, wherein the transistor cells extend lengthwise in a first lateral direction (the cells 42 extend in the y-direction, see fig 1-3), and wherein the elongate source contact extends lengthwise in the first lateral direction (the source electrode 55 extends in the x-direction, see fig 1-3).
Regarding claim 17, SOENO discloses the transistor device of claim 16, wherein for each of the transistor cells, the second body region is in contact with the first body region (24a and 24b are in direct contact, see fig 3).
Regarding claim 18, SOENO discloses the transistor device of claim 1, wherein for each of the transistor cells, the source region and the second body region are nonoverlapping (22 and 24a do not overlap along a vertical direction, see fig 3).
Regarding claim 19, SOENO discloses a transistor device, comprising:
a semiconductor substrate (the substrate 18, see fig 1-3, para 28) comprising a first major surface (the top surface of 18 in fig 3, see fig 1-3) and a first side face (the right side surface of 18 shown in fig 3 which is also the right surface of 18 in fig 1);
a first trench (the x-direction trench 40a above the cross-section III-III in the y-direction, see fig 1-3, para 29 and figure I below) and a second trench (the x-direction trench 40a below the cross-section III-III in the y-direction, see fig 1-3, para 29 and figure I below) formed in the first major surface and extending in a first direction (the trenches 40a extend lengthwise in the x-direction, see fig 1-3, para 29);
a source region (the device can have a drain region in ohmic contact with 54 to form an N-MOSFET which would make one of the n-type region 22 on the top surface a source region, see fig 1-3, para 32 and 65 and figure II below) of a first conductivity type (22 is n-type, see para 32);
a first body region (one of the p-type regions 24b, see fig 3, para 33) of a second conductivity type (p-type, see para 33) opposing the first conductivity type;
a second body region (one of the p+ regions 24a, see fig 3, para 33 and figure II below) of the second conductivity type having a higher doping concentration than the first body region (24a is a p+ region and 24b is a p- region); and
a source contact (top contact 55, see fig 3, para 48 and figure II below) in contact with the source region,
wherein the source region extends from a first position along the first direction away from the first side face (the rightmost edge of the source 22 in fig 3, see figure II below),
wherein the source contact extends from a second position along the first direction away from the first side face (the rightmost edge of 55, see fig 3 and figure II below), the second position being located closer to the first side face than the first position (see figure II below),
wherein the second body region extends from a third position along the first direction towards the first side face (the leftmost edge the region 24a which is the 2nd body region, see fig 3 and figure II below), the third position being located between the first position and the second position (see figure II below) and between the first trench and the second trench (everything in fig 3 is between the 1st and 2nd trench since the cross-section is taken between those trenches, see fig 1-3 and figure I below),
wherein the source region is laterally spaced apart from the second body region in an area between the first trench and the second trench (the region 22 which is the source region is spaced apart from the region 24a which is the 2nd body region, see fig 3 and figure II below).
Regarding claim 20, SOENO discloses the transistor device of claim 19, wherein the first body region, the second body region and the source region extend between the first trench and the second trench in a second direction that is orthogonal to the first direction (everything in fig 3 is between the 1st and 2nd trench since the cross-section is taken between those trenches, see fig 1-3 and figures I and II below).
Regarding claim 21, SOENO discloses the transistor device of claim 19, further comprising:
an edge termination trench arranged between the first side face and the second body region (the outermost trench 40 in fig 3 is between the edge of 18 and 24a, see fig 3, para 29),
wherein in the first direction, the second body region terminates before reaching the edge termination trench (the second body region 24a does not reach to the outermost trench 40, see fig 3, para 29 and figure II below).
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Figure I: SOENO figure 1 with added annotations.
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Figure II: SOENO figure 3 with added annotations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over SOENO (US 20170263754) in view of SAGGIO (US 20130149838).
Regarding claim 3, SOENO discloses the transistor device of claim 1.
SOENO fails to explicitly disclose a device, wherein the second body region laterally overlaps the elongate source contact by a distance between 0.5 microns and 15 microns.
SAGGIO teaches a device, wherein the second body region (portion 8 of the p-doped region which overlaps with source contact 19, see fig 9A, para 69 and 76) laterally overlaps the elongate source contact by a distance between 0.5 pm and 15pm (the width of 8 can be 3 microns so it will overlap with 19 at a distance of 3 microns, see fig 9a, para 79).
SOENO and SAGGIO are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of SOENO with the specific spacing of SAGGIO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of SOENO with the specific spacing of SAGGIO in order to horizontally limit electric field lines in reverse biasing (see SAGGIO para 77).
Claim(s) 5, 7-8 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over SOENO (US 20170263754) in view of OOSAWA (US 20120199900).
Regarding claim 5, SOENO discloses the transistor device of claim 1.
SOENO fails to explicitly disclose a device, wherein a doping concentration of the second body region is substantially constant along the length of the elongate source contact or increases in a direction from the cell field into the edge termination region or increases from the second distal end to the first distal end of the elongate source contact.
OOSAWA teaches a device, wherein a doping concentration of the second body region is substantially constant along the length of the elongate source contact (24 has a uniform doping, see fig 13, para 74) or increases in a direction from the cell field into the edge termination region or increases from the second distal end to the first distal end of the elongate source contact.
SOENO and OOSAWA are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of SOENO with the doping of OOSAWA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of SOENO with the doping of OOSAWA in order to improve the recovery withstand of the device (see OOSAWA para 6).
Regarding claim 7, SOENO discloses the transistor device of claim 1.
SOENO fails to explicitly disclose a device, wherein the second body region is positioned in an inactive region of the cell field.
OOSAWA teaches a device, wherein the second body region is positioned in an inactive region of the cell field (24 extends outside the element or active region 2, see fig 13, para 56).
SOENO and OOSAWA are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of SOENO with the inactive region of OOSAWA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of SOENO with the inactive region of OOSAWA in order to improve the recovery withstand of the device (see OOSAWA para 6).
Regarding claim 8, SOENO discloses the transistor device of claim 7.
SOENO fails to explicitly disclose a device, wherein the second body region extends into the edge termination region.
OOSAWA teaches a device, wherein the second body region extends into the edge termination region (24 extends into the region surrounding 2, see fig 13, para 56).
SOENO and OOSAWA are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of SOENO with the edge termination region of OOSAWA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of SOENO with the edge termination region of OOSAWA in order to improve the recovery withstand of the device (see OOSAWA para 6).
Regarding claim 15, SOENO and OOSAWA disclose the transistor device of claim 7.
SOENO further discloses a device,
wherein the second body region is positioned under the one or more of a gate metallization,
a gate finger, and
a source finger (24a is located under source finger 51, see fig 3, para 43).
Claim(s) 11, 13 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over SOENO (US 20170263754) in view of MATSUURA (US 20090026535).
Regarding claim 11, SOENO discloses the transistor device of claim 10.
SOENO fails to explicitly disclose a device, further comprising a field plate positioned in the elongate trench, the gate electrode being arranged above and electrically insulated from the field plate.
MATSUURA teaches a device, further comprising a field plate (fig 3, 8G1, para 11) positioned in the elongate trench, the gate electrode being arranged above and electrically insulated from the field plate (10G1 is above and insulated from 8G1, see fig 3, para 11).
SOENO and MATSUURA are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of SOENO with the field plate of MATSUURA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of SOENO with the field plate of MATSUURA in order to improve the breakdown voltage of the device (see MATSUURA para 71).
Regarding claim 13, SOENO discloses the transistor device of claim 9.
SOENO fails to explicitly disclose a device, wherein in plan view,
the second body region has a tapered form having a tip, and
wherein the tip is positioned in the elongate mesa or in the elongate trench.
MATSUURA teaches a device, wherein in plan view,
the second body region has a tapered form having a tip (100 has a tapering height at its left and right ends, see fig 2), and
wherein the tip is positioned in the elongate mesa or in the elongate trench (the right tapering end of 100 is in a mesa between trenches 6c and 6a, see fig 2).
SOENO and MATSUURA are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of SOENO with the body region shape of MATSUURA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of SOENO with the body region shape of MATSUURA in order to improve the breakdown voltage of the device (see MATSUURA para 71).
Regarding claim 22, SOENO discloses the transistor device of claim 19.
SOENO fails to explicitly disclose a device, wherein an end of the source contact is enclosed by the first body region.
MATSUURA teaches a device, wherein an end of the source contact is enclosed by the first body region (the projections of the source contact 21S into body 14 are surrounded by body 14, see fig 2, para 13).
SOENO and MATSUURA are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of SOENO with the source electrode shape of MATSUURA because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of SOENO with the source electrode shape of MATSUURA in order to improve the breakdown voltage of the device (see MATSUURA para 71).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over SOENO (US 20170263754) in view of OHSE (US 20180366574).
Regarding claim 14, SOENO discloses the transistor device of claim 9.
SOENO fails to explicitly disclose a device, wherein the second body region comprises a plurality of subsections arranged in a row and spaced apart by gaps.
OHSE teaches a device, wherein the second body region comprises a plurality of subsections arranged in a row and spaced apart by gaps (there are a plurality of regions of 4 spaced apart by gaps of 6, see fig 2).
SOENO and OHSE are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of SOENO with the body region shape of OHSE because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of SOENO with the body region shape of OHSE in order to increase breakdown capability (see OHSE para 41).
Claim(s) 23-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over SOENO (US 20170263754) in view of SAITO (US 20120056262).
Regarding claim 23, SOENO discloses the transistor device of claim 1.
SOENO fails to explicitly disclose a device, wherein for at least some of the transistor cells, the source region is laterally spaced apart from the second body region in an area between adjacent gate electrodes.
SAITO teaches a device, wherein for at least some of the transistor cells, the source region is laterally spaced apart from the second body region in an area between adjacent gate electrodes (13 and 14 are spaced apart in a region between gate electrodes 32, see fig 1, para 28, 22 and 24).
SOENO and SAITO are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of SOENO with the body and source region shape of SAITO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of SOENO with the body and source region shape of SAITO in order to improve reliability (see SAITO para 62).
Regarding claim 24, SOENO discloses the transistor device of claim 23.
SOENO fails to explicitly disclose a device, wherein the elongate source contact spans the area between adjacent gate electrodes where the source region is laterally spaced apart from the second body region.
SAITO teaches a device, wherein the elongate source contact spans the area between adjacent gate electrodes where the source region is laterally spaced apart from the second body region (33 spans the area between adjacent gate electrodes 32, see fig 1, para 24 and 26).
SOENO and SAITO are analogous art because they both are directed towards vertical semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of SOENO with the body and source region shape of SAITO because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of SOENO with the body and source region shape of SAITO in order to improve reliability (see SAITO para 62).
Response to Arguments
Applicant’s arguments, filed 11/20/2025, with respect to the rejection(s) of claim(s) 1 under 35 U.S.C. 102 in view of OOSAWA (US 20120199900) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of SOENO (US 20170263754), see above.
Applicant's arguments filed 11/20/2025 regarding the rejection of claim 19 by 35 U.S.C. 102 over SOENO et al have been fully considered but they are not persuasive. Regarding claim 19, the applicant argues that SOENO does not disclose every element of the claimed invention because it does not disclose a device wherein the source or body regions are located between the two trenches, and it does not disclose a device with a source region that is laterally spaced apart from the second body region. These arguments are unpersuasive for two reasons. Firstly, SOENO discloses a device with a source region (one of the regions 22, see fig 3) a first body region (one of the regions 24b, see fig 3) and a second body region (one of the regions 24a, see fig 3) are located between a pair of trenches because all of SOENO fig 3 is a cross-section taken between and parallel to two different trenches (see SOENO fig 1). Therefore, everything shown in fig 3 is between the two trenches, including the source and body regions and their edges. Secondly, SOENO disclose in fig 3 a device with several source and body regions, some of which are laterally spaced apart from each other.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811