DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after 16 March 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s reply filed on 08 December 2025.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 10, 11 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (U.S. Pub. 2021/0020602) in view of Cho et al. (U.S. Pub. 2016/0104665).
Claims 1, 10 and 11: Chen et al. discloses a power semiconductor module arrangement in Fig. 9 and in paragraphs 28, 30, 35 and 46, comprising:
a circuit carrier (110, left 114, right 114, and 118B) comprising an electrically insulating substrate (110, left 114 and right 114) and an upper metallization layer (118B) disposed on upper side of the electrically insulating substrate (110, left 114 and right 114); and
a plurality of inlays (SC2 and SC3),
wherein each of the inlays (SC2 and SC3) are modular units comprising terminals (308),
wherein each of inlays (SC2 and SC3) is embedded within the electrically insulating substrate (110, left 114 and right 114), and
wherein the upper metallization layer comprises (118B) conductive connectors that extend over the inlays (SC2 and SC3) and connect with the terminals (308) of the terminals of each of the inlays (SC2 and SC3).
Chen et al. appears not to explicitly disclose the plurality of inlays are power stage inlays that each comprise first and second transistor dies and a driver die configured to control switching of the first and second transistor dies,
wherein each of the power stage inlays comprising terminals that are electrically connected to the first and second transistor dies and the driver die,
wherein the power stage inlays are each configured as integrated half-bridge circuits, and wherein the first and second transistor dies of the power stage inlays form the high-side switch and the low- side switch of the integrated half-bridge circuit, respectively, and
wherein the first and second transistor dies of each of the power stage inlays are configured as vertical devices with first and second load terminals disposed on opposite sides of the respective transistor die.
Cho et al., however, in Fig. 5 and in paragraphs 2, 18, 54, 56 and 57, discloses a power stage inlay (504) that comprises first and second transistor dies (Q1 and Q2, respectively) and a driver die (528) configured to control switching of the first and second transistor dies (Q1 and Q2, respectively),
wherein the power stage inlay (504) comprising terminals (532b, 532c, 532d and 532e) that are electrically connected to the first and second transistor dies (Q1 and Q2, respectively) and the driver die (528),
wherein the power stage inlay (504) is configured as integrated half-bridge circuits (half bridge), and wherein the first and second transistor dies (Q1 and Q2, respectively) of the power stage inlay (504) form the high-side switch and the low-side switch of the integrated half-bridge circuit, respectively, and
wherein the first and second transistor dies (Q1 and Q2, respectively) of the power stage inlay is configured as vertical devices with first and second load terminals (terminals associated with 548) disposed on opposite sides (upper and lower side) of the respective transistor die in order to convert input voltage to a desired output voltage.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Chen et al. with the disclosure of Cho et al. to have made the plurality of inlays to be power stage inlays that each comprise first and second transistor dies and a driver die configured to control switching of the first and second transistor dies, and
wherein each of the power stage inlays comprising terminals that are electrically connected to the first and second transistor dies and the driver die,
wherein the power stage inlays are each configured as integrated half-bridge circuits, and wherein the first and second transistor dies of the power stage inlays form the high-side switch and the low- side switch of the integrated half-bridge circuit, respectively, and
wherein the first and second transistor dies of each of the power stage inlays are configured as vertical devices with first and second load terminals disposed on opposite sides of the respective transistor die in order to convert input voltage to a desired output voltage (paragraph 2 of Cho et al.).
Claim 2: Chen et al. in view of Cho et al. discloses the power semiconductor module arrangement of claim 1, and Chen et al., in paragraph 28, further discloses wherein the electrically insulating substrate (110, left 114 and right 114) comprises a dielectric resin (110 comprises resin) that contacts outer edge sides of the inlays (SC2 and SC3). Since Chen et al. in view of Cho et al. discloses the power stage inlays, Chen et al. in view of Cho et al would disclose wherein the electrically insulating substrate comprises a dielectric resin that contacts outer edge sides of the power stage inlays.
Claim 3: Chen et al. in view of Cho et al. discloses the power semiconductor module arrangement of claim 2, and Chen et al., in Fig. 9 and in paragraph 28, further discloses wherein the electrically insulating substrate (110, left 114 and right 114) further comprises a dielectric core structure (left 114 and right 114), and wherein each of the inlays (SC2 and SC3) is arranged on or within the dielectric core structure (left 114 and right 114). Since Chen et al. in view of Cho et al. discloses the power stage inlays, Chen et al. in view of Cho et al would disclose wherein each of the power stage inlays is arranged on or within the dielectric core structure.
Claim 4: Chen et al. in view of Cho et al. discloses the power semiconductor module arrangement of claim 3, and Chen et al., in Fig. 9, further discloses wherein the dielectric core structure (left 114 and right 114) comprises one or more recesses (recess formed by left 114 and right 114), and wherein each of the inlays (SC2 and SC3) is arranged within the one or more recesses (recess formed by left 114 and right 114). Since Chen et al. in view of Cho et al. discloses the power stage inlays, Chen et al. in view of Cho et al would disclose wherein each of the power stage inlays is arranged within the one or more recesses.
Claim 5: Chen et al. in view of Cho et al. discloses the power semiconductor module arrangement of claim 3, and Chen et al., in Fig. 9, further discloses wherein two or more of the of the inlays (SC2 and SC3) are arranged within one of the recesses (recess formed by left 114 and right 114). Since Chen et al. in view of Cho et al. discloses the power stage inlays, Chen et al. in view of Cho et al would disclose wherein two or more of the of the power stage inlays are arranged within one of the recesses.
Claim 6: Chen et al. in view of Cho et al. discloses the power semiconductor module arrangement of claim 1, and Chen et al., in Fig. 9, further discloses wherein each of the inlays (SC2 and SC3) comprise a plurality of upper I/O terminals (308) disposed on an upper side of the respective inlay (SC2 and SC3), and wherein the conductive connectors (118B) comprise I/O connectors (118B) that extend over and are in direct ohmic contact with the upper I/O terminals (308). Since Chen et al. in view of Cho et al. discloses the power stage inlays, Chen et al. in view of Cho et al would disclose wherein each of the power stage inlays comprise a plurality of upper I/O terminals disposed on an upper side of the respective power stage inlay, and wherein the conductive connectors comprise I/O connectors that extend over and are in direct ohmic contact with the upper I/O terminals.
Claim 14: Chen et al. in view of Cho et al. discloses the power semiconductor module arrangement of claim 1, and Chen et al., in Fig. 9 and in paragraph 23, further discloses wherein each of the inlays (SC2 and SC3) are laminate devices composing a plurality of laminate dielectric layers (202A) and structured metallization layers (202-TM and 202-LM) stacked on the laminate dielectric layers (202A), and wherein the terminals (308) are provided from outermost ones (202-TM) of the structured metallization layers (202-TM and 202-LM). Since Chen et al. in view of Cho et al. discloses the power stage inlays, Chen et al. in view of Cho et al would disclose wherein each of the power stage inlays are laminate devices composing a plurality of laminate dielectric layers and structured metallization layers stacked on the laminate dielectric layers, and wherein the terminals are provided from outermost ones of the structured metallization layers.
Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. in view of Cho et al. as applied to claims 1 and 6 above, and further in view of U.S. Pub. 2020/0105635, hereinafter referred to as Yu ‘635.
Claim 7: Chen et al. in view of Cho et al. discloses the power semiconductor module arrangement of claim 6.
Chen et al. in view of Cho et al. appears not to explicitly disclose wherein each of the power stage inlays comprise lower I/O terminals disposed on a lower side of the respective power stage inlay, and wherein each of the power stage inlays comprise through-via connections electrically connecting the upper I/O terminals and the lower I/O terminals of the respective power stage inlay.
Yu ‘635, however, in Fig. 2I and in paragraphs 39, 66, 71 and 73, discloses each of the power stage inlays (108, 112b, 200, 300, and lower portions of 134) comprise lower I/O terminals (108) disposed on a lower side of the respective power stage inlay, and wherein each of the power stage inlays comprise through-via connections (112b) electrically connecting the upper I/O terminals (lower portions of 134) and the lower I/O terminals (108) of the respective power stage inlay in order to transmit signals in the completed package.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Chen et al. in view of Cho et al. with the disclosure of Yu ‘635 to have made each of the power stage inlays comprise lower I/O terminals disposed on a lower side of the respective power stage inlay, and wherein each of the power stage inlays comprise through-via connections electrically connecting the upper I/O terminals and the lower I/O terminals of the respective power stage inlay in order to electrically couple the power stage inlays to other elements in the device (paragraph 47 of Yu ’635).
Claim 8: Chen et al. in view of Cho et al. discloses the power semiconductor module arrangement of claim 1.
Chen et al. in view of Cho et al., as applied to claim 1, appears not to explicitly disclose wherein each of the power stage inlays comprise a plurality of upper voltage supply terminals disposed on an upper side of the respective power stage inlay, wherein the upper voltage supply terminals are electrically connected to load terminals from the first and second transistor dies.
Cho et al., however, in Fig. 5 and in paragraphs 54 and 56, further discloses wherein the power stage inlay comprises a plurality of upper voltage supply terminals (532b and 532d) disposed on an upper side (lower side of 504) of the power stage inlay (504), wherein the upper voltage supply terminals (532b and 532d) are electrically connected to load terminals (terminals associated with 548) from the first and second transistor dies (Q1 and Q2, respectively).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Chen et al. in view of Cho et al., as applied to claim 1, with the further disclosure of Cho et al. to have made each of the power stage inlays comprise a plurality of upper voltage supply terminals disposed on an upper side of the respective power stage inlay, wherein the upper voltage supply terminals are electrically connected to load terminals from the first and second transistor dies in order to provide input voltage and ground to the power stage inlays.
Chen et al. in view of Cho et al. appears not to explicitly disclose wherein the conductive connectors comprise voltage supply connectors that extend over and are in direct ohmic contact with the upper voltage supply terminals.
Yu ‘635, however, in Fig. 2I and in paragraph 54, discloses the conductive connectors (upper portion of 134) comprise voltage supply connectors (upper portion of 134) that extend over and are in direct ohmic contact with the upper voltage supply terminals (lower portion of 134).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Chen et al. in view of Cho et al. with the disclosure of Yu ‘635 to have made the conductive connectors comprise voltage supply connectors that extend over and are in direct ohmic contact with the upper voltage supply terminals in order to route voltage and ground to the power stage inlays.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. in view of Cho et al. in view of Yu ‘635 as applied to claim 8 above, and further in view of U.S. Pub. 2022/0352082, hereinafter referred to as Yu ‘082
Claim 9: Chen et al. in view of Cho et al. in view of Yu ‘635 discloses the power semiconductor module arrangement of claim 8.
Chen et al. in view of Cho et al. in view of Yu ‘635 appears not to explicitly disclose wherein each of the power stage inlays comprise through-via connections that electrically connect the upper voltage supply terminals are electrically connected to the load terminals from the first and second transistor dies that face away from the upper side of the respective power stage inlay.
Yu ‘082, however, in Fig. 12B and in paragraph 43, discloses the power stage inlay (50c, 336, 154) comprise through-via connections (336) that electrically connect the upper voltage supply terminals (154) are electrically connected to the load terminals from the first and second transistor dies (50c) that face away from the upper side of the respective power stage inlay.
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It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Chen et al. in view of Cho et al. in view of Yu ‘635 with the disclosure of Yu ‘082 to have made each of the power stage inlays comprise through-via connections that electrically connect the upper voltage supply terminals are electrically connected to the load terminals from the first and second transistor dies that face away from the upper side of the respective power stage inlay in order to provide a voltage supply to the lower side of the power inlay.
Response to Arguments
Applicant's arguments filed 08 December 2025 have been fully considered but they are not persuasive.
Applicant contends chips SC2 and SC3 of Chen et al. are not inlays because they are discrete semiconductor chips, wherein the claimed “inlay” is not a semiconductor chip because the claimed “inlay” is a package structure that accommodates multiple semiconductor dies.
Examiner notes that Applicant’s specification does not explicitly define an inlay as having to have multiple semiconductor dies. Although the claims require the inlay to comprise multiple dies, neither the specification nor the claims exclude the interpretation of Chen’s chips SC2 and SC3 as the claimed inlays.
Applicant contends chips SC2 and SC3 of Chen et al. are sub-components of a complete package structure and package 504 of Cho et al. is a complete semiconductor package, therefore the person of ordinary skill would not regard Cho’s semiconductor package 504 as a viable replacement for Chen’s chips SC2 and SC3.
Examiner notes that Chen et al. discloses chip SC2 can be integrated circuit chips (paragraph 33) and chip SC3 is similar to chip SC2 (paragraph 46). Cho et al. discloses integrated circuits require power converters (paragraph 2) and element 504 is a power converter. Therefore, one of ordinary skill in the art would regard element 504 as an element that could be in an integrated circuit such as chips SC2 and SC3 of Chen et al.
Applicant contends the rational provided that such a modification would be obvious “in order to convert input voltage to a desired output voltage” lacks rational underpinning.
Examiner notes Cho et al. discloses integrated circuits require conversion of an input voltage to a lower or higher output voltage (paragraph 2). Therefore, one of ordinary skill would be motivated to modify Chen et al. with the disclosure of Cho et al. in order to convert input voltage to a desired output voltage.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.L/ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815