Attorney Docket Number: 86326248US04
Filing Date: 07/21/2022
Claimed Priority Date: 01/23/2020 (PCT/CN2020/074025)
Inventor: Chi
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the amendment filed on 11/07/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The amendment filed on 11/07/2025 in reply to the previous Office action mailed on 08/08/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-21.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following features must be shown or the features canceled from the claims. No new matter should be entered.
A first and second power module disposed in a die, as recited in claims 1 and 16
One end of a second redistribution metal connected to an upper surface of a first bond pad, and the other end of the second redistribution metal connected to an upper surface of a second bond pad, as recited in claims 4 and 19
A first capacitor disposed in a die, as recited in claims 5 and 20
A first inductor disposed in a die, as recited in claims 11 and 21
A second capacitor disposed in a die, as recited in claim 12
A first radio frequency path and a second radio frequency path disposed in a die, as recited in claim 13
A second inductor disposed in a die, as recited in claim 14
A second power module configured to supply power to a low-pass filter of a first radio frequency path, as recited in claim 15
A chip apparatus coupled to a baseband processing chip, wherein the chip apparatus comprises a die, a first bond pad, a second bond pad, and a first solder pad (and including all other elements of claim 16 as recited in lines 5-10), as recited in claim 16
A printed circuit board, wherein a baseband processing chip and a chip apparatus are fastened to the printed circuit board, as recited in claim 17
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference characters not mentioned in the description:
DCDC1 in figure 8
DCDC2 in figure 8
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Sharan (US 2016/0190113) in view of Gu (US 2018/0350762), Sinha (US 2004/0187085), Choi (US 2021/0217482), and Wilz (US 2017/0237424).
Regarding claim 1, Sharan (see, e.g., fig. 2) shows most aspects of the instant invention, including a chip apparatus 202 comprising:
a die 206;
a first bond pad 132;
a second bond pad 136; and
a first pad 234 (see, e.g., par.0019/ll.6-8)
wherein:
the first bond pad 132 and second bond pad 136 are disposed on an upper surface of the die 206;
a first power module 214 and a second power module 214 are disposed in the die (see, e.g., par.0025/ll.11-14);
the first power module 214 is coupled to the first bond pad 132; and
the first pad 234 is coupled to the first bond pad 132 and the second bond pad 136 and is separately coupled to an external power supply VIN of the chip apparatus (see, e.g., par.0023/ll.5-7)
Although Sharan shows most aspects of the instant invention, including that the die 206 can include multiple power modules (see, e.g., par.0025/ll.11-14), Sharan fails to show that the second power module is coupled to the second bond pad 136. Furthermore, although Sharan teaches that Sharan’s first pad 234 is a pad, that solder can be appropriate connecting material (see, e.g., par.0029/ll.12-13), and that Sharan’s input voltage may come from a circuit board (see, e.g., par.0023/ll.5-7), Sharan fails to specify that Sharan’s first pad comprises solder.
Gu, in a similar device to Sharan and in the same field of endeavor, also teaches that a die can internally house multiple power modules (see, e.g., Gu: figs. 3B-3C and par.0041/ll.1-3). Gu further teaches that having multiple power modules in such a die can allow for the input voltage supplied to the die to be converted to a variety of voltages for multitudinous desired logic operations (see, e.g., Gu: figs. 3B-3C and par.0041/ll.4-11). Additionally, Gu teaches that using solder as connecting material can allow for the physical coupling of a circuit board and device, as well as power supply routing from a circuit board to a die (see, e.g., Gu: figs. 3B-3C and pars.0029/ll.1-4, 0038/ll.6-8, and 0040/ll.1-4).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Sharan’s die-embedded second power module connected to Sharan’s input voltage pathway, i.e., coupled to Sharan’s second bond pad, so as to allow for the input voltage supplied to Sharan’s die to be converted to a variety of voltages for various desired logic operations, as taught by Gu. Furthermore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Sharan’s first pads be composed of solder, as taught by Gu, so as to allow Sharan’s first pads to both physically couple Sharan’s die and circuit board and to appropriately route Sharan’s input voltage to Sharan’s die.
Regarding the limitation “the second power module is coupled to the second bond pad to provide noise isolation”, although Sharan/Gu teaches that Sharan’s second power module is coupled to Sharan’s second bond pad (see paragraphs 8-11 above), Sharan does not explicitly state that Sharan’s second power module being coupled to Sharan’s second bond pad is dedicated to providing noise isolation. Sharan, however, does explicitly state that Sharan’s structure beneficially isolates various circuitry components, that Sharan’s die may comprise more than one power module, and that Sharan’s power modules can inherently comprise structures dedicated to reducing noise, demonstrating that Sharan recognizes that noise isolation is a pivotal necessity for the functionality of semiconductor devices (see, e.g., pars.0003/ll.1-7, 0021/ll.17, and par.0025/ll.11-14).
Accordingly, particularly since Sharan recognizes that noise isolation can be accomplished through Sharan’s power modules and in Sharan’s device, the specific claim limitation that “the second power module is coupled to the second bond pad to provide noise isolation” is a property of Sharan and Gu’s device. 2. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). “When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not.” In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). Therefore, the prima facie case can be rebutted by evidence showing that the prior art products do not necessarily possess the characteristics of the claimed product. In re Best, 562 F.2d at 1255, 195 USPQ at 433. See also Titanium Metals Corp.v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985). 3. In the instant case, Sharan/Gu teaches the same second power module coupled to the second bond pad and the same noise isolation provisions as recited in the claim, therefore, the second power module and second bond pad coupling will have the provided noise isolation characteristics also recited in the claim.
Furthermore, as recognized in the art, including Sinha (see, e.g., Sinha: pars.0004-0005), Choi (see, e.g., Choi: pars.0010-0011), and Wilz (see, e.g., par.0033/ll.6-9), the performance optimization and increased integration of semiconductor devices create a need to isolate noise, so as to ensure the reduction of performance degradation or parasitic effects. Along these lines, Sinha, in the same field of endeavor, teaches that pads and power modules in integrated circuit structures may be chosen by one of ordinary skill in the art to optimize noise isolation (see, e.g., Sinha: par.0017/ll.10-20). Choi, in the same field of endeavor, teaches that the coupling and disposition of various electronic components, including power modules, may be manipulated in a variety of ways so as to implement a tighter feedback loop and isolate noise (see, e.g., Choi: par.0057 and 0058/ll.1-2). Finally, Wilz, in the same field of endeavor, further teaches that noise isolation can be achieved through a variety of mechanisms, including through the integration of separate power modules in a die (see, e.g., pars.0035/ll.12-16 and 0070/ll.1-2).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Sharan’s second power module coupled to Sharan’s second bond pad, as taught by Sharan/Gu, in a way configured to provide noise isolation, as suggested by Sinha, Choi, and Wilz, so as to optimize device performance, parasitic reduction, and electrical characteristics. The motivation for such modification or inclusion arises from the well-known industry trend towards performance optimization and increased integration, as well as the benefits of improved reliability and cost minimization (see, e.g., Sinha: par.0005).
Regarding claim 2, Gu (see, e.g., fig. 3B) shows a redistribution layer (VSS, VDD in 320) (see, e.g., par.0040/ll.4-14) that is disposed on the upper side of die 310, wherein a first solder pad 360 is disposed on an upper surface of the redistribution layer.
Regarding claim 5, Sharan (see, e.g., fig. 2) shows a first capacitor 212 disposed in the die, and a first end (left-side end of 212) and a second end (right-side end of 212) of the first capacitor are coupled to a high level VIN and a low level GND respectively.
Claims 16-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sharan in view of Gu, Sinha, Choi, Wilz, and Han (US 2022/0159529).
Regarding claim 16, Sharan/Gu/Sinha/Choi/Wilz shows most aspects of the instant invention (see paragraphs 8-15 above). It is noted that since the chip apparatus comprisals of claim 16 are identical to the chip apparatus comprisals of claim 1, the comments stated above in paragraphs 8-15 as applied to claim 1 are considered to be repeated here as applied to claim 16. Sharan (see, e.g., fig. 9) further shows that Sharan’s chip apparatus may internally or externally include processing resources and radio frequency components or radio circuitry (see, e.g., pars.0019/ll.17-18 and 0026/ll.7-9), and that Sharan’s chip apparatus may further be coupled to a board in a wireless communication apparatus 100 (see, e.g., pars.0047/ll.1-3, 0048, and 0078). Sharan additionally teaches that such a wireless communication apparatus may include multitudinous unlimited other components also coupled to the board that may be combined with any of the other components (and thus, coupled to the chip apparatus) (see, e.g., par.0046). Sharan, however, fails to specify that these components include a baseband processing chip.
Han, in a similar wireless communication device to Sharan and in the same field of endeavor, teaches a radio frequency circuitry and a baseband circuitry including baseband processing chips coupled to a circuit board (see, e.g., Han: pars.0086/ll.1-4, 0109/ll.1-5 and 0109/ll.9-11). Han further teaches that such a baseband circuitry can be coupled to an application circuitry hosting similar components to Sharan’s device (see, e.g., Han: fig. 3 and par.0070). Han explains that such a baseband circuitry can be configured to carry out various radio or network protocol and control functions that enable communications with one or more radio networks via the radio frequency circuitry, and that the baseband circuitry can interface with the application circuitry to generate and process baseband signals (see, e.g., Han: pars.0104/ll.1-4 and 0104/ll.22-25).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a radio frequency circuitry and a baseband circuitry (comprising baseband processing chips) coupled to Sharan’s chip apparatus in Sharan’s wireless communication apparatus, as taught by Han, so as to facilitate various radio and network protocol and control functions as associated with the radio components of Sharan’s device, to expand Sharan’s radio network communications, and to generate and process baseband signals associated with Sharan’s chip apparatus.
Regarding claim 17, Sharan (see, e.g., fig. 9) teaches that Sharan’s wireless communication apparatus 100 further comprises a printed circuit board 2 and an antenna 16, wherein the chip apparatus is fastened to the printed circuit board (see, e.g., par.0078). Han (see, e.g., Han: par.0109/ll.1-5) teaches that the baseband chip is fastened to a printed circuit board. Han (see, e.g., Han: fig. 4 and pars.0104/ll.18-25 and 0122/ll.1-5) further shows that the antenna 611 is configured to provide a radio frequency signal for the chip apparatus 505.
Regarding claim 20, Sharan (see, e.g., fig. 2) shows a first capacitor 212 disposed in the die, and a first end (left-side end of 212) and a second end (right-side end of 212) are coupled to a high level VIN and a low level GND respectively.
Allowable Subject Matter
Claims 3-4, 6-15, 18-19, and 21 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
Response to Arguments
With regards to the drawings, the applicant argues:
Regarding the objections under 37 CFR 1.83(a), the specification provides the required support for the claims. Furthermore, the elements of the claims, such as those being “disposed in the die”, as disclosed are sufficiently supported by the presented specification and drawings. Additionally, regarding the objections under 37 CFR 1.84(p)(5), one of average skill in the art knows that DCDC refers to direct current to direct current voltage converters. Thus the nomenclature in the FIG. indicates that these power modules are direct current to direct current converter type power sources.
The examiner responds:
Regarding the applicant’s arguments concerning 37 CFR 1.83(a), although the specification may provide support for the claimed features of the application, support from the disclosure is not a sufficient substitute for compliance with 37 CFR 1.83(a). 37 CFR 1.83(a) directly and explicitly states that “the drawing in a nonprovisional application must show every feature of the invention specified in the claims”. The claims at present explicitly recite various features that the present drawings do not depict, and the absence of such depictions in the drawings prevents a clear, unambiguous visual understanding of the claimed structures from the features alone.
For example, the applicant’s drawings fail to illustrate various features being in a die (a planar view alone is insufficient for illustrating such features in a structure, as such figures fail to provide a clear and unambiguous visual understanding from the features alone the intended placement/location/disposition/etc. of the features within the structure; furthermore, the application itself makes no mention regarding the intention of “dashed lines” in such figures, and even the applicant’s remarks on page 8 admit that such features “cannot be seen from examining from a surface of the die”), a claimed redistribution metal architecture, and a printed circuit board. Regarding other features not illustrated in the drawings, please see paragraph 3 above. Furthermore, although the applicant’s arguments and specification make note of a “die” in figure 8, the figure itself fails to disclose the location of such a “die” and fails to illustrate how various features are meant to be disposed in such a “die”. To reassert the issue, and as again exemplarily evinced by the applicant’s arguments on page 8, features disposed in a die “cannot be seen from examining from a surface of the die”. This issue is similarly present in the drawings’ failure to depict “one end of a second redistribution metal connected to an upper surface of a first bond pad, and the other end of the second redistribution metal connected to an upper surface of a second bond pad”, as recited in claims 4 and 19, where the planar view presented by the applicant fails to show the claimed architecture (e.g., an upper surface of the redistribution metal connected to an upper surface of a second bond pad) of the redistribution metal. Accordingly, the drawings fail to depict various features explicitly recited in the claims, preventing a clear and unambiguous visual understanding of the claimed structures from the features alone.
Additionally, it is further noted that all dependent claims must inherit the features of the claims from which they depend. Accordingly, the figures the applicant cites as corresponding to features only present in dependent claims must be congruent with the figures the applicant cites as corresponding to features present in the claims from which such dependent claims depend. As a singular and non-exhaustive example of the substantiative issue, the feature wherein “a first radio frequency receive path and a second radio frequency receive path are disposed in a die”, as recited in claim 13, must be consistent with the die recited in the claim from which it depends, i.e., the “die” comprising a “first bond pad”, a “second bond pad… disposed on an upper surface of the die”, “a first power module and a second power module…disposed in the die”, and other features as recited in claim 1. At current, despite the applicant’s arguments, the application makes no mention of how such figures are meant to relate to one another, and as such, the consistency between such figures has not been sufficiently established. In fact, as an example, the specification regards figures 6 and 9, which the applicant argues represent the undisclosed features of claims 1 and 13 respectively, as “a schematic diagram of a chip apparatus” and “a schematic diagram of another chip architecture”, further illustrating the disconnect between figures (see, e.g., US 2022/0359475: pars.0069/ll.1 and 0095/ll.1-2). This issue is similarly present in the drawings’ failure to depict “a chip apparatus coupled to a baseband processing chip”, as recited in claim 16, wherein the chip apparatus comprises “a die, a first bond pad, a second bond pad, and a first solder pad” and various other features recited concerning the die in claim 16. Although the applicant’s arguments cite figure 3 as the figure representative of the “chip apparatus” recited in claim 16, the specification makes no mention of “a die, a first bond pad, a second bond pad, and a first solder pad” and other features concerning the die being contained in the “RFIC” (radio frequency integrated circuit) cited by the applicant to mean the “chip apparatus”. Furthermore, the specification makes no mention of any figure illustrating a chip apparatus comprising “a die, a first bond pad, a second bond pad, and a first solder pad” and other features concerning the die, as recited in claim 16, being included in an “RFIC”, as argued by the applicant. Accordingly, the consistency between figures has not been sufficiently established, even in the case of independent claim 16. An objection to drawings under 37 CFR 1.83(a) is not a dispositive finding that the claim lacks written support; rather it identifies that the figures do not show a claimed structural feature necessary for understanding the invention. Whether or not the written description may contain support for the feature is a separate inquiry.
Regarding the applicant’s arguments concerning 37 CFR 1.84(p)(5), whether one of ordinary skill in the art would recognize the feature in question is irrelevant to compliance with 37 CFR 1.84(p)(5). To comply with 37 CFR 1.84(p)(5), all reference characters mentioned in the drawings must also be mentioned in the description. As the applicant’s specification fails to include reference characters DCDC1 and DCDC2, the drawings fail to comply with 37 CFR 1.84(p)(5).
For all the reasons listed above, applicant’s request to withdraw the drawings objections is denied.
With regards to the claims, the applicant argues:
Regarding claim 1, claim 1 requires first and second power modules that are disposed in the die while Sharan teaches, at most, just one. Furthermore, the single power supply of Sharan is distributed over two die (the Uncore die and the Cores die which contains the capacitor which is part of the power supply). Regarding claim 2, VSS and VDD are merely power supply lines coming from external power sources VSS and VDD and are provided to die 310. Figure 3B does not show a redistribution layer that is part of the chip as the claims require.
The examiner responds:
Regarding the first argument concerning claim 1, as cited on page 5 of the previous Office action mailed on 08/08/2025, Sharan (see, e.g., par.0025/ll.11-14) states that while only one power module is shown, there may be one or more power modules. Accordingly, Sharan does not teach “at most, just one” power module. Furthermore, as cited in the previous Office action, Gu (see, e.g., Gu: figs. 3B-3C and par.0041/ll.4-11) teaches the beneficial use of more than one power module in a die. Accordingly, Sharan and Gu teach the corresponding features of the claim. Furthermore, regarding the second argument concerning claim 1, as also cited on page 5 of the previous Office action, figure 2 of Sharan shows that the “capacitor” may be included in a single die alongside other circuitry. Accordingly, Sharan shows a working alternative to the statement “the single power supply of Sharan is distributed over two die (the Uncore die and the Cores die which contains the capacitor which is a part of the power supply)”, as argued by the applicant.
Regarding claim 2, as cited in paragraph 14 of the previous Office action mailed on 08/08/2025, par.0040/ll.4-14 of Gu explicitly state “the positive power supply is routed, via one or more RDLs in substrate 320, to the decoupling capacitor 390 as well as to one of the a first merged bump site including post 352(0) and one or more solder 364. The negative power supply is routed, via one or more RDLs in substrate 320, to the decoupling capacitor 390 as well as to a second merged bump site including post 352(1) and one or more solder 364. The positive power supply and the negative power supply may be routed on separate RDLs in the substrate 320, and the order of RDLs may vary according to different designs”. It is noted that claim 2 only states “a redistribution layer that is disposed on the upper surface of the die” and that “the first solder pad is disposed on an upper surface of the redistribution layer” and not “a redistribution layer that is part of the chip”, as the applicant argues. Accordingly, Gu teaches the claimed aspects of the instant invention.
Applicant’s other arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant’s amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action.
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at (703) 756-1521 and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Shamita.Hanumasagar@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814