DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment/Argument
Applicant’s arguments, see remarks, filed 04/07/2026, with respect to the rejection(s) of claim(s) 1-22 and 26-28 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of an updated prior art search.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the housing claimed in claim 33 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 33 is objected to because of the following informalities: “of the layer of glass” should say “of the glass layer”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 35 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. The claimed housing is not shown in the drawings, clarification on where the housing is depicted or correction/cancellation is required.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, 9-15, 19-26 and 29-32 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1-4, 9-15, 19-26, 29-32 recites the limitation "conductive contacts" throughout the claims when it is clearly used to identify two different conductive contacts. One is between the first and second glass sheet and the other is above both glass sheets. Correction is required throughout the identified claims.
Claim 2 recites the limitation “wherein the interconnect structure is a first interconnect structure located in the first dielectric layer”, but this limitation conflicts with claim 1 because the interconnect structure comprises the first through-glass via, the second through-glass via, and the conductive trace located between the first and second glass sheets, which are all located in the glass layer not the first dielectric layer. Correction is required.
Claim 13 recites the limitation “the electrically conductive path comprising an interconnect structure located in the first dielectric layer or the second dielectric layer”, but this limitation conflicts with the same claim because the interconnect structure comprises the first through-glass via, the second through-glass via, and the conductive trace located between the first and second glass sheets, which are all located in the glass layer not the first dielectric layer. Correction is required.
Claim 26 recites the limitation “wherein the interconnect structure is a first interconnect structure located in the first dielectric layer or second dielectric layer”, but this limitation conflicts with claim 1 because the interconnect structure comprises the first through-glass via, the second through-glass via, and the conductive trace located between the first and second glass sheets, which are all located in the glass layer not the first or second dielectric layers. Correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-4, 9-10, 26 and 30-31 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Juang et al. (US-20230411171-A1 – hereinafter Juang).
Regarding claim 1, Juang teaches an apparatus (Fig.20 6; ¶0052), comprising:
a first dielectric layer (Fig.20 PM21-23; ¶0030) comprising conductive pads (Fig.20 MF21; ¶0030) arranged at a first pitch;
a second dielectric layer (Fig.20 PM11-14; ¶0021) located above the first dielectric layer (PM21-23), the second dielectric layer (PM11-14) comprising conductive contacts (Fig.20 MF11; ¶0021) arranged into a first set (left half) and a second set (right half), the first set (left half) further arranged at a second pitch;
a glass layer (Fig.20 102; ¶0051) located between the first dielectric layer (PM21-23) and the second dielectric layer (PM11-14), the glass layer (102) comprising a first glass sheet (Fig.20 102c; ¶0051), a second glass sheet (Fig.20 102a; ¶0051), a first through-glass via (Fig.20 DVc; ¶0051) extending through the first glass sheet (102c), a second through-glass via (Fig.20 DVa; ¶0051) extending through the second glass sheet (102a), and a conductive contact or a conductive trace (Fig.20 LP1; ¶0051) in a layer of solder resist or dielectric (Fig.20 102b; ¶0051) between the first glass sheet (102c) and the second glass sheet (102a); and
an electrically conductive path between a conductive contact (MF11) of the first set (left set) and one of the conductive pads (MF21), the electrically conductive path comprising an interconnect structure, the interconnect structure comprising the first through-glass via (DVc), the second through-glass via (DVa), and the conductive contact or the conductive trace (LP1).
Regarding claim 3, Juang teaches the apparatus of claim 1, wherein the first dielectric layer (PM21-23) comprises more than one sublayers, individual sub-layers comprising a respective conductive trace and via (PM21-23 comprises three layers that include conductive traces and vias).
Regarding claim 4, Juang teaches the apparatus of claim 1, wherein the second dielectric layer (PM11-14) comprises more than one sub-layers, individual sub-layers comprising a respective conductive trace and a via (PM11-14 comprises four layers that include conductive traces and vias).
Regarding claim 9, Juang teaches the apparatus of claim 1, further comprising:
a first die (Fig.20 D21; ¶0045) attached to the first set (left side); and
a second die (Fig.20 D23; ¶0045) attached to the second set (right side).
Regarding claim 10, Juang teaches the apparatus of claim 9, further comprising an encapsulant (Fig.20 E; ¶0045) located over the first die and second die (D12 and D23).
Regarding claim 26, Juang teaches the apparatus of claim 1, wherein the interconnect structure is a first interconnect structure located in the first dielectric layer or second dielectric layer , and wherein the electrically conductive path further comprises a second interconnect structure located in the glass layer and coupled to the first interconnect structure (The device taught by Fig.20 of Juang comprises interconnect structures in the first/second dielectric layer and the glass layer).
Regarding claim 30, Juang teaches the apparatus of claim 1, wherein the conductive contact or the conductive trace (SL11 could be the first conductive trace) is the conductive contact.
Regarding claim 31, Juang teaches the apparatus of claim 1, wherein the conductive contact or the conductive trace is the conductive trace (SL11 could be the first conductive trace), and wherein, in a cross-sectional view, the first through-glass via is non-overlapping with the second through-glass via (the electrical path could go through non-overlapping vias).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 2 and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Juang in view of Elsherbini et al. (US-20230207439-A1 – hereinafter Elsherbini).
Regarding claim 29, Juang teaches the apparatus of claim 1, further comprising a local interconnect component (Fig.20 40; ¶0048) located in the glass layer (102).
Juang does not teach wherein the local interconnect component to provides electrical communication between a first conductive contact in the first set and a first conductive contact in the second set.
Elsherbini teaches a bridge die (Fig.6A 665; ¶0056 of Elsherbini) that is located in a glass layer (Fig.6A 660; ¶0056 of Elsherbini) for providing electrical communication between a first set of conductive contacts (Fig.6A 605 left half; ¶0056 of Elsherbini) and a second set of conductive contacts (Fig.6A 605 right half; ¶0056 of Elsherbini).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the bridge die of Elsherbini (665 of Elsherbini) with the glass core of Juang (102 of Juang) to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit of enabling direct communication between the first and second sets of conductive contacts, which may be connected to other components like dies (as demonstrated in Fig.6A of Elsherbini).
Regarding claim 2, the aforementioned combination of Juang in view of Elsherbini teaches the apparatus of claim 29, wherein the interconnect structure is a first interconnect structure located in the first dielectric layer, wherein the electrically conductive path further comprises a second interconnect structure located in the glass layer and a third interconnect structure located in the second dielectric layer, and wherein the second interconnect structure is configured to couple the first interconnect structure to the third interconnect structure (The device taught by Fig.20 of Juang comprises interconnect structures in the first/second dielectric layer and the glass layer).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Juang in view of Ge et al. (US-20240274496-A1 – hereinafter Ge).
Regarding claim 11, Juang teaches the apparatus of claim 10, wherein the apparatus is a panel.
Juang does not teach the apparatus further comprising a cooling component located on the panel.
Ge teaches a heat sink (Fig.2 500; ¶0071 of Ge) disposed over a panel.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the heat sink of Ge (500 of Ge) with the device taught by Juang for the benefit of providing cooling to the top chips (D21/D23 of Juang).
Claim(s) 13-15, 19 and 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Juang in view of Mayukh et al. (US-20230367087-A1 – hereinafter Mayukh).
Regarding claim 13, Juang teaches an apparatus (Fig.20 6; ¶0052, comprising:
a first dielectric layer (Fig.20 PM21-23; ¶0030) comprising conductive pads (Fig.20 MF21; ¶0030) arranged at a first pitch;
a second dielectric layer (Fig.20 PM11-14; ¶0021) located above the first dielectric layer (PM21-23), the second dielectric layer (PM11-14) comprising conductive contacts (Fig.20 MF11; ¶0021) arranged into a first set (left set) and a second set (right set), the first set of the conductive contacts being arranged at a second pitch that is smaller than the first pitch (MF11 has a smaller pitch overall compared to MF21);
a glass layer (Fig.20 102; ¶0051) located between the first dielectric layer (PM21-23) and the second dielectric layer (PM11-14), the glass layer (102) comprising a first glass sheet (550-1), a second glass sheet (550-2), a first through-glass via (Fig.20 DVc; ¶0051) extending through the first glass sheet (Fig.20 102c; ¶0051), a second through-glass via (Fig.20 DVa; ¶0051) extending through the second glass sheet (Fig.20 102a; ¶0051), and a conductive contact or a conductive trace (Fig.20 LP1; ¶0051) in a layer of solder resist or dielectric (Fig.20 102b; ¶0051) between the first glass sheet (102c) and the second glass sheet (102a); and
an electrically conductive path between a second conductive contact (MF11) from the first set (left set) and one of the conductive pads (MF21), the electrically conductive path comprising an interconnect structure located in the first dielectric layer or the second dielectric layer (see 112 rejection), the interconnect structure comprising the first through-glass via (DVc), the second through-glass via (DVa), and the conductive contact or the conductive trace (LP1).
Juang does not teach a photonic integrated circuit (PIC) located in the glass layer and in electrical communication with a first conductive contact from the first set.
Mayukh teaches a PIC (Fig.3 320; ¶0035 of Mayukh) within a glass substrate (Fig.3 310; ¶0035 of Mayukh) for transmitting optical signals (¶0035 of Mayukh)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the PIC device of Mayukh (320 of Mayukh) with the device taught by Juang (6 of Juang) to arrive at the claimed invention. A practitioner of ordinary skill would have been motivated to make this modification for optical signal applications (¶0013 of Mayukh)
Regarding claim 14, the aforementioned combination of Juang in view of Mayukh from claim 13 teaches the apparatus of claim 13, wherein the PIC comprises a silicon micro-ring resonator (this is a very common and well-known in the art component of a PIC device).
Regarding claim 15, the aforementioned combination of Juang in view of Mayukh from claim 14 teaches the apparatus of claim 14, further comprising a waveguide in the glass layer (¶0036 of Mayukh).
Regarding claim 19, the aforementioned combination of Juang in view of Mayukh from claim 13 teaches the apparatus of claim 13, further comprising:
a first die (Fig.20 D21; ¶0045) attached to the first set (left set); and
a second die (Fig.20 D23; ¶0045) attached to the second set (right set).
Regarding claim 32, the aforementioned combination of Juang in view of Mayukh from claim 13 teaches the apparatus of claim 13, wherein a thickness of the PIC is equal to a thickness of the layer of glass (this limitation does not patentably distinguish claim 32 over claim 13 because the particular thickness of PIC is a matter of design choice).
Claim(s) 20-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Juang in view of Taniguchi et al. (US-20160056089-A1 – hereinafter Taniguchi).
Regarding claim 20, Juang teaches the apparatus of claim 1.
Juang does not teach the device further comprising:
a micro-channel located in the glass layer, the micro-channel configured to accommodate a flow of a liquid coolant.
Taniguchi teaches a semiconductor package (Fig.9 60; ¶0155 of Taniguchi) comprising coolant channels (Fig.9 41/42; ¶0080 of Taniguchi) and coolant cavities (Fig.9 S; ¶0058 of Taniguchi) within a substrate.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the coolant channels and cavities of Taniguchi (41/42 and S of Taniguchi) with the substrate taught by Juang (102 of Juang) to arrive at the claimed invention. A practitioner of ordinary skill would have been motivated to make this modification for the benefit of providing cooling to the device (6 of Juang) during operation.
Regarding claim 21, the aforementioned combination of Juang in view of Taniguchi from claim 20 teaches the apparatus of claim 20, wherein the micro-channel (41/42 of Taniguchi) has a lateral portion near the first set (Fig.9 of Taniguchi depicts the coolant channels entering from the right side of the device which includes a lateral portion).
Regarding claim 22, the aforementioned combination of Juang in view of Taniguchi from claim 20 teaches the apparatus of claim 20, further comprising a cavity (S of Taniguchi) located in the glass layer (102 Juang).
Claim(s) 33-34 and 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Juang in view of Pearson et al. (US-20240126692-A1 – hereinafter Pearson).
Regarding claim 33, Juang teaches an apparatus, comprising:
a first panel (Fig.20 6; ¶0052), comprising:
a first dielectric layer (Fig.20 PM21-23; ¶0030) comprising first conductive pads (Fig.20 MF21; ¶0030) arranged at a first pitch;
a second dielectric layer (Fig.20 PM11-14; ¶0021) located above the first dielectric layer (PM21-23), the second dielectric layer (PM11-14) comprising first conductive contacts (Fig.20 MF11; ¶0021) arranged at a second pitch;
a first glass layer (Fig.20 102; ¶0051) located between the first dielectric layer (PM21-23) and the second dielectric layer (PM11-14), the first glass layer (102) comprising a first glass sheet (Fig.20 102c; ¶0051), a second glass sheet (Fig.20 102a; ¶0051), a first through-glass via (Fig.20 DVc; ¶0051) extending through the first glass sheet (102c), a second through-glass via (Fig.20 DVc; ¶0051) extending through the second glass sheet (102a), and a conductive trace or a conductive contact (Fig.20 LP1; ¶0051) in a first layer of solder resist or dielectric (Fig.20 102b; ¶0051) between the first glass sheet (102c) and the second glass sheet (102a);
a first electrically conductive path between one of the first conductive contacts (MF11) and one of the first conductive pads (MF21), the first electrically conductive path comprising a first interconnect structure, the first interconnect structure comprising the first through-glass via (DVc), the second through-glass via (DVa), and the conductive trace or the conductive contact (LP1) in the first layer of solder resist or dielectric (102b); and
a plurality of first integrated circuit dies (Fig.20 D21-23; ¶0041), individual first integrated circuit dies (D21) attached to one or more of the first conductive contacts (MF11).
Juang does not teach a second panel, comprising:
a third dielectric layer comprising second conductive pads;
a fourth dielectric layer located above the third dielectric layer, the fourth dielectric layer comprising second conductive contacts;
a second glass layer located between the third dielectric layer and the fourth dielectric layer, the second glass layer comprising a third glass sheet, a fourth glass sheet, a third through-glass via extending through the third glass sheet, a fourth through-glass via extending through the fourth glass sheet, and a conductive trace or a conductive contact in a second layer of solder resist or dielectric between the third glass sheet and the fourth glass sheet;
a second electrically conductive path between one of the second conductive contacts and one of the second conductive pads, the second electrically conductive path comprising a second interconnect structure, the second interconnect structure comprising the third through-glass via, the fourth through-glass via, and the conductive trace or the conductive contact in the second layer of solder resist or dielectric; and
a plurality of second integrated circuit dies attached to the second conductive contacts; and
a substrate to which the first panel and the second panel are attached, the substrate comprising one or more fifth dielectric layers, individual fifth dielectric layers comprising one or more third conductive traces and one or more vias, the one or more third conductive traces and the one or more vias comprising a third electrically conductive path between one of the first conductive contacts and one of the second conductive contacts.
Pearson teaches a substrate (Fig.1 102; ¶0019 of Pearson) comprising a plurality of chip packages (Fig.1 104; ¶0020 of Pearson). Additionally, it is well-known in the art that PCB boards are dielectric layers comprising conductive traces/vias for electrically connecting a plurality of chip packages.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use a PCB board and a duplicate panel of the one taught by Juang (6 of Juang) to create a layout like the layout taught by Pearson (Fig.1 of Pearson) to arrive at the claimed invention. This modification is obvious because it is a matter of design choice.
Regarding claim 34, the aforementioned combination of Juang in view of Pearson from claim 33 teaches the apparatus of claim 33, wherein the first through-glass via is nonoverlapping with the second through-glass via (the electrical path could go through non-overlapping vias).
Regarding claim 36, the aforementioned combination of Juang in view of Pearson from claim 33 teaches the apparatus of claim 33, wherein one of the plurality of first integrated circuit dies is a power management integrated circuit component (¶0041 of Juang).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Juang in view of Ge, and further in view of Pearson et al. (US-20240126692-A1 – hereinafter Pearson).
Regarding claim 12, the aforementioned combination of Juang in view of Ge from claim 11 teaches the apparatus of claim 11, wherein the panel is a first panel.
The aforementioned combination does not teach the apparatus further comprising:
a substrate;
the first panel;
and a second panel being attached to the substrate.
Pearson teaches a substrate (Fig.1 102; ¶0019 of Pearson) comprising a plurality of chip packages (Fig.1 104; ¶0020 of Pearson).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use a PCB board and a duplicate panel of the one taught by Juang (6 of Juang) to create a layout like the layout taught by Pearson (Fig.1 of Pearson) to arrive at the claimed invention. This modification is obvious because it is a matter of design choice.
Claim(s) 35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Juang in view of Pearson, and further in view of Newlin (US- 20220351901-A1).
Regarding claim 35, the aforementioned combination of Juang in view of Pearson from claim 33 teaches the apparatus of claim 33.
The aforementioned combination does not teach the apparatus further comprising a housing, wherein the first panel, the second panel, and the substrate are enclosed by, or integrated with the housing.
Newlin teaches a housing (Fig.6 61; ¶0021 of Newlin) for encapsulating a chip (Fig.6 41; ¶0021 of Newlin) and a substrate (Fig.6 21; ¶0021 of Newlin).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to add the housing of Newlin (61 of Newlin) to the device taught by Juang in view of Pearson to arrive at the claimed invention. A practitioner would have been motivated to make this modification for the benefit of protection from the outside environment (¶0021 of Newlin).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/T.J.K./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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