Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 10, 13-17 and 19-21 rejected under 35 U.S.C. 103 as being unpatentable over Li (CN 113098493) of record, in view of Zhao (CN 116072676) of record.
Regarding Claim 1
FIG. 10 of Li discloses a semiconductor device having a standard cell, comprising: a first bottom transistor (M14) in a first row; a first top transistor (M12) disposed above the first bottom transistor in the first row, the first bottom transistor and the first top transistor sharing a first gate structure (G7); a second bottom transistor (M13) in a second row next to the first row; a second top transistor (M11) disposed above the second bottom transistor in the second row, the second bottom transistor and the second top transistor sharing a second gate structure (G6); and a first bottom-transistor-level metal line (Connecting M14S) extending laterally from a first source/drain region of the first bottom transistor to a source/drain region of the second bottom transistor.
Li is silent with respect to “the first bottom-transistor-level metal line has a top surface at a higher elevation than the first source/drain region of the first bottom transistor”; “the first bottom-transistor-level metal line has a bottommost position level with a bottommost position of the first source/drain region of the first bottom transistor” and “the first bottom-transistor-level metal line laterally extends from a sidewall of the first source/drain region of the first bottom transistor to a sidewall of the source/drain region of the second bottom transistor”.
FIG. 24 of Zhao discloses a similar semiconductor device, wherein the first bottom-transistor-level metal line (420, horizontal portion) has a top surface at a higher elevation than the first source/drain region (right 410) of the first bottom transistor; wherein the first bottom-transistor-level metal line has a bottommost position level with a bottommost position of the first source/drain region of the first bottom transistor; and wherein the first bottom-transistor-level metal line laterally extends from a sidewall of the first source/drain region of the first bottom transistor to a sidewall of the source/drain region of the second bottom transistor.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Li, as taught by Zhao. The ordinary artisan would have been motivated to modify Li in the above manner for purpose of improving the working performance of the semiconductor structure (Contents of the Invention of Zhao).
Regarding Claim 10
FIG. 10 of Li discloses a semiconductor device having a standard cell, comprising: a first bottom transistor (M14) disposed on a substrate (10) in a first row; a first top transistor (M12) disposed above the first bottom transistor in the first row, the first bottom transistor and the first top transistor sharing a first gate structure (G7); a second bottom transistor (M13) in a second row next to the first row; a second top transistor (M11) disposed above the second bottom transistor in the second row, the second bottom transistor and the second top transistor sharing a second gate structure (G6); and a first top-transistor-level metal line (V18) extending laterally from a first source/drain region of the first top transistor to a first source/drain region of the second top transistor.
Li is silent with respect to “the first top-transistor-level metal line has a top surface at a higher elevation than the first source/drain region of the first top transistor” and “the first top-transistor-level metal line has a bottommost position level with a bottommost position of the first source/drain region of the first top transistor”.
FIG. 24 of Zhao discloses a similar semiconductor device, wherein the first top-transistor-level metal line (horizontal portion 620) has a top surface at a higher elevation than the first source/drain region (left 610) of the first top transistor; wherein the first top-transistor-level metal line has a bottommost position level with a bottommost position of the first source/drain region of the first top transistor.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Li, as taught by Zhao. The ordinary artisan would have been motivated to modify Li in the above manner for purpose of improving the working performance of the semiconductor structure (Contents of the Invention of Zhao).
Regarding Claim 13
FIG. 8 of Li discloses an inter-level source/drain via (V12) electrically connecting a second source/drain region of the first top transistor to a source/drain region of the first bottom transistor.
Regarding Claim 14
FIG. 8 of Li discloses a bottom-transistor-level metal line (V13) extending from the source/drain region of the first bottom transistor to a source/drain region of the second bottom transistor.
Regarding Claim 15
FIG. 23 of Zhao discloses a VDD line (140) inlaid in the substrate (100); a second top-transistor-level metal line (620) extending from a second source/drain region of the second top transistor to a position above the VDD line; and a via extending vertically from the second top-transistor-level metal line to the VDD line.
Regarding Claim 16
FIG. 20 of Zhao discloses a Vss line (140) inlaid in the substrate (100); a bottom-transistor-level metal line (420) extending from a source/drain region of the first bottom transistor to a position above the Vss line; and a via extending vertically from the bottom-transistor-level metal line to the Vss line.
Regarding Claim 17
FIG. 10 of Li discloses a method, comprising: forming a first bottom semiconductor layer (M14) and a second bottom semiconductor layer (M13) over a substrate (10), the first and second bottom semiconductor layers are arranged in adjacent rows; forming first bottom source/drain regions (M14S/M14D) on the first bottom semiconductor layer, and second bottom source/drain regions (M13S/M13D) on the second bottom semiconductor layer; forming a first top semiconductor layer (M12) above the first bottom semiconductor layer, and a second top semiconductor layer (M11) above the second bottom semiconductor layer; forming first top source/drain regions (M12S/M12D) on the first top semiconductor layer, and second top source/drain regions (M11S/M11D) on the second top semiconductor layer; forming an inter-level source/drain via between a first one of the first top source/drain regions and a first one of the first bottom source/drain regions; and forming a first gate structure (G7) wrapping around a channel region in the first bottom semiconductor layer and a channel region in the first top semiconductor layer, and forming a second gate structure (G6) wrapping around a channel region in the second bottom semiconductor layer and a channel region in the second top semiconductor layer; and forming a bottom-transistor-level metal line.
Li is silent with respect to “the first bottom-transistor-level metal line has a top surface at a higher elevation than the first source/drain region of the first bottom transistor”; “the first bottom-transistor-level metal line has a bottommost position level with a bottommost position of the first source/drain region of the first bottom transistor”.
FIG. 24 of Zhao discloses a similar semiconductor device, wherein the first bottom-transistor-level metal line (horizontal portion of 420) has a top surface at a higher elevation than the first source/drain region (left 410) of the first bottom transistor; wherein the first bottom-transistor-level metal line has a bottommost position level with a bottommost position of the first source/drain region of the first bottom transistor.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Li, as taught by Zhao. The ordinary artisan would have been motivated to modify Li in the above manner for purpose of improving the working performance of the semiconductor structure (Contents of the Invention of Zhao).
Regarding Claim 19
FIG. 8 of Li discloses forming a top-transistor-level metal line (VOUT4) laterally extending from the first one of the first top source/drain regions to one of the second top source/drain regions.
Regarding Claim 20
FIG. 8 of Li discloses the inter-level source/drain via is formed prior to forming the first gate structure and the second gate structure.
Regarding Claim 21
FIG. 10 of Li discloses the bottom-transistor-level metal line is in direct contact with said one of the first and second bottom source/drain regions.
Claims 1-3, 8-10 and 17 rejected under 35 U.S.C. 103 as being unpatentable over Li (CN 113098493) of record, in view of Hong (EP 3979306) of record, in view of Yamagami (U.S. Patent Pub. No. 2006/0027835) of record.
Regarding Claim 1
FIG. 10 of Li discloses a semiconductor device having a standard cell, comprising: a first bottom transistor (M14) in a first row; a first top transistor (M12) disposed above the first bottom transistor in the first row, the first bottom transistor and the first top transistor sharing a first gate structure (G7); a second bottom transistor (M13) in a second row next to the first row; a second top transistor (M11) disposed above the second bottom transistor in the second row, the second bottom transistor and the second top transistor sharing a second gate structure (G6); and a first bottom-transistor-level metal line (Connecting M14S) extending laterally from a first source/drain region of the first bottom transistor to a source/drain region of the second bottom transistor.
Li is silent with respect to “the first bottom-transistor-level metal line has a top surface at a higher elevation than the first source/drain region of the first bottom transistor”; “the first bottom-transistor-level metal line has a bottommost position level with a bottommost position of the first source/drain region of the first bottom transistor” and “the first bottom-transistor-level metal line laterally extends from a sidewall of the first source/drain region of the first bottom transistor to a sidewall of the source/drain region of the second bottom transistor”.
FIG. 5A of Hong discloses a similar semiconductor device, wherein the first bottom-transistor-level metal line (522) has a top surface at a higher elevation than the first source/drain region (512) of the first bottom transistor; and wherein the first bottom-transistor-level metal line has a bottommost position level with a bottommost position of the first source/drain region of the first bottom transistor.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Li, as taught by Hong. The ordinary artisan would have been motivated to modify Li in the above manner, because the claimed configuration was a matter of choice (evidenced by various embodiments of Hong).
Li as modified by Hong is silent with respect to ““the first bottom-transistor-level metal line laterally extends from a sidewall of the first source/drain region of the first bottom transistor to a sidewall of the source/drain region of the second bottom transistor””.
FIG. 3 of Yamagami discloses a similar semiconductor device, wherein the first bottom-transistor-level metal line (160) laterally extends from a sidewall of the first source/drain region (111a) of the first bottom transistor to a sidewall of the source/drain region (112a) of the second bottom transistor [0089].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Li, as taught by Yamagami. The ordinary artisan would have been motivated to modify Li in the above manner for purpose of enabling operation ([0001] of Yamagami).
Regarding Claim 2
FIG. 8 of Li discloses an inter-level source/drain via extending vertically from the first source/drain region of the first bottom transistor to a source/drain region of the first top transistor.
Regarding Claim 3
FIG. 8 of Li discloses one or more power rails (VSS) disposed at a level lower than the first and second bottom transistors.
Regarding Claim 8
FIG. 8 of Li discloses a longitudinal axis of the first gate structure (G4) is aligned with a longitudinal axis of the second gate structure (G5).
Regarding Claim 9
FIG. 6 of Li discloses an output node of the first and second bottom transistors is aligned with an output node of the first and second top transistors.
Regarding Claim 10
FIG. 10 of Li discloses a semiconductor device having a standard cell, comprising: a first bottom transistor (M14) disposed on a substrate (10) in a first row; a first top transistor (M12) disposed above the first bottom transistor in the first row, the first bottom transistor and the first top transistor sharing a first gate structure (G7); a second bottom transistor (M13) in a second row next to the first row; a second top transistor (M11) disposed above the second bottom transistor in the second row, the second bottom transistor and the second top transistor sharing a second gate structure (G6); and a first top-transistor-level metal line (V18) extending laterally from a first source/drain region of the first top transistor to a first source/drain region of the second top transistor.
Li is silent with respect to “the first top-transistor-level metal line has a top surface at a higher elevation than the first source/drain region of the first top transistor” and “the first top-transistor-level metal line has a bottommost position level with a bottommost position of the first source/drain region of the first top transistor”.
FIG. 5C of Hong discloses a similar semiconductor device, wherein the first top-transistor-level metal line (523) has a top surface at a higher elevation than the first source/drain region (513) of the first top transistor; and wherein the first top-transistor-level metal line has a bottommost position level with a bottommost position of the first source/drain region of the first top transistor.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Li, as taught by Hong. The ordinary artisan would have been motivated to modify Li in the above manner, because the claimed configuration was a matter of choice (evidenced by various embodiments of Hong).
Regarding Claim 17
FIG. 10 of Li discloses a method, comprising: forming a first bottom semiconductor layer (M14) and a second bottom semiconductor layer (M13) over a substrate (10), the first and second bottom semiconductor layers are arranged in adjacent rows; forming first bottom source/drain regions (M14S/M14D) on the first bottom semiconductor layer, and second bottom source/drain regions (M13S/M13D) on the second bottom semiconductor layer; forming a first top semiconductor layer (M12) above the first bottom semiconductor layer, and a second top semiconductor layer (M11) above the second bottom semiconductor layer; forming first top source/drain regions (M12S/M12D) on the first top semiconductor layer, and second top source/drain regions (M11S/M11D) on the second top semiconductor layer; forming an inter-level source/drain via between a first one of the first top source/drain regions and a first one of the first bottom source/drain regions; and forming a first gate structure (G7) wrapping around a channel region in the first bottom semiconductor layer and a channel region in the first top semiconductor layer, and forming a second gate structure (G6) wrapping around a channel region in the second bottom semiconductor layer and a channel region in the second top semiconductor layer; and forming a bottom-transistor-level metal line.
Li is silent with respect to “the inter-level source/drain via has opposite sidewalls respectively aligned with opposite sidewalls of the first one of the first top source/drain regions”.
FIG. 5A of Hong discloses a similar semiconductor device, wherein the first bottom-transistor-level metal line (522) has a top surface at a higher elevation than the first source/drain region (512) of the first bottom transistor; and wherein the first bottom-transistor-level metal line has a bottommost position level with a bottommost position of the first source/drain region of the first bottom transistor.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Li, as taught by Hong. The ordinary artisan would have been motivated to modify Li in the above manner, because the claimed configuration was a matter of choice (evidenced by various embodiments of Hong).
Claims 4-7 rejected under 35 U.S.C. 103 as being unpatentable over Li, Hong and Yamagami, in view of Masuoka (U.S. Patent Pub. No. 2016/0329348) of record.
Regarding Claim 4
Li as modified by Hong and Yamagami discloses Claim 3.
Li as modified by Hong and Yamagami is silent with respect to “the one or more power rails comprise a first power rail, a second power rail and a third power rail, wherein the first bottom transistor and the first top transistor in the first row is between the first and second power rails from a top view, and wherein the second bottom transistor and the second top transistor in the second row is between the second the third power rails from the top view”.
FIG. 3 of Masuoka discloses a similar semiconductor device, wherein the one or more power rails comprise a first power rail (VCC), a second power rail (VSS) and a third power rail (VCC), wherein the first bottom transistor and the first top transistor in the first row is between the first and second power rails from a top view, and wherein the second bottom transistor and the second top transistor in the second row is between the second the third power rails from the top view.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Li, as taught by Masuoka. The ordinary artisan would have been motivated to modify Li in the above manner for purpose of compact layout ([0012] of Masuoka).
Regarding Claim 5
FIG. 3 of Masuoka discloses the first and third power rails are VDD lines, and the second power rail is a Vss line.
Regarding Claim 6
FIG. 3 of Yamagami discloses a top-transistor-level metal line (160) extending laterally from a source/drain region of the second top transistor, wherein the top-transistor-level metal line electrically connects the Vss line (162).
Regarding Claim 7
Li as modified by Hong, Masuoka and Yamagami discloses a top-transistor-level metal line extending laterally from a source/drain region of the second top transistor to a position above the VDD line; and a via electrically connecting the VDD line and the top-transistor-level metal line.
Claims 1 and 22 rejected under 35 U.S.C. 103 as being unpatentable over Li, in view of Hong, in view of Gu (U.S. Patent Pub. No. 2013/0082235) of record.
Regarding Claim 1
FIG. 10 of Li discloses a semiconductor device having a standard cell, comprising: a first bottom transistor (M14) in a first row; a first top transistor (M12) disposed above the first bottom transistor in the first row, the first bottom transistor and the first top transistor sharing a first gate structure (G7); a second bottom transistor (M13) in a second row next to the first row; a second top transistor (M11) disposed above the second bottom transistor in the second row, the second bottom transistor and the second top transistor sharing a second gate structure (G6); and a first bottom-transistor-level metal line (Connecting M14S) extending laterally from a first source/drain region of the first bottom transistor to a source/drain region of the second bottom transistor.
Li is silent with respect to “the first bottom-transistor-level metal line has a top surface at a higher elevation than the first source/drain region of the first bottom transistor”; “the first bottom-transistor-level metal line has a bottommost position level with a bottommost position of the first source/drain region of the first bottom transistor” and “the first bottom-transistor-level metal line laterally extends from a sidewall of the first source/drain region of the first bottom transistor to a sidewall of the source/drain region of the second bottom transistor”.
FIG. 5A of Hong discloses a similar semiconductor device, wherein the first bottom-transistor-level metal line (522) has a top surface at a higher elevation than the first source/drain region (512) of the first bottom transistor; and wherein the first bottom-transistor-level metal line has a bottommost position level with a bottommost position of the first source/drain region of the first bottom transistor.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Li, as taught by Hong. The ordinary artisan would have been motivated to modify Li in the above manner, because the claimed configuration was a matter of choice (evidenced by various embodiments of Hong).
Li as modified by Hong is silent with respect to ““the first bottom-transistor-level metal line laterally extends from a sidewall of the first source/drain region of the first bottom transistor to a sidewall of the source/drain region of the second bottom transistor””.
FIG. 5 of Gu discloses a similar semiconductor device, wherein the first bottom-transistor-level metal line (522-526) laterally extends from a sidewall of the first source/drain region of the first bottom transistor to a sidewall of the source/drain region of the second bottom transistor.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Li, as taught by Gu. The ordinary artisan would have been motivated to modify Li in the above manner for purpose of forming a monolithic 3D IC ([0002] of Gu).
Regarding Claim 22
FIG. 5 of Gu discloses an inter-level via (546) having a bottom surface interfacing the first bottom-transistor-level metal line (526) and a top surface interfacing a source/drain region (528) of the first top transistor.
Claim 23 rejected under 35 U.S.C. 103 as being unpatentable over Li, Hong and Gu, in view of Herbert (U.S. Patent Pub. No. 2012/0178211) of record.
Regarding Claim 23
Li as modified by Hong and Gu discloses Claim 22.
Li as modified by Hong and Gu is silent with respect to “an interface formed by the inter-level via and the first bottom-transistor-level metal line is larger than an interface formed by the inter-level via and the source/drain region of the first top transistor”.
However, said configuration was a matter of choice. Furthermore, FIG. 10 of Herbert discloses a similar semiconductor device, wherein an interface formed by the inter-level via and the metal line is larger than an interface formed by the inter-level via and the source/drain region.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Li, as taught by Herbert. The ordinary artisan would have been motivated to modify Li in the above manner for purpose of reducing parasitic source inductance ([0040] of Herbert).
Pertinent Art
FIG. 15 of Herbert (U.S. Patent Pub. No. 2012/0178211) discloses the inter-level source/drain via has opposite sidewalls respectively aligned with opposite sidewalls of the first one of the first top source/drain regions. FIG. 1 of Horibe (U.S. Patent Pub. No. 2005/0212014) discloses the first bottom-transistor-level metal line (104) has a top surface at a higher elevation than the first source/drain region (103) of the first bottom transistor; and wherein the first bottom-transistor-level metal line has a bottommost position level with a bottommost position of the first source/drain region of the first bottom transistor. Takeno (JP 7160105) discloses a VDD line inlaid in the substrate. Pertinent art also includes US 20120313227, 20220123023 and 20230062140.
Response to Arguments
Applicant’s arguments with respect to Claim 1 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection. With respect to Claim 10, FIG. 5 of Hong discloses the first bottom-transistor-level metal line (522) has a top surface at a higher elevation than the first source/drain region (512) of the first bottom transistor; the first bottom-transistor-level metal line has a bottommost position level with a bottommost position of the first source/drain region of the first bottom transistor; and the first top-transistor-level metal line (523) has a top surface at a higher elevation than the first source/drain region (513) of the first top transistor; the first top-transistor-level metal line has a bottommost position level with a bottommost position of the first source/drain region of the first top transistor. In addition, mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See MPEP 2144.04. Applicant’s arguments with respect to Claim 17 have been considered but are they not persuasive, because the limitation “the inter-level source/drain via has opposite sidewalls respectively aligned with opposite sidewalls of the first one of the first top source/drain regions” in method claim 17 directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: (1) the process as claimed can be used to make another and materially different product or (2) the product as claimed can be made by another and materially different process (MPEP § 806.05(f)). In the instant case the method as claimed can be used to make another and materially different device, e.g., the device claimed does not require that the inter-level source/drain via has opposite sidewalls respectively aligned with opposite sidewalls of the first one of the first top source/drain regions. The method claimed does not require that the first bottom-transistor-level metal line has a top surface at a higher elevation than the first source/drain region of the first bottom transistor, and the first bottom-transistor-level metal line has a bottommost position level with a bottommost position of the first source/drain region of the first bottom transistor. Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, the limitation “the inter-level source/drain via has opposite sidewalls respectively aligned with opposite sidewalls of the first one of the first top source/drain regions” withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
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