Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment to claim 20 traverses the objection which is hereby withdrawn.
Response to Arguments
Applicant's arguments filed 10/29/2025 have been fully considered but they are not persuasive.
Applicant's amendment of claim 1 necessitated the new grounds of rejection. As such, Applicant’s arguments on pages 7-11 regarding the 102 rejections of claims 1-7 are moot.
On pages 14-15, Applicant alleges that the rejection of claims 8-9 are not proper. In particular, Applicant alleges that the spring connectors 18 are not coupled to the motherboard 10, therefore Duley does not disclose the limitation “a CMT connector operatively coupled to the motherboard” as recited in claim 8.
The Examiner respectfully disagrees with Applicant’s allegations and conclusion.
The Examiner agrees with Applicant that Duley’s spring connectors 18 are coupled to the component package 14B which is coupled to the motherboard 10. Therefore, the Examiner respectfully submits that Duley’s spring connectors 18 are operatively coupled to the motherboard 10. It is noted that claim 8 does not require that the CMT connector is directly coupled to the motherboard.
Because Duley’s spring connectors 18 are operatively coupled to the motherboard 10, the Examiner respectfully submits that claim 8 is properly rejected under 103 over Duley in view of Pardo.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999).
The term: “contact mount technology (CMT)” in each of independent claims 1, 8, and 15 is indefinite because the specification does not clearly redefine the term. It is noted that the specification at Abstract and [0006] discusses: “compression mount technology (CMT).”
In order to expedite prosecution, the claimed term “contact mount technology (CMT)” in each independent claim is construed as “compression mount technology (CMT).”
All dependent claims are rejected by virtue of their dependency from a rejected parent claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6 are rejected under 35 U.S.C. 103as being unpatentable over “Duley” (US 6,979,784) in view of Eskandar (US 2019/0206827).
Regarding claim 1, Duley discloses 1. An apparatus, comprising:
a board including voltage regulation circuitry providing a plurality of output voltages, the board further including a first array of compression mount technology (CMT) contact pads having a first pattern and disposed on a surface layer of the board and including wiring connecting CMT pads to the plurality of output voltages (Figs. 1-4, col. 4, lines 11-18, col. 5, lines 15-20, col. 6, lines 55-57; the power board 16 is a board including the voltage regulation module 28 providing a plurality of voltages through a first array of the spring connectors 18 and the respective connector for each of the respective conductive pads on the power board 16. Examiner’s note: see the 112 rejection above regarding the construction of this limitation.),
wherein the board is configured to be installed in a compute platform including a CMT connector coupled to a motherboard, the CMT connector having an array of spring-loaded contacts arranged in a second pattern matching the first pattern (Figs. 1-4, col. 1, lines 19-20, col. 4, lines 11-18, col. 5, lines 15-20, col. 6, lines 55-57; the power board 16 is installed in modern processor products including an array of the spring connectors 18 coupled to the component package 14B on the motherboard 10),
and wherein when the board is installed in the compute platform the CMT connector is disposed between the motherboard and the board (Figs. 1-4, col. 1, lines 19-20, col. 4, lines 11-18, col. 5, lines 15-20, col. 6, lines 55-57; the spring connectors 18 are disposed between the motherboard 10 and the power board 16).
Duley does not disclose the motherboard having a second array of CMT pads, and the spring-loaded contacts are in compression contact with respective CMT contact pads in the first and second arrays of CMT contact pads.
Eskandar discloses the motherboard having a second array of CMT pads, and the spring-loaded contacts are in compression contact with respective CMT contact pads in the first and second arrays of CMT contact pads (Fig. 1, [0032]; the motherboard 150 has an array of compressed contact pads 140).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Duley’s apparatus with Eskandar’s compression pads in order to advantageously provide access to semiconductor dies within an overmolded semiconductor package without requiring access to the solder balls and/or contact pads on the lower surface of the semiconductor package, as suggested by Eskandar at [0020].
Regarding claim 2, Duley in view of Eskandar discloses the claimed invention as applied to claim 1, above.
Duley discloses 2. The apparatus of claim 1, wherein the voltage regulation circuitry includes at least one voltage regulation module (VRM) (Figs. 1-4, col. 4, lines 11-18; the voltage regulation module 28).
Regarding claim 3, Duley in view of Eskandar discloses the claimed invention as applied to claim 1, above.
Duley discloses 3. The apparatus of claim 1, wherein at least a portion of the voltage regulation circuitry comprises electrical components mounted to the board on a side opposite the first array of CMT contact pads (Figs. 1-4, col. 4, lines 11-18; at least a portion of the voltage regulation module 28 comprises electrical components mounted to the power board 16 at the connectors 24 and 26, on a side opposite the array of spring connectors 18).
Regarding claim 4, Duley in view of Eskandar discloses the claimed invention as applied to claim 1, above.
Duley discloses 4. The apparatus of claim 1, wherein at least a portion of the voltage regulation circuitry comprises electrical components mounted to the board on the same side as the first array of CMT contact pads (Figs. 1-4, col. 4, lines 11-18; at least a portion of the voltage regulation module 28 comprises electrical components mounted to the power board 16 at the standoffs 32 at the same side as the array of spring connectors 18).
Regarding claim 5, Duley in view of Eskandar discloses the claimed invention as applied to claim 1, above.
Duley discloses 5. The apparatus of claim 1, wherein a first portion of the voltage regulation circuitry comprises electrical components mounted to the board on a first side and a second portion of the voltage regulation circuitry comprises electrical components mounted to the board on a second side (Figs. 1-4, col. 4, lines 11-18; at first portion of the voltage regulation module 28 comprises electrical components mounted to the power board 16 at the connectors 24 and 26 on a first side, and a second portion of the voltage regulation module 28 comprises electrical components mounted to the power board 16 at the standoffs 32 on a second side).
Regarding claim 6, Duley in view of Eskandar discloses the claimed invention as applied to claim 1, above.
Duley discloses 6. The apparatus of claim 1, wherein the voltage regulation circuitry comprises electrical components mounted to the board on the same side as the first array of CMT contact pads, further comprising a heat sink mounted on the opposite side of the board (Figs. 1-4, col. 4, lines 11-18; the voltage regulation module 28 comprises electrical components mounted to the power board 16 at the standoffs 32 on the same side as the array of spring connectors 18, and the heat sink 20 is mounted on the opposite side of the power board 16).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Duley in view of Eskandar and “Pardo” (US 5,959,370).
Regarding claim 7, Duley in view of Eskandar discloses the claimed invention as applied to claim 1 above.
Duley does not disclose the limitations of claim 7.
Pardo discloses 7. The apparatus of claim 1, wherein the plurality of output voltages including output voltages having different phases, and wherein the apparatus is configured to work with a plurality of different motherboards having different input voltage and phase requirements (Figs. 1-5, col. 5, lines 38-40, col 6, lines 1-5; computers and electronic devices may require different voltages and some even require three phase voltages, the output terminals 24, 25, 26 and 27 is electrically interconnected to regulator circuitry 34, 35, 36, 37, respectively, structured to drop the corresponding battery output voltages to the input voltages required by the computer motherboard).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Duley’s apparatus, as modified by Eskandar, with Pardo’s apparatus since newer computers, televisions and other electronic motherboard systems often require several different, voltages and currents to operate, as suggested by Pardo at col. 1, lines 19-23.
Claims 8-10, 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Duley in view of “Pardo” (US 5,959,370).
Regarding claim 8, Duley discloses 8. A compute platform, comprising: a power conversion module comprising a board having voltage regulation circuitry providing a plurality of output voltages (Figs. 1-4, col. 4, lines 11-18, col. 5, lines 15-20, col. 6, lines 55-57; the power board 16 is a board including the voltage regulation module 28 providing a plurality of voltages through an array of the spring connectors 18 and the respective connector for each of the respective conductive pads on the power board 16),
the board further including a first array of compression mount technology (CMT) contact pads having a first pattern and disposed on a surface layer of the board and including wiring connecting CMT pads to the plurality of output voltages (Figs. 1-4, col. 1, lines 19-20, col. 4, lines 11-18, col. 5, lines 15-20, col. 6, lines 55-57; the power board 16 is installed in modern processor products including an array of the spring connectors 18 and respective contact pads disposed on a surface layer of the power board 16 and including wiring connecting the pads to the output voltages. Examiner’s note: see the 112 rejection above regarding the construction of this limitation.);
a motherboard, including a plurality of components operatively coupled thereto including at least one processor (Figs. 1-4, col. 1, lines 19-20, col. 4, lines 11-18, col. 5, lines 15-20, col. 6, lines 55-57; the motherboard 10 includes a plurality of components including a processor);
and a CMT connector operatively coupled to the motherboard, having an array of spring-loaded contacts or pins arranged in a second pattern matching the first pattern, the CMT connector disposed between the motherboard and the board with the spring-loaded contacts or pins being in compression contact with respective CMT contact pads in the first array of CMT contact pads (Figs. 1-4, col. 1, lines 19-20, col. 4, lines 11-18, col. 5, lines 15-20, col. 6, lines 55-57; the array of the spring connectors 18 is coupled to the motherboard 10 arranged in a second pattern matching the first pattern, the array of the spring connectors 18 are disposed between the motherboard 10 and the power board 16 with the array of the spring connectors 18 being in compression contact with the respective first array of CMT contact pads).
Duley does not disclose output voltages having different phases.
Pardo discloses output voltages having different phases (Figs. 1-5, col. 5, lines 38-40, col 6, lines 1-5; computers and electronic devices may require different voltages and some even require three phase voltages, the output terminals 24, 25, 26 and 27 is electrically interconnected to regulator circuitry 34, 35, 36, 37, respectively, structured to drop the corresponding battery output voltages to the input voltages required by the computer motherboard).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Duley’s apparatus with Pardo’s apparatus since newer computers, televisions and other electronic motherboard systems often require several different, voltages and currents to operate, as suggested by Pardo at col. 1, lines 19-23.
Regarding claim 9, Duley in view of Pardo discloses the claimed invention as applied to claim 8, above.
Duley discloses 9. The compute platform of claim 8, further comprising a second array of CMT contact pads disposed on a surface layer of the motherboard, the second array of CMT contact pads arranged in a third pattern matching the first pattern, wherein at least a portion of the CMT contact pads in the second array of CMT contact pads are coupled to pins or contacts on the processor via wiring in the motherboard (Figs. 1-4, col. 1, lines 19-24, col. 4, lines 11-18, col. 5, lines 15-20, col. 6, lines 55-57; a second array of the spring connectors 18 are disposed on a surface layer of the motherboard 10, arranged in a third pattern matching the first pattern, a portion of the spring connectors 18 and the respective contact pads are coupled to contacts on the component 14, which is a processor via wiring in the motherboard 10).
Regarding claim 10, Duley in view of Pardo discloses the claimed invention as applied to claim 8, above.
Duley discloses 10. The compute platform of claim 8, wherein the spring-loaded contacts or pins include or are operatively coupled to conductive members extending downward below the CMT connector (Figs. 1-4, col. 1, lines 19-24, col. 4, lines 11-18, col. 5, lines 15-20, col. 6, lines 55-57; the spring connectors 18 a include or are operatively coupled to conductive members extending downward below the spring connectors 18),
and wherein the CMT connector is coupled to the motherboard via an array of solder balls that are formed around the conductive members (Figs. 1-4, col. 6, lines 55-62; the spring connectors 18 comprise a connector for the conductive pads on the power board 16 that extends to the component package 14B which may be electrically coupled by solder connections).
Regarding claim 12, Duley in view of Pardo discloses the claimed invention as applied to claim 8, above.
Duley discloses 12. The compute platform of claim 8, further comprising: a second power conversion module having voltage regulation circuitry providing a second plurality of output voltages, including a third array of CMT contact pads having a third pattern and disposed on a surface layer of the board and including wiring connecting CMT pads to the second plurality of output voltages (Figs. 6-7, col. 10, lines 42-54; the set of power planes for a four-layer embodiment of a multiple power conversion module having voltage regulation circuitry providing a plurality of output voltages, including a third array of contact pads including wiring connecting pads to the respective output voltages);
and a second CMT connector operatively coupled to the motherboard, having a second array of spring-loaded contacts or pins arranged in a fourth pattern matching the third pattern, the second CMT connector disposed between the motherboard and the board with the spring-loaded contacts or pins being in compression contact with respective CMT contact pads in the third array of CMT contact pads (Figs. 1-4, col. 1, lines 19-20, col. 4, lines 11-18, col. 5, lines 15-20, col. 6, lines 55-57; a second array of the spring connectors 18 are disposed between the motherboard 10 and the power board 16 with the spring connectors 118 being in compression contact with respective pads in the third array).
Duley does not disclose the second power conversion module comprising a second board.
It would have been obvious to one having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Duley’s set of power planes for a four-layer embodiment of a multiple power conversion module as separate first and second boards, since it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art. In re Dulberg, 289 F.2d 522, 523, 129 USPQ 348, 349 (CCPA 1961).
Regarding claim 14, Duley in view of Pardo discloses the claimed invention as applied to claim 8, above.
Duley discloses 14. The compute platform of claim 8, wherein the CMT connector is disposed toward an edge of the motherboard, and wherein the power conversion module includes voltage regulation circuitry that is disposed on the same side as the first array of CMT contact pads (Figs. 1-4, col. 1, lines 19-24, col. 4, lines 11-18, col. 5, lines 15-20, col. 6, lines 55-57; the spring connectors 18 are disposed toward an edge of the motherboard 10, and the voltage regulation module 28 circuitry is disposed on the same side as the first array of contact pads),
and wherein the voltage regulation circuitry includes one or more components that extend past a top surface plane of the motherboard (Figs. 1-4, col. 8, lines 5-7; the voltage regulation module 28 includes one or more components that extend past a top surface plane of the motherboard 10).
Claims 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Duley in view of Pardo and “Sato” (US 2011/0226462).
Regarding claim 11, Duley in view of Pardo discloses the claimed invention as applied to claim 8 above.
Duley discloses the at least one processor includes a System on a Chip (SoC) (Figs. 1-4, col.4, lines 19-24; the computer system includes a processor used as an example of the component 14).
Duley does not disclose the processor including a multi-core central processing unit (CPU) and an integrated graphics processing unit (GPU).
Sato discloses a processor including a multi-core central processing unit (CPU) and an integrated graphics processing unit (GPU) (Figs. 1-2, [0024]-[0026]; the computer includes a multi-core CPU, a GPU and a high speed memory).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Duley’s apparatus, as modified by Pardo, with Sato’s apparatus in order to obtain high reliability, high efficiency, and low power requirements, without also incurring an increase in PCB space and cost, as suggested by Sato at [0007].
Regarding claim 13, Duley in view of Pardo discloses the claimed invention as applied to claim 12 above.
Duley discloses the second power conversion module supplies power to components in the subsystem (Figs. 6-7, col. 10, lines 42-54; the set of power planes for a four-layer embodiment of a multiple power conversion module having voltage regulation circuitry providing a plurality of output voltages to components in the subsystem).
Duley does not disclose the compute platform includes a memory subsystem.
Sato discloses the compute platform includes a memory subsystem (Figs. 1-2, [0024]-[0026]; the computer includes a multi-core CPU, a GPU and a high speed memory).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Duley’s apparatus, as modified by Pardo, with Sato’s apparatus in order to obtain high reliability, high efficiency, and low power requirements, without also incurring an increase in PCB space and cost, as suggested by Sato at [0007].
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Duley in view of Eskandar, Pardo and “Sato” (US 2011/0226462).
Regarding claim 15, Duley discloses 15. A compute platform, comprising: a power conversion module comprising a board having voltage regulation circuitry providing a plurality of output voltages (Figs. 1-4, col. 4, lines 11-18, col. 5, lines 15-20, col. 6, lines 55-57; the power board 16 is a board including the voltage regulation module 28 providing a plurality of voltages through an array of the spring connectors 18 and the respective connector for each of the respective conductive pads on the power board 16),
the board further including a first array of compression mount technology (CMT) contact pads having a first pattern and disposed on a surface layer of the board and including wiring connecting CMT pads to the plurality of output voltages (Figs. 1-4, col. 1, lines 19-20, col. 4, lines 11-18, col. 5, lines 15-20, col. 6, lines 55-57; the power board 16 is installed in modern processor products including an array of the spring connectors 18 and respective contact pads disposed on a surface layer of the power board 16 and including wiring connecting the pads to the output voltages. Examiner’s note: see the 112 rejection above regarding the construction of this limitation.);
a motherboard, including a plurality of components operatively coupled thereto (Figs. 1-4, col. 1, lines 19-20, col. 4, lines 11-18, col. 5, lines 15-20, col. 6, lines 55-57; the motherboard 10 includes a plurality of components operatively coupled thereto),
a CMT connector operatively coupled to the motherboard, having an array of spring-loaded contacts or pins arranged in a third pattern matching the first pattern, the CMT connector disposed between the motherboard and the board (Figs. 1-4, col. 1, lines 19-20, col. 4, lines 11-18, col. 5, lines 15-20, col. 6, lines 55-57; the array of the spring connectors 18 is coupled to the motherboard 10 arranged in a third pattern matching the first pattern, the array of the spring connectors 18 are disposed between the motherboard 10 and the power board 16),
wherein at least of portion of the plurality of output voltages provided by the power conversion module are used as input voltages (Figs. 6-7, col. 10, lines 42-54; the set of power planes for a four-layer embodiment of a multiple power conversion module having voltage regulation circuitry providing a plurality of output voltages, including a third array of contact pads including wiring connecting pads to the respective output voltages).
Duley does not disclose output voltages having different phases and a central processing unit (CPU) and a graphics processing unit (GPU), the motherboard having a second array of CMT contact pads having a second pattern matching the first pattern, with the spring-loaded contacts or pins being in compression contact with respective CMT contact pads in the first array of CMT contact pads.
Pardo discloses output voltages having different phases (Figs. 1-5, col. 5, lines 38-40, col 6, lines 1-5; computers and electronic devices may require different voltages and some even require three phase voltages, the output terminals 24, 25, 26 and 27 is electrically interconnected to regulator circuitry 34, 35, 36, 37, respectively, structured to drop the corresponding battery output voltages to the input voltages required by the computer motherboard).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Duley’s apparatus with Pardo’s apparatus since newer computers, televisions and other electronic motherboard systems often require several different, voltages and currents to operate, as suggested by Pardo at col. 1, lines 19-23.
Sato discloses a central processing unit (CPU) and a graphics processing unit (GPU) (Figs. 1-2, [0024]-[0026]; the computer includes a multi-core CPU, a GPU and a high speed memory).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Duley’s apparatus, as modified by Pardo, with Sato’s apparatus in order to obtain high reliability, high efficiency, and low power requirements, without also incurring an increase in PCB space and cost, as suggested by Sato at [0007].
Eskandar discloses the motherboard having a second array of CMT contact pads having a second pattern matching the first pattern, with the spring-loaded contacts or pins being in compression contact with respective CMT contact pads in the first array of CMT contact pads (Fig. 1, [0032]; the motherboard 150 has an array of compressed contact pads 140).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Duley’s apparatus, as modified by Pardo and Saito, with Eskandar’s compression pads in order to advantageously provide access to semiconductor dies within an overmolded semiconductor package without requiring access to the solder balls and/or contact pads on the lower surface of the semiconductor package, as suggested by Eskandar at [0020].
Regarding claim 16, Duley in view of Eskandar, Pardo and Sato discloses the claimed invention as applied to claim 15 above.
Duley does not disclose the limitations of claim 16.
Pardo discloses plurality of output voltages includes output voltages at multiple phases (Figs. 1-5, col. 5, lines 38-40, col 6, lines 1-5; computers and electronic devices may require different voltages and some even require three phase voltages, the output terminals 24, 25, 26 and 27 is electrically interconnected to regulator circuitry 34, 35, 36, 37, respectively, structured to drop the corresponding battery output voltages to the input voltages required by the computer motherboard).
Sato discloses the CPU comprises a System on a Chip including a CPU core (Figs. 1-2, [0024]-[0026]; the computer includes a multi-core CPU, a GPU and a high speed memory).
Regarding claim 17, Duley in view of Eskandar, Pardo and Sato discloses the claimed invention as applied to claim 15 above.
Duley discloses 17. The compute platform of claim 15, further comprising: a second power conversion module having voltage regulation circuitry providing a second plurality of output voltages, the second board including a fourth array of CMT contact pads having a fourth pattern and disposed on a surface layer of the second board and including wiring connecting CMT pads to the second plurality of output voltages (Figs. 6-7, col. 10, lines 42-54; the set of power planes for a four-layer embodiment of a multiple power conversion module having voltage regulation circuitry providing a plurality of output voltages, including a fourth array of contact pads including wiring connecting pads to the respective output voltages);
and a second CMT connector operatively coupled to the motherboard, having a second array of spring-loaded contacts or pins arranged in a fifth pattern matching the fourth pattern, the second CMT connector disposed between the motherboard and the board with the spring-loaded contacts or pins being in compression contact with respective CMT contact pads in the fourth array of CMT contact pads (Figs. 1-4, col. 1, lines 19-20, col. 4, lines 11-18, col. 5, lines 15-20, col. 6, lines 55-57; a second array of the spring connectors 18 are disposed between the motherboard 10 and the power board 16 with the spring connectors 118 being in compression contact with respective pads in the fourth array).
Duley does not disclose the second power conversion module comprising a second board.
It would have been obvious to one having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Duley’s set of power planes for a four-layer embodiment of a multiple power conversion module as separate first and second boards, since it has been held that constructing a formerly integral structure in various elements involves only routine skill in the art. In re Dulberg, 289 F.2d 522, 523, 129 USPQ 348, 349 (CCPA 1961).
Regarding claim 18, Duley in view of Eskandar, Pardo and Sato discloses the claimed invention as applied to claim 17 above.
Duley discloses the CPU comprises a System on a Chip (SoC) (Figs. 1-4, col.4, lines 19-24; the computer system includes a processor used as an example of the component 14),
the second power conversion module provides input power (Figs. 6-7, col. 10, lines 42-54; the set of power planes for a four-layer embodiment of a multiple power conversion module having voltage regulation circuitry providing a plurality of output voltages, including a third array of contact pads including wiring connecting pads to the respective output voltages).
Duley does not disclose a memory controller that is coupled to one or more memory devices.
Sato discloses a memory controller that is coupled to one or more memory devices (Figs. 1-2, 7, [0024]-[0026], [0044]-[0047]; the CPU block includes a memory and interface to allow the memory to communicate with the rest of the VR and cooling control IC).
Regarding claim 19, Duley in view of Eskandar, Pardo and Sato discloses the claimed invention as applied to claim 18 above.
Duley discloses the second power conversion module further provides power to other platform components (Figs. 6-7, col. 10, lines 42-54; the set of power planes for a four-layer embodiment of a multiple power conversion module having voltage regulation circuitry providing a plurality of output voltages, including a third array of contact pads including wiring connecting pads to the respective output voltages).
Duley does not disclose using at least one of a 1.8 volt output voltage and a 3.3 volt output voltage.
Pardo discloses using at least one of a 1.8 volt output voltage and a 3.3 volt output voltage (co.. 2, lines 36-41; motherboards require 3.3 volts).
Regarding claim 20, Duley in view of Eskandar, Pardo and Sato discloses the claimed invention as applied to claim 15 above.
Duley discloses 20. The compute platform of claim 15, further comprising a power supply providing a plurality of output voltages and being operatively coupled to the motherboard, wherein the motherboard includes wiring mean for coupling the plurality of power supply output voltages to the motherboard (Figs. 1-4, col. 1, lines 19-20, col. 4, lines 11-18, col. 5, lines 15-20, col. 6, lines 55-57, col. 8, lines 14-15; the array of the spring connectors 18 is coupled to the motherboard 10, any power supply module may be used in place of the VRM 28).
Duley does not disclose coupling to CMT contact pads in the second array of CMT contact pads on the motherboard.
Eskandar discloses CMT contact pads in the second array of CMT contact pads on the motherboard (Fig. 1, [0032]; the motherboard 150 has an array of compressed contact pads 140).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANLEY TSO whose telephone number is (571)270-0723. The examiner can normally be reached Tu-Thurs 6am-6pm, alt M 6am-2pm.
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/STANLEY TSO/Primary Examiner, Art Unit 2847
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