DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-13, and 17-23 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (“Kwon” US 2019/0172767) and Matsushima et al. (“Matsushima” US 2001/0040288).
Regarding claim 1, Kwon discloses:
A semiconductor package (Figure 4A), comprising:
a substrate (204, para. [0026]) having a top surface and a bottom surface (shown in modified Figure 4A);
a semiconductor die (210, para. [0026]) mounted on the top surface of the substrate (shown in modified Figure 4A); and
a two-part lid (401, 402) mounted on a perimeter of the top surface of the substrate (shown in modified Figure 4A) and housing the semiconductor die (210), wherein the two-part lid (401, 402) comprises an annular lid base (401) and a cover plate (402) removably installed on the annular lid base (401, Figures 1A and 1B show that the lid is removably installed on the base),
wherein the cover plate (402) when engaged with the annular lid base (401) forms a sealed space (sealed area between cover plate and annular lid base, labeled in modified Figure 4A) between the top surface of the substrate (204), the annular lid base (401) and the cover plate (402), wherein the semiconductor die (210) is disposed in the sealed space (the semiconductor die 210 is disposed in, i.e. the disposition of the semiconductor die is inside the bounds of, the sealed space as shown in modified Figure 4A below, using the sealed space as a sort of boundary, or bounds, the semiconductor die is disposed in the boundary as set by the sealed space, thus is disposed in the sealed space).
Kwon does not disclose that the semiconductor die is directly under the cover plate.
However, Matsushima discloses in Figures 2 A and 2B a cover plate (1) that contacts a back side of the semiconductor die (5), the semiconductor die (5) being directly under the cover plate (1).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Matsushima into the teachings of Kwon to include the shape and disposition of the cover plate (1) of Matsushima. One would be motivated to make the combination because the shape and disposition of the cover plate as taught by Matsushima provides improved heat dissipation performance, specifically heat generated by the semiconductor die can be conducted away from the die and to the outside environment when the cover plate is in contact with and directly above the semiconductor chip as taught by Matsushima (Matsushima, para. [0056]).
Regarding claim 5, Kwon discloses:
The semiconductor package (Figure 4A) according to claim 1, wherein the two-part lid (401, 402) is a metal lid (para. [0025] discloses the metal materials of the ring 402, and para. [0020] discloses the rings can be made of the same material).
Regarding claim 6, Kwon discloses:
The semiconductor package (Figure 4A) according to claim 1, wherein the cover plate (402) is arranged in a movable relationship with the annular lid base (401) by using a sliding mechanism (para. [0030] discloses the slide-lock mechanism used).
Regarding claim 7, Kwon discloses:
The semiconductor package(Figure 4A) according to claim 6, wherein the sliding mechanism (para. [0030]) is structured between the annular lid base (401) and the cover plate (402) such that the cover plate (402) is movable relative to the annular lid base (401, para. [0030] describes this sliding mechanism where 402 is slid into place, i.e. moving relative to the base 401).
Regarding claim 8, Kwon discloses:
The semiconductor package (Figure 4A) according to claim 1, wherein the annular lid base (401) comprises vertical inner walls spaced apart from the semiconductor die (210, shown in modified Figure 4A) and vertical outer walls opposite to the vertical inner walls (shown in modified Figure 4A).
Regarding claim 9, Kwon discloses:
The semiconductor package (Figure 4A) according to claim 8, wherein two parallel sliding grooves (406, para. [0030], bottom view of Figure 4B shows parallel arrangement of grooves) are provided on the vertical outer walls (shown in modified Figure 4A), wherein the two parallel sliding grooves (406) and mating tongues of the cover plate (tongue of 402, shown in modified Figure 4A) are structured to cooperate in a manner that permits the cover plate (402) to slide along the two parallel sliding grooves (406) relative to the annular lid base (401, Figure 4A shows this arrangement and para. [0030] discloses this cooperating manner).
Regarding claim 10, Kwon discloses:
The semiconductor package (Figure 4A) according to claim 9, wherein the cover plate (402) is moved to a position along a single sliding direction (sliding direction shown in Figure 1B, which is a single clockwise direction) by sliding along the two parallel sliding grooves (406) until an integral stopping member (catches 405, para. [0030]) of the cover plate (402) is in direct contact with the annular lid base (401, direct contact shown in Figure 4A).
Regarding claim 11, Kwon discloses:
The semiconductor package (Figure 4A) according to claim 9, wherein the annular lid base (401) and the cover plate (402) are constructed of stainless steel, aluminum, copper, platinum, nickel or an alloy thereof (para. [0031] discloses 401 is made of a magnetic material, and nickel is a magnetic material, and para. [0020] discloses rings are made of the same material).
Regarding claim 12, Kwon discloses:
An electronic device (Figure 4A), comprising:
a base (para. [0030] discloses coupling the substrate 204 to a printed circuit board or other device, which is interpreted as a base); and
a semiconductor package (Figure 4A), mounted on the base (para. [0030]), wherein the semiconductor package (Figure 4A) further comprises:
a substrate (204, para. [0026]) having a top surface and a bottom surface (shown in modified Figure 4A);
a semiconductor die (210, para. [0026]) mounted on the top surface of the substrate (shown in modified Figure 4A); and
a two-part lid (401, 402) mounted on a perimeter of the top surface of the substrate (shown in modified Figure 4A) and housing the semiconductor die (210), wherein the two-part lid (401, 402) comprises an annular lid base (401) and a cover plate (402) removably installed on the annular lid base (401, Figures 1A and 1B show that the lid is removably installed on the base),
wherein the cover plate (402) when engaged with the annular lid base (401) forms a sealed space (labeled in modified Figure 4A) between the top surface of the substrate (204), the annular lid base (401) and the cover plate (402), wherein the semiconductor die (210) is disposed in the sealed space (the semiconductor die 210 is disposed in, i.e. the disposition of the semiconductor die is inside the bounds of, the sealed space as shown in modified Figure 4A below, using the sealed space as a sort of boundary, or bounds, the semiconductor die is disposed in the boundary as set by the sealed space, thus is disposed in the sealed space).
Kwon does not disclose that the semiconductor die is directly under the cover plate.
However, Matsushima discloses in Figures 2 A and 2B a cover plate (1) that contacts a back side of the semiconductor die (5), the semiconductor die (5) being directly under the cover plate (1).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Matsushima into the teachings of Kwon to include the shape and disposition of the cover plate (1) of Matsushima. One would be motivated to make the combination because the shape and disposition of the cover plate as taught by Matsushima provides improved heat dissipation performance, specifically heat generated by the semiconductor die can be conducted away from the die and to the outside environment when the cover plate is in contact with and directly above the semiconductor chip as taught by Matsushima (Matsushima, para. [0056]).
Regarding claim 13, Kwon discloses:
The semiconductor package according to claim 12, wherein the base comprises an application board or a system board (para. [0030] discloses the substrate 204 is coupled to a printed circuit board, which is interpreted as a system board).
Regarding claim 17, Kwon discloses:
The semiconductor package (Figure 4A) according to claim 12, wherein the two-part lid (401, 402) is a metal lid (para. [0025] discloses the metal materials of the ring 402, and para. [0020] discloses the rings can be made of the same material).
Regarding claim 18, Kwon discloses:
The semiconductor package according to claim 12, wherein the cover plate (402) is arranged in a movable relationship with the annular lid base (401) by using a sliding mechanism (para. [0030] discloses the slide-lock mechanism used).
Regarding claim 19, Kwon discloses:
The semiconductor package according to claim 18, wherein the sliding mechanism (para. [0030]) is structured between the annular lid base (401) and the cover plate (402) such that the cover plate (402) is movable relative to the annular lid base (401, para. [0030] describes this sliding mechanism where 402 is slid into place, i.e. moving relative to the base 401).
Regarding claim 20, Kwon discloses:
The semiconductor package (Figure 4A) according to claim 12, wherein the annular lid base (401) comprises vertical inner walls spaced apart from the semiconductor die (210, shown in modified Figure 4A) and vertical outer walls opposite to the vertical inner walls (shown in modified Figure 4A).
Regarding claim 21, Kwon discloses:
The semiconductor package (Figure 4A) according to claim 20, wherein two parallel sliding grooves (406, para. [0030], parallel arrangement shown in Figure 4B) are provided on the vertical outer walls (shown in modified Figure 4A), wherein the two parallel sliding grooves (406) and mating tongues of the cover plate (tongue of 402, shown in modified Figure 4A) are structured to cooperate in a manner that permits the cover plate (402) to slide along the two parallel sliding grooves (406) relative to the annular lid base (401, Figure 4A shows this arrangement and para. [0030] discloses this cooperating manner).
Regarding claim 22, Kwon discloses:
The semiconductor package (Figure 4A) according to claim 21, wherein the cover plate (402) is moved to a position along a single sliding direction (sliding direction shown in Figure 1B, clockwise direction which is in a single, i.e. one, direction) by sliding along the two parallel sliding grooves (406) until an integral stopping member (catches 405, para. [0030]) of the cover plate (402) is in direct contact with the annular lid base (401, direct contact shown in Figure 4A).
Regarding claim 23, Kwon discloses:
The semiconductor package (Figure 4A) according to claim 21, wherein the annular lid base (401) and the cover plate (402) are constructed of stainless steel, aluminum, copper, platinum, nickel or an alloy thereof (para. [0031] discloses 401 is made of a magnetic material, and nickel is a magnetic material, and para. [0020] discloses rings are made of the same material).
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Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (“Kwon” US 2019/0172767) as applied to claim 1 above, and further in view of Chang et al. (“Chang” US 2021/0074603).
Regarding claim 2, Kwon does not explicitly disclose:
[The semiconductor package according to claim 1], wherein the semiconductor die is mounted on the top surface of the substrate in a flip-chip manner.
Chang discloses:
[The semiconductor package according to claim 1], wherein the semiconductor die (21, para. [0033]) is mounted on the top surface of the substrate (20, shown in Figure 2A)in a flip-chip manner (para. [0033]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Chang into the teachings of Kwon to include wherein the semiconductor die is mounted on the top surface of the substrate in a flip-chip manner for the purpose of increasing routing density and meet miniaturization requirements (Chang, para. [0003]).
Regarding claim 3, Kwon does not disclose:
[The semiconductor package according to claim 2], wherein the semiconductor die has an active surface that faces downwardly to the substrate and connecting elements disposed on the active surface, wherein the connecting elements are bonded to respective pads disposed on the top surface of the substrate.
Chang discloses:
[The semiconductor package according to claim 2], wherein the semiconductor die (21) has an active surface (21a) that faces downwardly to the substrate (shown in Figure 2A) and connecting elements (210, para. [0033]) disposed on the active surface (21a, shown in Figure 2A), wherein the connecting elements (210) are bonded to respective pads (211, para. [0033]) disposed on the top surface of the substrate (20, shown in Figure 2A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Chang into the teachings of Kwon to include wherein the semiconductor die has an active surface that faces downwardly to the substrate and connecting elements disposed on the active surface, wherein the connecting elements are bonded to respective pads disposed on the top surface of the substrate for the purpose of bonding the die to the substrate in a flip-chip manner that increases routing density and meets miniaturization requirements (Chang, para. [0003]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (“Kwon” US 2019/0172767) and Chang et al. (“Chang” US 2021/0074603) as applied to claim 2 above, and further in view of Wu et al. (“Wu” US 2011/0186960).
Regarding claim 4, Kwon does not disclose:
[The semiconductor package according to claim 2], wherein a gap between the semiconductor die and the substrate is filled with an underfill layer.
Wu discloses:
[The semiconductor package according to claim 2], wherein a gap between the semiconductor die (108, para. [0048]) and the substrate (102, gap is area occupied by underfill 118) is filled with an underfill layer (118, para. [0048]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Wu into the teachings of Kwon to include wherein a gap between the semiconductor die and the substrate is filled with an underfill layer for the purpose of providing electrical insulation (Wu, para. [0048]).
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (“Kwon” US 2019/0172767) as applied to claim 12 above, and further in view of Chang et al. (“Chang” US 2021/0074603).
Regarding claim 14, Kwon does not explicitly disclose:
[The semiconductor package according to claim 12], wherein the semiconductor die is mounted on the top surface of the substrate in a flip-chip manner.
Chang discloses:
[The semiconductor package according to claim 12], wherein the semiconductor die (21, para. [0033]) is mounted on the top surface of the substrate (20, shown in Figure 2A)in a flip-chip manner (para. [0033]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Chang into the teachings of Kwon to include wherein the semiconductor die is mounted on the top surface of the substrate in a flip-chip manner for the purpose of increasing routing density and meet miniaturization requirements (Chang, para. [0003]).
Regarding claim 15, Kwon does not disclose:
[The semiconductor package according to claim 14], wherein the semiconductor die has an active surface that faces downwardly to the substrate and connecting elements disposed on the active surface, wherein the connecting elements are bonded to respective pads disposed on the top surface of the substrate.
Chang discloses:
[The semiconductor package according to claim 14], wherein the semiconductor die (21) has an active surface (21a) that faces downwardly to the substrate (shown in Figure 2A) and connecting elements (210, para. [0033]) disposed on the active surface (21a, shown in Figure 2A), wherein the connecting elements (210) are bonded to respective pads (211, para. [0033]) disposed on the top surface of the substrate (20, shown in Figure 2A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Chang into the teachings of Kwon to include wherein the semiconductor die has an active surface that faces downwardly to the substrate and connecting elements disposed on the active surface, wherein the connecting elements are bonded to respective pads disposed on the top surface of the substrate for the purpose of bonding the die to the substrate in a flip-chip manner that increases routing density and meets miniaturization requirements (Chang, para. [0003]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (“Kwon” US 2019/0172767) and Chang et al. (“Chang” US 2021/0074603) as applied to claim 14 above, and further in view of Wu et al. (“Wu” US 2011/0186960).
Regarding claim 16, Kwon does not disclose:
[The semiconductor package according to claim 14], wherein a gap between the semiconductor die and the substrate is filled with an underfill layer.
Wu discloses:
[The semiconductor package according to claim 14], wherein a gap between the semiconductor die (108, para. [0048]) and the substrate (102, gap is area occupied by underfill 118) is filled with an underfill layer (118, para. [0048]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Wu into the teachings of Kwon to include wherein a gap between the semiconductor die and the substrate is filled with an underfill layer for the purpose of providing electrical insulation (Wu, para. [0048]).
Response to Arguments
Applicant’s arguments with respect to claims 1 and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899