DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3.13.2026 has been entered.
Election/Restrictions
Claims 3, 6-7 and 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention/species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1.10.2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Ode et al. (of record, US 20110244628 A1) in view of Shibita et al. (of record, US 20110074048 A1).
Regarding claim 1, Ode discloses a semiconductor package (Fig. 12) comprising:
an interposer (21, “wiring substrate 21”);
a first stacked chip (all of 22, “semiconductor chips 22”) comprising a first semiconductor chip (22c, “lowermost semiconductor chip 22c”) disposed on the interposer and one or more second semiconductor chips (the rest of 22) disposed on the first semiconductor chip;
a first molding layer (24, “under-fill material 24”) surrounding the first stacked chip (Figs. 11 and 12); and
a second molding layer (27, “sealing material 27”) surrounding the first molding layer and comprising a single, uniform, non-conductive material (Fig. 12),
wherein an upper(most) surface of the first stacked chip (uppermost of 22a) is coplanar with an upper surface (not the uppermost; the surface abutting 22a) of the second molding layer (27) and an upper(most) surface of the first molding layer (24, Fig. 12).
Ode fails to disclose wherein the second molding layer extends from an uppermost surface of the interposer into a trench of the interposer, wherein the trench is located entirely outside an outermost horizontal edge of the first stacked chip, wherein a depth of the trench is less than a height of the interposer, wherein the trench is defined in the interposer, and wherein a horizontal width from an inner surface of the second molding layer to an outer surface of the second molding layer is equal to a horizontal width of the trench.
Shibita discloses (Figs. 2-3) the second molding layer (3) extends from an uppermost surface of the interposer (1+11a; MPEP 2111) into a trench (16) of the interposer, wherein the trench is located entirely outside an outermost horizontal edge of the first stacked chip (2), wherein a depth of the trench is less than a height of the interposer (Figs. 2-3), wherein the trench (16) is defined in the interposer (1+11a), and wherein a horizontal width (W1, inside the trench) from an inner (not innermost, IS) surface of the second molding layer (3) to an outer(most) surface (OS) of the second molding layer (3) is equal to a horizontal width (W2) of the trench (16, Fig. 3).
PNG
media_image1.png
443
585
media_image1.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to incorporate the teachings of Shibita into the device of Ode and arrive at the claimed invention so as to prevent moisture from entering a region near a semiconductor chip (Shibita, [0031]).
Regarding claim 2, Ode/Shibita discloses the semiconductor package of claim 1, wherein the second molding layer (27) covers at least a side surface of the first molding layer (24, Fig. 12).
Regarding claim 5, Ode/Shibita discloses the semiconductor package of claim 1, wherein the first molding layer (24) and the second molding layer (27) are in direct contact with each other (Fig. 12).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Ode et al. (of record, US 20110244628 A1) in view of Shibita et al. (of record, US 20110074048 A1) as applied to claim 2 above, and further in view of Chen et al. (of record, US 9859245 B1).
Regarding claim 4, Ode/Shibita fails to disclose the semiconductor package of claim 2, wherein the second molding layer does not cover the upper surface of the first molding layer.
Chen discloses wherein the second molding layer (240, “molding layer 240”) does not cover the upper surface of the first molding layer (140/180, “molding layer 180” and “molding layer 140”, Fig. 1J).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to incorporate the teachings of Chen into the device of Ode/Shibita and arrive at the claimed invention so as to provide a co-planar surface onto which a heatsink can be mounted onto a chip surface to aid in dissipation of heat.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Ode et al. (of record, US 20110244628 A1) in view of Shibita et al. (of record, US 20110074048 A1) as applied to claim 1 above, and further in view of Kang et al. (of record, US 20140084456 A1).
Regarding claim 8, Ode/Shibita fails to disclose the semiconductor package of claim 1, wherein each that each of outer surfaces of the second molding layer is not aligned with a side surface of the interposer in a vertical direction and is located inside the interposer in a horizontal direction.
Kang discloses (Fig. 20) wherein each of outer surfaces of the second molding layer (substrate mold layer 600; para. [0273]) is not aligned with a side surface of the interposer (printed circuit board 500; para. [0263]) in a vertical direction and is located inside the interposer (500) in a horizontal direction.
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to incorporate the teachings of Kang into the device of Ode/Shibita to include each of outer surfaces of the second molding layer is not aligned with a side surface of the interposer in a vertical direction and is located inside the interposer in a horizontal direction for the purpose of allowing for multiple devices to be formed simultaneously and subsequently trimmed/sawed without risking damage to the molding layers or other components as would be understood by one skilled in the art and/or so as to minimize the amount of molding material needed to protect encapsulated devices.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Ode et al. (of record, US 20110244628 A1) in view of Shibita et al. (of record, US 20110074048 A1) as applied to claim 1 above, and further in view of Kim et al. (of record, US 20180006006 A1).
Regarding claim 9, Ode/Shibita fails to disclose the semiconductor package of claim 1, wherein the first semiconductor chip is a buffer chip configured to control the one or more second semiconductor chips, and wherein the one or more second semiconductor chips are memory cell chips.
Kim discloses (Fig. 20) wherein the first semiconductor chip (C1) is a buffer chip configured to control the one of more second semiconductor chips (C2-C5), and wherein the one or more second semiconductor chips (C2-C5) are memory cell chips ( [0038] explains first chip can be a logic chip and second chip can be a memory chip, see also [0049]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to incorporate the teachings of Kim into the device of Ode/Shibita so as to provide for a packaged device with high degree of functionality with a reduced size (Kim, [0003]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Ode et al. (of record, US 20110244628 A1) in view of Shibita et al. (of record, US 20110074048 A1) as applied to claim 1 above, and further in view of Kang et al. (of record, US 20140084456 A1) and Chang et al (of record, US 20190273075 A1).
Regarding claim 10, Ode/Shibita fails to disclose the semiconductor package of claim 1, wherein the first molding layer and the second molding layer are of different materials.
Kang discloses (Fig. 20) wherein the first molding layer (160) and the second molding layer (600) are of different materials (different physical property described in [0274]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to incorporate the teachings of Kang into the device Ode/Shibita to include the first molding layer and the second molding layer are of different materials for the purpose of allowing the different molding layers to have different physical properties such as different thermal expansion coefficients, viscosities, or gap-fill properties to allow for better device stability and structural integrity as evidenced by Chang ( [0052]).
Claims 1-2 and 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over of Chen et al. (of record, US 9859245 B1) in view of Shibita et al. (of record, US 20110074048 A1).
Regarding claim 1, Chen discloses (Fig. 1J) a semiconductor package comprising:
an interposer (230);
a first stacked chip comprising a first semiconductor chip (172) disposed on the interposer and one or more second semiconductor chips (132) disposed on the first semiconductor chip;
a first molding layer (140/180 or 140/180/150; MPEP 2111) surrounding the first stacked chip; and
a second molding layer (240) surrounding the first molding layer and comprising a single, uniform, non-conductive material (“The molding layer 240 includes a polymer material or another suitable insulating material”),
wherein an upper(most) surface (131) of the first stacked chip is coplanar with an upper(most) surface of the second molding layer (240) and an upper(most) surface of the first molding layer (Fig. 1J).
Chen fails to disclose wherein the second molding layer extends from an uppermost surface of the interposer into a trench of the interposer, wherein the trench is located entirely outside an outermost horizontal edge of the first stacked chip, wherein a depth of the trench is less than a height of the interposer, wherein the trench is defined in the interposer, and wherein a horizontal width from an inner surface of the second molding layer to an outer surface of the second molding layer is equal to a horizontal width of the trench.
Shibita discloses (Figs. 2-3) the second molding layer (3) extends from an uppermost surface of the interposer (1+11a; MPEP 2111) into a trench (16) of the interposer, wherein the trench is located entirely outside an outermost horizontal edge of the first stacked chip (2), wherein a depth of the trench is less than a height of the interposer (Figs. 2-3), wherein the trench (16) is defined in the interposer (1+11a), and wherein a horizontal width (W1, inside the trench) from an inner (not innermost, IS) surface of the second molding layer (3) to an outer(most) surface (OS) of the second molding layer (3) is equal to a horizontal width (W2) of the trench (16, Fig. 3).
PNG
media_image1.png
443
585
media_image1.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to incorporate the teachings of Shibita into the device of Chen and arrive at the claimed invention so as to prevent moisture from entering a region near a semiconductor chip (Shibita, [0031]).
Regarding claim 2, Chen/Shibita discloses the semiconductor package of claim 1, wherein the second molding layer (240) covers at least a side surface of the first molding layer (Fig. 1J).
Regarding claim 4, Chen/Shibita discloses wherein the second molding layer (240) does not cover the upper(most) surface of the first molding layer (Fig. 1J).
Regarding claim 5, Chen/Shibita discloses the semiconductor package of claim 1, wherein the first molding layer and the second molding layer (240) are in direct contact with each other (Fig. 1J).
Response to Arguments
Applicant's arguments filed 3.13.2026 have been fully considered but they are not persuasive.
The applicant alleges: “First, the resin mold body 3 is not a "second molding" that "extends from an uppermost surface of an interposer into a trench." Rather, the resin mold body 3 is the only molding disclosed by Shibita. As is clear from FIG. 2 of Shibita, there is no molding other than mold body 3 that covers the semiconductor element 2. The Office's alleged combination requires taking the protruding portion of the single molding in Shibita and incorporating it specifically into the alleged "second molding" (sealing material 27) of Ode”.
In response to applicant:
The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Furthermore, in Ode at Fig. 12, the second molding layer (27) is the outermost molding layer and is in contact with the interposer (21) while in Shibita at Figs. 2-3, the outermost of the only molding layer (3) extends into the trench and is in contact with the interposer. The examiner’s rationale to combine the references and include a trench in relation to the second molding layer is maintained given the placement of the molding layers and the moisture prevention of [0031] of Shibita.
The applicant alleges: “However, neither reference provides any teaching, suggestion, or rationale for: relocating the protrusion from a single-molding structure into a dual-molding structure, much less selecting the outer molding (rather than the inner molding) as the location for that protrusion. In Shibita, the resin mold body 3 that includes the protruding portion is the only molding surrounding the chip. Once Ode's dual-molding structure is introduced, a design choice must be made as to which molding would carry the protrusion. Shibita offers no teaching that would inform that choice. The Office's rejection therefore depends on hindsight reconstruction”.
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Finally, in Ode at Fig. 12, the second molding layer (27) is the outermost molding layer and is in contact with the interposer (21) while in Shibita at Figs. 2-3, the outermost of the only molding layer (3) extends into the trench and is in contact with the interposer. The examiner’s rationale to combine the references and include a trench in relation to the second molding layer is maintained given the placement of the molding layers and the moisture prevention of [0031] of Shibita.
The applicant alleges: “Indeed, if one were to incorporate a structural feature from a single-molding encapsulant into a two-layer system, the most natural analog to Shibi ta' s molding would be Ode's alleged "first molding" (under-fill material 24) because both mold resin body 3 and under-fill material 24 are structurally positioned closer to a semiconductor chip”.
This is not persuasive since in Ode at Fig. 12, the second molding layer (27) is the outermost molding layer and is in contact with the interposer (21) while in Shibita at Figs. 2-3, the outermost of the only molding layer (3) extends into the trench and is in contact with the interposer. The examiner’s rationale to combine the references and include a trench in relation to the second molding layer is maintained given the placement of the molding layers and the moisture prevention of [0031] of Shibita.
The applicant alleges: “Second, Shibita fails to disclose the resin mold body 3 extends into a trench "wherein the trench is defined in the interposer." Shibita discloses a recessed portion in a solder resist layer, not within the body of the interposer. Shibita' s recessed portion 16 is limited to the upper layer--the solder resist layer--and does not penetrate into or modify the interposer body itself. As explained in Shibita, the recessed portion 16 is formed in a solder resist 11a. See [0026]” and “However, the solder resist 11a is formed on the substrate 1, which includes a base material 5 and a plurality of wires 6. There is no disclosure or suggestion in Shibita that the recessed portion extends into the substrate 1”.
This is not found persuasive because per MPEP 2111, the interposer of Shibita is 11a+1 since the claim would not preclude said interpretation and because 11a directly abuts 1.
The applicant alleges: “Third, Shibita fails to disclose "wherein a horizontal width from an inner surface of the second molding layer to an outer surface of the second molding layer is equal to a horizontal width of the trench." Shibita's FIG. 2 discloses a horizonal width the resin mold body that is substantially wider than Shibita' s alleged trench”.
This is not persuasive because Shibita discloses wherein a horizontal width (W1, inside the trench) from an inner (not innermost, IS) surface of the second molding layer (3) to an outer(most) surface (OS) of the second molding layer (3) is equal to a horizontal width (W2) of the trench (16, Fig. 3).
PNG
media_image1.png
443
585
media_image1.png
Greyscale
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Regarding claim 1, Lee et al. (US 20150311182 A1) discloses a semiconductor package (Fig. 9) comprising:
an interposer (200);
a first stacked chip (210) comprising a first semiconductor chip (210) disposed on the interposer
a first molding layer (240) surrounding the first stacked chip; and
a second molding layer (260a) surrounding the first molding layer and comprising a single, uniform, non-conductive material,
wherein the second molding layer (260a) extends from an uppermost surface of the interposer into a trench (250, Fig. 7) of the interposer, wherein the trench is located entirely outside an outermost horizontal edge of the first stacked chip (210), wherein a depth of the trench is less than a height of the interposer (Fig. 9),
wherein the trench is defined in the interposer (Fig. 9),
wherein a horizontal width from an inner surface (towards 210) of the second molding layer to an outer surface (away from 210) of the second molding layer is equal to a horizontal width of the trench (250), and
wherein an upper surface of the first stacked chip (210) is coplanar with an upper surface of the second molding layer (260a) and an upper surface of the first molding layer (240).
PNG
media_image2.png
380
730
media_image2.png
Greyscale
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Andres Munoz/ Primary Examiner, Art Unit 2818