DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6.2.2026 is being considered by the examiner.
Election/Restrictions
Claims 3, 6-7 and 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention/species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1.10.2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (of record, US 20150311182 A1) in view of Ode et al. (of record, US 20110244628 A1).
Regarding claim 1, Lee discloses a semiconductor package (Fig. 9) comprising:
an interposer (200);
a first stacked chip (210) comprising a first semiconductor chip (210) disposed on the interposer
a first molding layer (240) surrounding the first stacked chip; and
a second molding layer (260a) surrounding the first molding layer and comprising a single, uniform, non-conductive material,
wherein the second molding layer (260a) extends from an uppermost surface of the interposer into a trench (250, Fig. 7) of the interposer, wherein the trench is located entirely outside an outermost horizontal edge of the first stacked chip (210), wherein a depth of the trench is less than a height of the interposer (Fig. 9),
wherein the trench is defined in the interposer (Fig. 9),
wherein a horizontal width from an innermost surface (towards 210) of the second molding layer to an outermost surface (away from 210) of the second molding layer is equal to a horizontal width of the trench (250), and
wherein an upper(most) surface of the first stacked chip (210) is coplanar with an upper(most) surface of the second molding layer (260a) and an upper(most) surface of the first molding layer (240).
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Lee fails to disclose a first stacked chip comprising a first semiconductor chip disposed on the interposer and one or more second semiconductor chips disposed on the first semiconductor chip.
Ode discloses (Fig. 12) a first stacked chip (all of 22, “semiconductor chips 22”) comprising a first semiconductor chip (22c, “lowermost semiconductor chip 22c”) disposed on the interposer (21) and one or more second semiconductor chips (the rest of 22) disposed on the first semiconductor chip.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the stacked chip of Ode in Lee and arrive at the claimed invention so as to provide stacked chips with multiple functions, increase the packaging density of semiconductor devices and/or minimize footprint of highly integrated packages.
Regarding claim 2, Lee/Ode discloses the semiconductor package of claim 1, wherein the second molding layer (260a) covers at least a side surface of the first molding layer (240, Fig. 9).
Regarding claim 4, Lee/Ode discloses the semiconductor package of claim 2, wherein the second molding layer (260a) does not cover the upper(most) surface of the first molding layer (240, Fig. 9).
Regarding claim 5, Lee/Ode discloses the semiconductor package of claim 1, wherein the first molding layer (240) and the second molding layer (260a) are in direct contact with each other (Fig. 9).
Regarding claim 8, Lee/Ode discloses the semiconductor package of claim 1, wherein each of outer surfaces of the second molding layer (260a) is not aligned with a side surface of the interposer (200) in a vertical direction and is located inside the interposer in a horizontal direction (Fig. 9).
Regarding claim 10, Lee/Ode discloses the semiconductor package of claim 1, wherein the first molding layer (240, “epoxy molding compound (EMC)”) and the second molding layer (260a, “BCB and polyimide or a mixture of one or more polymer materials”) are of different materials.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (of record, US 20150311182 A1) in view of Ode et al. (of record, US 20110244628 A1) as applied to claim 1 above, and further in view of Kim et al. (of record, US 20180006006 A1).
Regarding claim 9, Lee/Ode fails to disclose the semiconductor package of claim 1, wherein the first semiconductor chip is a buffer chip configured to control the one or more second semiconductor chips, and wherein the one or more second semiconductor chips are memory cell chips.
Kim discloses (Fig. 20) wherein the first semiconductor chip (C1) is a buffer chip configured to control the one of more second semiconductor chips (C2-C5), and wherein the one or more second semiconductor chips (C2-C5) are memory cell chips ( [0038] explains first chip can be a logic chip and second chip can be a memory chip, see also [0049]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to incorporate the teachings of Kim into the device of Lee/Ode so as to provide for a packaged device with high degree of functionality with a reduced size (Kim, [0003]).
Response to Arguments
Applicant's arguments filed 6.22.2026 have been fully considered but they are not persuasive.
The applicant alleges the prior art of record fails to disclose or suggest “wherein a horizontal width from an innermost surface of the second molding layer to an outermost surface of the second molding layer is equal to a horizontal width of the trench” as recited in claim 1.
Lee et al. (of record, US 20150311182 A1) discloses (Fig. 9) wherein a horizontal width from an innermost surface (towards 210) of the second molding layer (260a) to an outermost surface (away from 210) of the second molding layer is equal to a horizontal width of the trench (250).
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Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andres Munoz/ Primary Examiner, Art Unit 2818
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