DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9.8.2026 has been entered.
Election/Restrictions
Claims 3, 6-7 and 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention/species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1.10.2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2, 4-5 and 8-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, “wherein the second molding layer comprises an upper portion disposed above the uppermost surface of the interposer and horizontally outward of an outermost side surface of the first molding layer relative to the first stacked chip, and a lower portion extending from the upper portion into and filling the trench” (emphasis added) is indefinite because it is unclear if “and horizontally outward of an outermost side surface of the first molding layer relative to the first stacked chip” is a modifier of the “second molding layer” or of the “upper portion” and this obscures the scope of the claim. It is treated as modifying either of the options listed above.
None of dependent claims 2, 4-5 and 8-10 address this deficiency and are rejected along with base claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2 and 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 20210143126 A1) in view of Shibita et al. (of record, US 20110074048 A1).
Regarding claim 1, Choi discloses a semiconductor package (Fig. 1) comprising:
an interposer (200);
a first stacked chip (310/320) comprising a first semiconductor chip (310) disposed on the interposer and one or more second semiconductor chips (320) disposed on the first semiconductor chip;
a first molding layer (330) surrounding the first stacked chip; and
a second molding layer (600) surrounding the first molding layer and comprising a single, uniform, non-conductive material ([0051]),
wherein an upper(most) surface of the first stacked chip is coplanar with an upper(most) surface of the second molding layer and an upper(most) surface of the first molding layer (said surfaces are coplanar due to the presence of element 700 in Fig. 1), and
wherein the second molding layer (600) comprises an upper portion disposed above the uppermost surface of the interposer (200) and horizontally outward of an outermost side surface of the first molding layer relative to the first stacked chip (Fig. 1),
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Choi fails to disclose wherein the second molding layer extends from an uppermost surface of the interposer into a trench of the interposer, wherein the trench is located entirely outside an outermost horizontal edge of the first stacked chip, wherein a depth of the trench is less than a height of the interposer, wherein the trench is defined in the interposer, and wherein the second molding layer comprises a lower portion extending from the upper portion into and filling the trench.
Shibita discloses (Figs. 2-3) wherein the second molding layer (3) extends from an uppermost surface of the interposer (1+11a) into a trench (16) of the interposer, wherein the trench is located entirely outside an outermost horizontal edge of the and wherein the second molding layer (3) comprises a lower portion extending from the upper portion into and filling the trench (Figs. 2-3).
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Note: under the proposed modification, the second molding layer 600 of Choi (Fig. 1) would extend into a trench (such as 16 of Shibita in Fig. 3) partially extending through Choi’s interposer 200; this proposed modification meets the claim.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the trench and related arrangement of Shibita in Choi and arrive at the claimed invention so as to prevent moisture penetration (Shibita, [0031]).
Regarding claim 2, Choi/Shibita discloses the semiconductor package of claim 1, wherein the second molding layer (600) covers at least a side surface of the first molding layer (330, Fig. 1).
Regarding claim 4, Choi/Shibita discloses the semiconductor package of claim 2, wherein the second molding layer (600) does not cover the upper(most) surface of the first molding layer (330, Fig. 1).
Regarding claim 5, Choi/Shibita discloses the semiconductor package of claim 1, wherein the first molding layer (330) and the second molding layer (600) are in direct contact with each other (Fig. 1).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 20210143126 A1) in view of Shibita et al. (of record, US 20110074048 A1) as applied to claim 1 above, and further in view of Kang et al. (of record, US 20140084456 A1).
Regarding claim 8, Choi/Shibita fails to disclose the semiconductor package of claim 1, wherein each of outer surfaces of the second molding layer is not aligned with a side surface of the interposer in a vertical direction and is located inside the interposer in a horizontal direction.
Kang discloses (Fig. 20) wherein each of outer surfaces of the second molding layer (substrate mold layer 600; para. [0273]) is not aligned with a side surface of the interposer (printed circuit board 500; para. [0263]) in a vertical direction and is located inside the interposer (500) in a horizontal direction.
It would have been obvious to one of ordinary skill in the art, before the effective filling date, to incorporate the teachings of Kang into the device of Choi/Shibita to include each of outer surfaces of the second molding layer is not aligned with a side surface of the interposer in a vertical direction and is located inside the interposer in a horizontal direction for the purpose of allowing for multiple devices to be formed simultaneously and subsequently trimmed/sawed without risking damage to the molding layers or other components as would be understood by one skilled in the art and/or so as to minimize the amount of molding material needed to protect encapsulated devices.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 20210143126 A1) in view of Shibita et al. (of record, US 20110074048 A1) as applied to claim 1 above, and further in view of Kim et al. (of record, US 20180006006 A1).
Regarding claim 9, Choi/Shibita fails to disclose the semiconductor package of claim 1, wherein the first semiconductor chip is a buffer chip configured to control the one or more second semiconductor chips, and wherein the one or more second semiconductor chips are memory cell chips.
Kim discloses (Fig. 20) wherein the first semiconductor chip (C1) is a buffer chip configured to control the one of more second semiconductor chips (C2-C5), and wherein the one or more second semiconductor chips (C2-C5) are memory cell chips ( [0038] explains first chip can be a logic chip and second chip can be a memory chip, see also [0049]).
It would have been obvious to one of ordinary skill in the art, before the effective filling date, to incorporate the teachings of Kim into the device of Choi/Shibita so as to provide for a packaged device with high degree of functionality with a reduced size (Kim, [0003]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 20210143126 A1) in view of Shibita et al. (of record, US 20110074048 A1) as applied to claim 1 above, and further in view of Kang et al. (of record, US 20140084456 A1) and Chang et al (of record, US 20190273075 A1).
Regarding claim 10, Choi/Shibita fails to disclose the semiconductor package of claim 1, wherein the first molding layer and the second molding layer are of different materials.
Kang discloses (Fig. 20) wherein the first molding layer (160) and the second molding layer (600) are of different materials (different physical property described in [0274]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to incorporate the teachings of Kang into the device Choi/Shibita to include the first molding layer and the second molding layer are of different materials for the purpose of allowing the different molding layers to have different physical properties such as different thermal expansion coefficients, viscosities, or gap-fill properties to allow for better device stability and structural integrity as evidenced by Chang ( [0052]).
Claims 1, 2 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Ode et al. (of record, US 20110244628 A1) in view of Shibita et al. (of record, US 20110074048 A1).
Regarding claim 1, Ode discloses a semiconductor package (Fig. 12) comprising:
an interposer (21);
a first stacked chip (22c/22/22a) comprising a first semiconductor chip (22c) disposed on the interposer and one or more second semiconductor chips (the rest of 22) disposed on the first semiconductor chip;
a first molding layer (24) surrounding the first stacked chip; and
a second molding layer (27) surrounding the first molding layer and comprising a single, uniform, non-conductive material (Fig. 12),
wherein an upper(most) surface (at 22a) of the first stacked chip is coplanar with an upper (not uppermost) surface (abutting 22a) of the second molding layer (27) and an upper(most) surface of the first molding layer (24), and
wherein the second molding layer (27) comprises an upper portion disposed above the uppermost surface of the interposer (21) and horizontally outward of an outermost side surface of the first molding layer (24) relative to the first stacked chip (Fig. 12),
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Ode fails to disclose wherein the second molding layer extends from an uppermost surface of the interposer into a trench of the interposer, wherein the trench is located entirely outside an outermost horizontal edge of the first stacked chip, wherein a depth of the trench is less than a height of the interposer, wherein the trench is defined in the interposer, and wherein the second molding layer comprises a lower portion extending from the upper portion into and filling the trench.
Shibita discloses (Figs. 2-3) wherein the second molding layer (3) extends from an uppermost surface of the interposer (1+11a) into a trench (16) of the interposer, wherein the trench is located entirely outside an outermost horizontal edge of the height of the interposer (1+11a), wherein the trench (16) is defined in the interposer (1+11a), and wherein the second molding layer (3) comprises a lower portion extending from the upper portion into and filling the trench (Figs. 2-3).
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Note: under the proposed modification, the second molding layer 27 of Ode (Fig. 12) would extend into a trench (such as 16 of Shibita in Fig. 3) partially extending through Ode’s interposer 21; this proposed modification meets the claim.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the trench and related arrangement of Shibita in Ode and arrive at the claimed invention so as to prevent moisture penetration (Shibita, [0031]).
Regarding claim 2, Ode/Shibita discloses the semiconductor package of claim 1, wherein the second molding layer (27) covers at least a side surface of the first molding layer (24, Fig. 12).
Regarding claim 5, Ode/Shibita discloses the semiconductor package of claim 1, wherein the first molding layer (24) and the second molding layer (27) are in direct contact with each other (Fig. 12).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Ode et al. (of record, US 20110244628 A1) in view of Shibita et al. (of record, US 20110074048 A1) as applied to claim 1 above, and further in view of Kang et al. (of record, US 20140084456 A1).
Regarding claim 8, Ode/Shibita fails to disclose the semiconductor package of claim 1, wherein each of outer surfaces of the second molding layer is not aligned with a side surface of the interposer in a vertical direction and is located inside the interposer in a horizontal direction.
Kang discloses (Fig. 20) wherein each of outer surfaces of the second molding layer (substrate mold layer 600; para. [0273]) is not aligned with a side surface of the interposer (printed circuit board 500; para. [0263]) in a vertical direction and is located inside the interposer (500) in a horizontal direction.
It would have been obvious to one of ordinary skill in the art, before the effective filling date, to incorporate the teachings of Kang into the device of Ode/Shibita to include each of outer surfaces of the second molding layer is not aligned with a side surface of the interposer in a vertical direction and is located inside the interposer in a horizontal direction for the purpose of allowing for multiple devices to be formed simultaneously and subsequently trimmed/sawed without risking damage to the molding layers or other components as would be understood by one skilled in the art and/or so as to minimize the amount of molding material needed to protect encapsulated devices.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Ode et al. (of record, US 20110244628 A1) in view of Shibita et al. (of record, US 20110074048 A1) as applied to claim 1 above, and further in view of Kim et al. (of record, US 20180006006 A1).
Regarding claim 9, Ode/Shibita fails to disclose the semiconductor package of claim 1, wherein the first semiconductor chip is a buffer chip configured to control the one or more second semiconductor chips, and wherein the one or more second semiconductor chips are memory cell chips.
Kim discloses (Fig. 20) wherein the first semiconductor chip (C1) is a buffer chip configured to control the one of more second semiconductor chips (C2-C5), and wherein the one or more second semiconductor chips (C2-C5) are memory cell chips ( [0038] explains first chip can be a logic chip and second chip can be a memory chip, see also [0049]).
It would have been obvious to one of ordinary skill in the art, before the effective filling date, to incorporate the teachings of Kim into the device of Odei/Shibita so as to provide for a packaged device with high degree of functionality with a reduced size (Kim, [0003]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Ode et al. (of record, US 20110244628 A1) in view of Shibita et al. (of record, US 20110074048 A1) as applied to claim 1 above, and further in view of Kang et al. (of record, US 20140084456 A1) and Chang et al (of record, US 20190273075 A1).
Regarding claim 10, Ode/Shibita fails to disclose the semiconductor package of claim 1, wherein the first molding layer and the second molding layer are of different materials.
Kang discloses (Fig. 20) wherein the first molding layer (160) and the second molding layer (600) are of different materials (different physical property described in [0274]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to incorporate the teachings of Kang into the device Ode/Shibita to include the first molding layer and the second molding layer are of different materials for the purpose of allowing the different molding layers to have different physical properties such as different thermal expansion coefficients, viscosities, or gap-fill properties to allow for better device stability and structural integrity as evidenced by Chang ( [0052]).
Response to Arguments
Applicant’s arguments with respect to the pending claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andres Munoz/ Primary Examiner, Art Unit 2818
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