DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/17/26 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Amano et al. (US PGPub 2010/0093154, hereinafter referred to as “Amano”, IDS reference) in view of Watanabe et al. (US PGPub 2010/0099240, hereinafter referred to as “Watanabe”).
Amano discloses the semiconductor device substantially as claimed. See figures 1-5 and corresponding text, where Amano teaches, in claim 1, a dicing die attach film, comprising: a dicing film (10); and
a die attach film (3) laminated on the dicing film, wherein the die attach film has in contact with the dicing film, (figure 1; [0045]) and wherein a value of ratio of Ra1 to an arithmetic average roughness Ra2 at a surface that is of the die attach film and is opposite to the surface in contact with the dicing film is from 1.05 to 28.00. ([0045-0047])
Amano fails to show, in claim 1, an arithmetic average roughness Ra1 of from 0.05 to 2.50 µm at a surface in contact with the dicing film; wherein a value of ratio of Ra1 to an arithmetic average roughness Ra2 at a surface; and wherein the arithmetic average roughness Ra2 is 0.03 µm or more and 2.00 µm or less.
Amano teaches, in claim 1, that by adjusting the arithmetic mean roughness of the of the pressure-sensitive layer (2) or the die bond layers (3) the adhesion and peeling of the semiconductor chip from a pickup step is controlled ([0045-0046]).
Watanabe teaches, in claim 1, and adhesive film with a surface roughness of 0.15 μm that is determined by a shape measuring system (figures 1a and 1b; [0159-0167]). In addition, Watanabe provides the advantages of using a non-pressure sensitive adhesive film such as an acrylic, has excellent removability [0190]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed, to incorporate an arithmetic average roughness Ra1 of from 0.05 to 2.50 µm at a surface in contact with the dicing film; wherein a value of ratio of Ra1 to an arithmetic average roughness Ra2 at a surface; and wherein the arithmetic average roughness Ra2 is 0.03 µm or more and 2.00 µm or less, in the device of Amano, according to the teachings of both Amano and Watanabe, with the motivation of controlling the adhesion and peeling of the semiconductor chip from a pickup step that has excellent removability. Regarding a variable which achieves a recognized result, before the determination of the optimum or workable ranges of said variable might be characterized as routine experimentation, because "obvious to try" is not a valid rationale for an obviousness finding. In KSR International Co. v. Teleflex Inc., 550 U.S. 398 (2007),
Amano in view of Watanabe shows, in claim 2, wherein the die attach film comprises: an epoxy resin (A), an epoxy resin curing agent (B), a polymer component (C), and an inorganic filler (D), and wherein the die attach film is thermally cured to give a cured body having a thermal conductivity of 1.0 W/m.Math.K or more.([0074], [0084-0096])
Amano in view of Watanabe shows, in claim 3, wherein when the die attach film is heated at a temperature elevation rate of 5° C./min from 25° C., a melt viscosity at 120° C. is in a range of 500 to 10,000 Pa.Math.s. ([0101)
Amano in view of Watanabe shows, in claim 4, wherein the dicing film is energy ray-curable. ([0073])
Amano in view of Watanabe shows, in claim 5, comprising leveling a surface of the die attach film by using a pressure roll to create a surface state satisfying Ra1 and Ra2. ([0105])
Amano in view of Watanabe shows, in claim 6, a semiconductor package, comprising:
a semiconductor chip and a circuit board which are bonded to each other with a thermally cured product of a bonding agent; ([0109-0110])
and/or semiconductor chips which are bonded to each other with a thermally cured product of a bonding agent, wherein the bonding agent is derived from the die attach film of the dicing die attach film.
Amano in view of Watanabe shows, in claim 7, a method of producing a semiconductor package, comprising the steps of: ([0103-0114])
a first step of thermocompression bonding the dicing die attach film to a back surface of a semiconductor wafer where at least one semiconductor circuit is formed on a surface so that the die attach film is in contact with the back surface of the semiconductor wafer;
a second step of integrally dicing the semiconductor wafer and the die attach film to obtain a semiconductor chip with a bonding agent layer on the dicing film, the semiconductor chip with a bonding agent layer including a piece of the die attach film and a semiconductor chip;
a third step of removing the semiconductor chip with a bonding agent layer from the dicing film and thermocompression bonding the semiconductor chip with a bonding agent layer and a circuit board via the bonding agent layer; and
a fourth step of thermally curing the bonding agent layer.
Response to Arguments
Applicant's arguments filed 2/17/26 have been fully considered but they are not persuasive. In the Remarks applicant raises the clear issue as to whether Amano alone or in combination with Watanabe suggests wherein the arithmetic average roughness Ra2 is 0.03 µm or more and 2.00 µm or less.
The Examiner views that Amano in view of Watanabe does suggest the above claimed limitation and/or suggestions. Specifically, Amano and Watanabe suggest that by adjusting the arithmetic mean roughness of the of the pressure-sensitive layer or the die bond layers adhesion and removability can be achieved. Therefore, the he arithmetic mean roughness between the die attach film and the dicing film are obvious variants to the functionality of the adhesion and removal process of the semiconductor chip during a pickup process, thus would result in routine experimentation.
Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 March 7, 2026