DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This final office action is responsive to the amendments filed on 01/12/2026.
Claims 1-23 are pending.
Response to Amendment
Applicant has amended independent claims 1, 12, 20 and dependent claims 2, 4-6, 8, 11, 13-15, 17, 23 to include new/old limitations in a form not previously presented necessitating new search and considerations.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-23 are rejected under 35 U.S.C. 112 (b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or joint inventor regards as the invention.
The following claim language is not clearly understood:
Claim 1 recites “data size that would be consumed by including the transaction in the transmission”. It is unclear if the data size is consumed is referring to the amount of data being used or size of data is being transferred or actual data being transferred or size of bandwidth is being consumed. It is also unclear if the quantity of data is consumed by the transaction or transmission or both (i.e. consuming data is referring to what).
Claim 1 recites “a corresponding quantity” without clearly reciting quantity of what e.g. number of transaction, amount of transferred data, or both.
Claim 1 recites “transaction type as a function of their respective data sizes”. It is unclear data size is referring to data size in the request, data size of the response or both for a given transaction.
Claims 12 and 20 recite elements of claim 1 and have similar deficiency as claim 1. Therefore, they are rejected for the same rational. Remaining dependent claims 2-11, 13-19 and 21-23 are also rejected due to their dependency on the rejected independent claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12, 14-21, 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mace et al. (US 2012/0011291 A1, hereafter Mace) in view of Krueger (US 2018/0203723 A1, hereafter Krueger), and further in view of Dodson et al. (US 9,684,461 B1, hereafter Dodson)
Mace and Kruger were cited in the last office action.
As per claim 1, Mace teaches the invention substantially as claimed including a method comprising:
identifying respective transaction types of a plurality of transactions issued, for transmission in a time slot ([0140] transaction requests of different types, identifier identifying the type of issued transaction request [0005] fixed slots to each of master devices [0006] weighted round robin scheme, one master device receives more time slots than another master device) and over one or more buses by one or more processing resources of a plurality of processing resources sharing the one or more buses ([0089] fig. 1 master devices 4 slave devices 6 bus system 8 interconnects 10; routing transaction requests between master devices and slave devices [0090]);
determining, for each transaction of the plurality of transactions, a corresponding quantity based at least on a corresponding transaction type of the respective transaction types ([0140] transaction requests, different type identifiers, different bandwidth requirements of these types of transactions requests; different type of transaction requests, type, transaction, request which does not require much bus bandwidth, request requires a higher rate of bandwidth [0011] rate, transaction requests, issued from the master device) and a data size that would be consumed by including the transaction in the transmission ([0012] number of outstanding transaction requests, i.e. number of transaction requests that have been issued to the bus system and are awaiting servicing by the slave device, measure of the bus bandwidth occupied i.e. amount of data being transferred [0013] number of outstanding transaction N.x [0017] outstanding transaction requests, time averaged over an average cycle), the corresponding quantity varying amongst a set of the plurality of transactions of the respective transaction types as a function of their respective data sizes ([0140] transaction requests, different type identifiers, different bandwidth requirements of these types of transactions requests; different type of transaction requests, type, transaction, request which does not require much bus bandwidth, request requires a higher rate of bandwidth [0012] number of outstanding transaction requests, i.e. number of transaction requests that have been issued to the bus system and are awaiting servicing by the slave device, measure of the bus bandwidth occupied i.e. amount of data being transferred);
incrementing, by the corresponding quantity of each of the plurality of transactions, a counter that represents a total volume of data transfer of the transmission that is consumed by the plurality of transactions ([0011] amount of bus or slave device bandwidth, occupied, transaction request, rate at which transaction requests are issued [0012] number of outstanding transaction requests, i.e. number of transaction requests that have been issued to the bus system and are awaiting servicing by the slave device, measure of the bus bandwidth occupied i.e. amount of data being transferred [0019] accumulator, increment the accumulation value, amount, proportional, number of outstanding transaction requests greater than N [0021] modifies, accumulation value, per processing cycle [0140] transaction requests, different type identifiers, different bandwidth requirements of these types of transactions requests; different type of transaction requests, type, transaction, request which does not require much bus bandwidth, request requires a higher rate of bandwidth) and that aggregates the corresponding quantity of at least two of the plurality of transactions that correspond to different transaction types of the respective transaction types ([0140] transaction requests, different type identifiers, different bandwidth requirements of these types of transactions requests; different type of transaction requests, type, transaction, request which does not require much bus bandwidth, request requires a higher rate of bandwidth [0035] transaction request, read, write); and
filtering one or more transactions of the plurality of transactions with respect to the transmission ([0008] selectively issue, transaction requests to, bus system [0009] [0010] issue circuit, issue transaction request to bus system, transaction outstanding value [0013] [0014] [0031] [0034] [0036] read/write transaction requests, arbiter, current number of outstanding transaction request being equal to N-1 to select one of pending read transaction and write transaction to issue, selection criteria to select one of the pending read and write transaction requests, selection criterion could be favor write over read, at random, round robin) based at least on comparing the counter to a threshold data transfer allocated to the time slot ([0019] bus, processing cycles, accumulator, issue control, control the transaction interface, issue, an additional request; when said current number of outstanding transaction request is fewer than N; or current number of outstanding transaction request is N and accumulation value is decremented beyond a predetermined threshold value / equal to predetermined threshold value).
Mace doesn’t specifically teach, the corresponding quantity varying amongst a set of the plurality of transactions that have a same transaction type of the respective transaction types as a function of their respective data sizes; filtering based on threshold volume of data transfer.
Kreuger, however, teaches counter that represents a total volume of data transfer of the transmission that is consumed by the plurality of transaction ([0184] usage against a limit can be determined, counter, count usage of a resource limited by said limit, counter resets every predetermined period of time [0188] counter, keeps track, counter, transaction forward, incremented, received response, counter, decremented [0189] counter associated with a period of time; counter and limit could be directed towards data transferred over a period of time [0029] resources for handling transactions, interconnects, amount of bandwidth available for handling memory transaction);
filtering based on threshold volume of data transfer ([0029] resources for handling transactions, interconnects i.e. bus, amount of bandwidth available for handling memory transaction [0177] limit, bandwidth limit, memory system component, bandwidth, expressed as an amount of data transferred in, out or in and out of the at least one memory system component over a period of time [0178] current bandwidth usage of said memory system components, exceeds said maximum bandwidth [0184] usage against a limit can be determined, counter, count usage of a resource limited by said limit [0189] counter associated with a period of time; counter and limit could be directed towards data transferred over a period of time [0186] fig. 16 current bandwidth> maximum bandwidth-y 362, set preference =3 364 [0033] [0188] limit met or exceeded, transaction will not be forwarded [0192] fig. 20 384 386).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to combine the teachings of Mace with the teachings of Krueger of using counter to determine resource usage against a limit for a period of time e.g. counter limit counter and limit could be directed towards data transferred over a period of time and not forwarding transaction if the limit is met to improve efficiency and allow a counter that represents a total volume of data transfer of the transmission that is consumed by the plurality of transaction, and filtering based on threshold volume of data transfer to the method of Mace as in the instant invention.
The combination would have been obvious because using counter for the bus bandwidth usage and identifying and controlling progression of transaction with usage exceeding maximum limit as taught by Krueger to the amount of bus bandwidth usage taught by Mace to yield predictable result and improved efficiency.
Mace and Kruger doesn’t specifically teach quantity varying amongst a set of the plurality of transactions that have a same transaction type of the respective transaction types as a function of their respective data sizes.
Dodson, however, teaches quantity varying amongst a set of the plurality of transactions that have a same transaction type of the respective transaction types as a function of their respective data sizes (fig. 6 selected data size 612 col 6 lines 5-40 read queue, read requests, selected data size 612 variable settings 614 and reduced data setting 616; amount of data fetched for each read request is selected data size e.g. core 1 - 16X while core 2 is 32X i.e. same type of read transaction with different amount of data size ).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention was made to combine the teachings of Mace and Kruger with the teachings of Dodson of read queue comprising read transaction with different amount of data fetched corresponding to the selected data size to improve resource utilization efficiency and allow quantity varying amongst a set of the plurality of transactions that have a same transaction type of the respective transaction types as a function of their respective data sizes to the method of Mace and Kruger as in the instant invention.
The combination would have been because applying a variable data size for same type of transaction to fetch different amount of data as taught by Dodson to the method of Mace and Kruger to yield expected result and improved resource utilization efficiency.
As per claim 2, Mace teaches wherein the plurality of transactions are upstream transactions ([0035] write transaction i.e. upstream), and the volume of data transfer corresponds to a downstream data volume caused by including the plurality of transactions in the transmission ([0004] slave device, performs requested service and send a response to the master device i.e. downstream [0091] slave, bandwidth, available for use by respective master device, divided evenly, may require more bandwidth [0011] amount of bus or slave device bandwidth, occupied, transaction request, rate at which transaction requests are issued [0012] number of outstanding transaction requests, i.e. number of transaction requests that have been issued to the bus system and are awaiting servicing by the slave device, measure of the bus bandwidth occupied i.e. amount of data being transferred).
Krueger teaches remaining claim elements of total volume of data transferred ([0184] counter, count usage of a resource limited by said limit [0189] counter associated with a period of time; counter and limit could be directed towards data transferred over a period of time [0188] downstream).
As per claim 3, Mace teaches wherein the time slot is of a plurality of sequential time slots each corresponding to respective sequential processing cycles ([0019] bus system, clocked, processing cycles [0020] number of processing cycles, [0029] following processing cycles i.e. sequential).
Krueger teaches remaining claim elements of resetting the counter for the one or more processing resources based at least on detecting an end to the time slot and a beginning of a subsequent tile slot in the plurality of sequential time slots ([0184] usage against a limit can be determined, counter, count usage of a resource limited by said limit, counter resets every predetermined period of time).
As per claim 4, Krueger teaches wherein the counter is a first counter corresponding to a first volume of downstream data allocated to the one or more processing resources for the time slot ([0184] counter, count usage of a resource limited by said limit, counter resets every predetermined period of time [0188] counter, keep track of number of outstanding transactions, downstream [0189] counter associated with a period of time; counter and limit could be directed towards data transferred over a period of time), and the method further includes updating a second counter corresponding to a second volume of upstream data allocated to the one or more processing resources for the time slot based at least on the respective transaction type ([0184] counter, count usage of a resource limited by said limit, counter resets every predetermined period of time [0188] counter, keep track of number of outstanding transactions, response received, counter is decremented i.e. upstream can be separately tracked [0189] counter associated with a period of time; counter and limit could be directed towards data transferred over a period of time [0165] upstream response).
As per claim 5, Mace teaches wherein the transaction is an upstream transaction ([0035] write transaction requests i.e. upstream), the data size corresponds to bandwidth downstream to the one or more processing resources ([0035] read transaction i.e. downstream transaction [0011] amount of bus bandwidth occupied by transaction requests from a particular master device, dependent upon the rate at which transaction requests are issued), and the filtering includes:
permitting at least one transaction to be transmitted over the one or more buses based at least on the at least one transaction corresponding to an upstream write operation ([0019] bus, processing cycles, accumulator, issue control, control the transaction interface, issue, an additional request; when said current number of outstanding transaction request is fewer than N; or current number of outstanding transaction request is N and accumulation value is decremented beyond a predetermined threshold value / equal to predetermined threshold value [0034] transaction requests, plurality of target outstanding transaction, types of transaction requests, control, interface, issue the transaction requests, time averaged number of outstanding transaction requests, type of transaction request, target outstanding transaction value for the type, different type identifiers, control issuing of the transaction request, target outstanding request, type identified by the type identifier [0035] transaction request, write transaction requests, manage, write transaction request, separately, separate target outstanding transaction value [0036] issue control, arbiter, select, pending read/write transaction, issue to the bus system).
As per claim 6, Mace teaches receiving the data generated from the transaction ([0138] response to a transaction request, data required); and
determine the corresponding transaction type (([0034] transaction request, types).
Kruger teaches remaining claim elements of receiving the decoded packet data generated from one or more packets representing the transaction ([0037] fetch instruction, decoding the fetched instructions, queuing instructions );
analyzing the decoded packet data ([0186] next transaction, analyzed).
As per claim 7, Mace teaches wherein the one or more processing resources connect to a bus interface corresponding to the one or more buses ([0097] fig. 4 master devices M0, M1, transaction I/F0, I/F1 transaction interface 18 receives a transaction request from the master device and selectively issues the transaction request to the bus system 8, from where the transaction request can be forwarded to a further interconnect 10 or to a slave device 6 coupled to the interconnect 10), and the total volume of data transfer allocated to the one or more processing resources for the plurality of ([0011] amount of bus bandwidth, transaction request, rate of transaction being issues to the bus system [0096] allocate fractional amount of bus bandwidth, master device, allocated amount of bandwidth, number of outstanding transaction, master device, maintain an integer number, fractional number N.x [0104] total amount, length of time transaction was pending).
Kruger teaches remaining claim elements of counter corresponds to total volume of data transfer allocated to the one or more processing resources ([0188] counter, keep track of number of outstanding transactions, downstream [0189] counter associated with a period of time; counter and limit could be directed towards data transferred over a period of time )
Dodson, however, teaches send and receive lines (col 4 lines 11-20 memory interface bus, multiple parallel lines, to communicate).
As per claim 8, Krueger teaches the time slot and reset of the counter to zero ([0184] counter, counter resets every predetermined period of time [0188] counter, keeps track, counter, transaction forward, incremented, received response, counter, decremented [0189] counter associated with a period of time; counter and limit could be directed towards data transferred over a period of time [0158] new window starts, bandwidth, zero).
Dodson teaches remaining claim elements of wherein the time slot corresponds to a plurality of cycles (col 17 60-67 number of clock cycles, during a time window).
As per claim 9, Mace teaches wherein the one or more buses correspond to a memory interface that is shared amongst the plurality of processing resources (fig. 1 master devices 4-0, 4-1 interconnect 10-0 10-1 bus system 8).
As per claim 10, Mace teaches wherein the one or more processing resources are of one or more graphics processing units (GPUs) ([0140] master device, graphics processor) and the one or more buses connect the one or more GPUs to one or more central processing units (CPUs) (fig. 1 master devices 4, bus 8, external device 11 slave device 6 [0089] external device 11 processor ([0140] master device, graphics processor).
As per claim 11, Mace teaches wherein the filtering includes blocking the one or more transactions from being included in the transmission ([0109] control transaction interface, prevent issue of a transaction request ).
Claim 12 recites system for elements similar to claim 1. Therefore, it is rejected for the same rationale.
As per claim 14, Mace teaches incrementing includes adding the corresponding quantity to the counter ([0011] amount of bus or slave device bandwidth, occupied, transaction request, rate at which transaction requests are issued [0012] number of outstanding transaction requests, i.e. number of transaction requests that have been issued to the bus system and are awaiting servicing by the slave device, measure of the bus bandwidth occupied i.e. amount of data being transferred [0019] accumulator, increment the accumulation value, amount, proportional, number of outstanding transaction requests greater than N [0021] modifies, accumulation value, per processing cycle)
Claim 15 recites elements similar to combination of part of claims 5 and 11. Therefore, it is rejected for the same rationale.
Claim 16 recites elements similar to combination of part of claim 4 and additionally claiming filtering uses the first and second counter (same as claim Mace: [0019]). Therefore, it is rejected for the same rationale.
As per claim 17, Mace teaches the data transfer corresponds to one or more downstream transactions to be received, responsive to including the plurality of transactions in the time slot ([0019] fig. 19 read/write transaction [0138] response to a transaction request [0034] type of transaction requests [0006] master device, time slots).
Krueger teaches remaining claim elements of data transfer in one or more time slots subsequent to the time slot ([0184] usage against a limit can be determined, counter, count usage of a resource limited by said limit, counter resets every predetermined period of time [0188] counter, keeps track, counter, transaction forward, incremented, received response, counter, decremented [0189] counter associated with a period of time; counter and limit could be directed towards data transferred over a period of time ).
As per claim 18, Mace teaches wherein the filtering is based at least on reducing an allocation of data transfer volume to the one or more processing resources for the time slot in response to a determination that incoming traffic from an entity is directed to the one or more processing resources ([0012] measure of the bus bandwidth occupied by the master device, higher the number of outstanding transaction requests, associated with master device; higher the proportion i.e. increasing/decreasing of the bus bandwidth occupied by the master device [0097] allowed to issue a received transaction request).
As per claim 19, Krueger teaches wherein the system is comprised in at least one of:
a control system for an autonomous or semi-autonomous machine;
a perception system for an autonomous or semi-autonomous machine;
a system for performing simulation operations;
a system for performing digital twin operations;
a system for performing light transport simulation;
a system for performing collaborative content creation for 3D assets;
a system for performing deep learning operations;
a system implemented using an edge device;
a system implemented using a robot;
a system for performing conversational Al operations;
a system for generating synthetic data;
a system incorporating one or more virtual machines (VMs) ([0002] software execution environments, applications or virtual machines);
a system implemented at least partially in a data center ([0030] data center server application); or
a system implemented at least partially using cloud computing resources.
Claim 20 recites at least one processor comprising: one or more circuits for elements similar to claim 1. Therefore, it is rejected for the same rationale.
As per claim 21, Mace teaches wherein a second time slot uses the threshold volume of data transfer reduced volume of data transfer ([0006] master device, generate transaction requests at a higher rate than the other master device, master receives, more time slots than another master device, bus system [0012] higher the number of outstanding transaction requests associated with the master device, the higher the proportion i.e. increasing / decreasing of the bus/slave bandwidth occupied by that master device).
Krueger teaches remaining claim elements of at least on the one or more processing resource exceeding the threshold volume of data transfer in the time slot ([0186] fig. 16 current bandwidth> maximum bandwidth-y 362, set preference =3 364 [0033] [0184] usage against a limit can be determined, counter, count usage of a resource limited by said limit, counter resets every predetermined period of time [0188] counter, keeps track, transaction forward, received response [0189] counter associated with a period of time; counter and limit could be directed towards data transferred over a period of time [0029] resources for handling transactions, interconnects, amount of bandwidth available for handling memory transaction).
Claim 23 recites elements similar to claim 19. Therefore, it is rejected for the same rationale.
Claims 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mace in view of Krueger, and further in view of Dodson, as applied to above claims, and further in view of Park et al. (US 2021/0034296 A1, hereafter Park).
Park was cited in the last office action.
As per claim 13, Dodson teaches where in the data size is included in corresponding transaction and is extracted to determine the corresponding quantity (fig. 6 read queue 600 data size 612 col 13 lines 7-11 amount of data fetched for each request is specified by the selected data size 612).
Mace, Krueger and Dodson, in combination, do not specifically teach data size included in a header of the transaction and is extracted from the header.
Park, however, teaches wherein the data size is included in a header of the transaction and is extracted from the header ([0190] read operation, command UPIU, received [0192] header, transaction type, expected data transfer length ).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to combine the teachings of Mace, Krueger and Dodson with the teachings of Park of read operation UPIU command with header comprising expected data transfer length corresponding to improve efficiency and allow the data volume is included in a header of the transaction and is extracted from the header to the method of Mace, Krueger and Dodson as in the instant invention. The combination would have been obvious because supplementing the teachings of managing bus bandwidth by Mace, Krueger and Dodson with the teachings of Park of command header for the read operation including expected data transfer length to yield predictable results of determining the data volume to be transferred based on the transaction header including expected length of data transfer with reasonable expectation of success and improved efficiency.
Claims 22 is rejected under 35 U.S.C. 103 as being unpatentable over Mace in view of Krueger, and further in view of Dodson, as applied to above claims, and further in view of Watanbe (US 2023/0043990 A1).
As per claim 22, Mace teaches wherein the volume of data transfer is a first volume of downstream data transfer allocated to the one or more processing resources for the time slot ([0011] amount, bus, bandwidth, occupied, transaction requests, master device [0089] fig. 1 master devices 4 [0140] different types of the transaction requests, requiring different amount of bandwidth, a type of transaction request which does not require much bus bandwidth is not unnecessarily allocated a large amount of bandwidth, whilst a type of transaction request from the same master device that requires a higher rate of bandwidth can still receive its required allocation i.e. bandwidth allocation based on transaction type from same master device [0141] fig. 19 read transaction i.e. downstream), and
the one or more circuits are further to enforce a second volume of upstream data transfer allocated to the one or more processing resources for the time slot based at least on the transaction type ([0011] amount, bus, bandwidth, occupied, transaction requests, master device [0089] fig. 1 master devices 4 [0140] different types of the transaction requests, requiring different amount of bandwidth, a type of transaction request which does not require much bus bandwidth is not unnecessarily allocated a large amount of bandwidth, whilst a type of transaction request from the same master device that requires a higher rate of bandwidth can still receive its required allocation i.e. bandwidth allocation based on transaction type from same master device [0141] fig. 19 write transaction i.e. upstream).
Krueger teaches remaining claim elements of threshold volume of data transfer ([0186] minimum / maximum bandwidth limits [0033] [0184] usage against a limit can be determined, counter, count usage of a resource limited by said limit, counter resets every predetermined period of time [0188] counter, keeps track, counter, transaction, received response [0189] counter associated with a period of time; counter and limit could be directed towards data transferred over a period of time [0029] resources for handling transactions, interconnects, amount of bandwidth available for handling memory transaction).
Mace, Krueger, and Dodson, in combination, don’t specifically teach the threshold volume is downstream transfer and second threshold volume of upstream data transfer.
Watanbe, however, teaches the threshold volume is downstream transfer and second threshold volume of upstream data transfer (fig. 10 bandwidth / IOPS, read/write thresholds).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to combine the teachings of Mace, Krueger and Dodson with the teachings of Watanbe for different threshold corresponding to the different read/write operations to improve efficiency and allow the threshold volume is downstream transfer and second threshold volume of upstream data transfer to the method of Mace, Krueger and Dodson as in the instant invention. The combination would have been obvious because supplementing the teachings of managing bus bandwidth by Mace, Krueger and Dodson with the teachings of Watanbe of different threshold corresponding to the different operation i.e. read/write to yield predictable results of different thresholds for upstream / downstream data volume transfer and improved efficiency.
Response to Arguments
The previous claim objections have been withdrawn.
The previous objections under 35 USC 112 (b) have been withdrawn.
The previous objections under 35 USC 101 have been withdrawn.
Applicant's arguments filed on 01/12/2026 have been fully considered but they are not persuasive. In Applicant’s response filed on 01/12/2026, Applicant argues the following:
Applicant respectfully submits that the combination of references does not teach or suggest, at least “a data size that would be consumed by including the transaction in the transmission, the corresponding quantity varying amongst a set of the plurality of transactions that have a same transaction type of the respective transaction types as a function of their respective data sizes," as recited in amended claim 1.
Mace doesn’t teach “a counter that represents a total volume of data transfer of the transmission that is consumed by the plurality of transactions” as recited in the amended claim 1.
Mace doesn’t teach or suggest “counter… that aggregates the corresponding quantity of at least two of the plurality of transactions that correspond to different transaction types of the respective transaction types” with “… a corresponding quantity based at least one a corresponding transaction type” as recited in the amended claim 1.
Examiner has thoroughly considered Applicant’s arguments, but respectfully, find them unpersuasive for at least the following reasons:
With respect to point i.) Argument is moot in view of new grounds of rejections.
With respect to point ii.) First, Examiner respectfully request applicant to clarify the claim limitations i.e. consumption of data by transaction. Examiner has interpreted the consuming data is referring to amount of data fetched/transferred in response to the processed transaction.
Mace teaches the amount of bus or slave device bandwidth that is occupied by transaction requests from a particular master device is dependent upon the rate at which transaction requests are issued from that master device to the bus system. Therefore, by controlling the issuing of the transaction requests from the master device to the bus system, the bus/slave bandwidth associated with the master device can be regulated ([0011] [0012]). Bandwidth occupied by the transaction request is equivalent to the limitations of amount of data being transferred and is based on the transaction issue rate. Mace further provides a method of counting or keeping track of transaction using accumulator ([0019]). In addition to Mace, Krueger also teaches a counter to count usage of resource ([0184]) and keeps track of transactions ([0188]), and further in other embodiments teaches counter is associated with data transferred over a period of time ([0189]), all of which are equivalent to the limitations of claim total volume of the transmission that is consumed by the plurality of transaction as recited in claim 1.
With respect to point iii.) as explained above with respect to point ii., there are various ways to keep track of the aggregate volume of data corresponding to the transactions being transmitted. Further, each cited prior art independently teaches transactions can be read/write transactions (Mace [0035] Dodson (fig. 3) Watanbe [0022]). Therefore, cited prior arts teaches at least two of the plurality of transactions that correspond to different transaction types of the respective transaction types as recited in the amended claim 1.
Examiners Note
Applicant is further reminded of that the cited paragraphs and in the references as applied to the claims above for the convenience of the applicant(s) and although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider all of the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABU ZAR GHAFFARI whose telephone number is (571)270-3799. The examiner can normally be reached on Monday-Thursday 9:00 - 17:00 Hrs.
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/ABU ZAR GHAFFARI/Primary Examiner, Art Unit 2195
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