DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This non-final office action is responsive to the RCE filed on 07/15/2026.
Claims 1-23 are pending.
Response to Amendment
Applicant has amended independent claims 1, 12, 20 and dependent claims 2, 3, 5, 7-8, 11, 13, 15, 16, and 18 to include new/old limitations in a form not previously presented necessitating new search and considerations.
Claim Objections
Claim 1-23 are objected to because of the following informalities:
Claims recites -- data volume -- on multiple occasion in claims 1-23 without ever reciting the same in the specification. Applicant is requested to use terms that are present in the specification for consistency.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 5, 8, 11 and 13 are rejected under 35 U.S.C. 112 (b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or joint inventor regards as the invention.
The following claim language is not clearly understood:
Claim 5 recites “data volume represented by the corresponding quantity for the first transaction is further of the request”. It is unclear data volume is part of the request or part of the response of the request or either.
Claim 8 recites “partition size of a partition of a host device”. It is unclear what is meant by partition of host device, and what is being referred by partition size.
Claim 11 recites “downstream traffic sent…based at least on receiving at least one of the one or more responses to the request”. It is unclear if the traffic is in response to receiving the requests or in response to receiving the response to the request.
Claim 13 recites “header of the transaction”. It is unclear if the header of the transaction or header of the packet of the transaction / traffic is being intended.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12, 14-21, 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mace et al. (US 2012/0011291 A1, hereafter Mace) in view of Dodson et al. (US 9,684,461 B1, hereafter Dodson) and further in view of Krueger (US 2018/0203723 A1, hereafter Krueger).
Mace, Dodson and Kruger were cited in the last office action.
As per claim 1, Mace teaches the invention substantially as claimed including a method comprising:
identifying respective transaction types of a plurality of transactions issued, for transmission in a time slot ([0140] transaction requests of different types, identifier identifying the type of issued transaction request [0005] fixed slots to each of master devices [0006] weighted round robin scheme, one master device receives more time slots than another master device) and over one or more buses by one or more processing resources of a plurality of processing resources sharing the one or more buses ([0089]fig. 1 master devices 4 slave devices 6 bus system 8 interconnects 10; routing transaction requests between master devices and slave devices [0090]);
determining, for each transaction of the plurality of transactions ([0034] plurality of types of transaction requests [0035] transaction requests, read transaction requests, write transaction requests ), a corresponding quantity of data transfer over the one or more buses ([0140] transaction requests, different bandwidth requirements of these types of transactions requests; different type of transaction requests, type, transaction, request which does not require much bus bandwidth, request requires a higher rate of bandwidth i.e. bandwidth represents amount of data per unit time; different quantity of data transfer [0011] rate, transaction requests, issued from the master device) that would be caused by including the transaction in the transmission ([0035] read/write transaction requests [0140] transaction requests), the corresponding quantity being determined based at least on a corresponding transaction type of the respective transaction types ([0140] transaction requests, different bandwidth requirements of these types of transactions requests; different type of transaction requests, type, transaction, request which does not require much bus bandwidth, request requires a higher rate of bandwidth i.e. different quantity of data transfer) and representing a data volume of at least one of a request represented by the transaction ([0140] type of transaction request, require, not/higher rate bus bandwidth i.e. bandwidth represents amount of data transfer per unit time corresponds to the expected data volume associated with the transaction) or one or more responses to the request that are to be received during one or more time slots subsequent to the time slot ([0004] master device, request, service, slave device, perform the requested service, response to the master device [0138] response to transaction request, delivers the response and any data required to the master device [0136] fig. 16 time averaged outstanding transaction value, averaged, over the cycles [0137] transaction request, processing cycle), the data volume represented by the corresponding quantity for a first transaction of the plurality of transactions being at least of the one or more responses ([0138] response to transaction request, delivers the response and any data required to the master device [0140] type of transaction request, require, not/higher rate bus bandwidth i.e. bandwidth represents amount of data transfer per unit time, corresponds to the expected data volume associated with the transaction);
incrementing, by the corresponding quantity of each of the plurality of transactions, a counter assigned to the time slot that represents a total volume of data transfer that would be caused by including the plurality of transactions in the transmission ([0011] amount of bus or slave device bandwidth, occupied, transaction request, rate at which transaction requests are issued [0012] number of outstanding transaction requests, i.e. number of transaction requests that have been issued to the bus system and are awaiting servicing by the slave device, measure of the bus bandwidth occupied i.e. amount of data that would be transferred; higher the number of outstanding transaction requests associated with the master device, the higher the proportion of the bus/slave bandwidth occupied by that master device [0019] accumulator, increment the accumulation value, amount, proportional, number of outstanding transaction requests greater than N [0021] modifies, accumulation value, per processing cycle [0140] transaction requests, different type identifiers, different bandwidth requirements of these types of transactions requests; different type of transaction requests, type, transaction, request which does not require much bus bandwidth, request requires a higher rate of bandwidth) and that aggregates the corresponding quantity of at least two of the plurality of transactions that correspond to different transaction types of the respective transaction types ([0140] transaction requests, different type identifiers, different bandwidth requirements of these types of transactions requests; different type of transaction requests, type, transaction, request which does not require much bus bandwidth, request requires a higher rate of bandwidth [0035] transaction request, read, write); and
blocking the first transaction from being included in the transmission ([0008] selectively issue, transaction requests to, bus system i.e. blocking remaining unselected transactions; [0036] read/write transaction requests, arbiter, current number of outstanding transaction request being equal to N-1 to select one of pending read transaction and write transaction to issue, selection criteria to select one of the pending read and write transaction requests, selection criterion could be favor write over read, at random, round robin [0109] prevent issue of transaction request) based at least on the corresponding quantity for the first transaction causing the counter to exceed a threshold volume of data transfer allocated to the time slot ([0019] bus, processing cycles, accumulator, issue control, control the transaction interface, issue, an additional request; when said current number of outstanding transaction request is fewer than N; or current number of outstanding transaction request is N and accumulation value is decremented beyond a predetermined threshold value / equal to predetermined threshold value [0140] transaction requests, different type identifiers, different bandwidth requirements of these types of transactions requests i.e. bandwidth is amount of data transfer per unit time [0035] transaction request, read, write [0017] number of outstanding transaction requests, time averaged over an averaging cycle, repeats over time).
Mace doesn’t specifically teach quantity representing a data volume of at least one of a request represented by the transaction (although require bandwidth is equivalent metric), counter assigned to the time slot that represents a total volume of data transfer that would be caused by including the plurality of transactions in the transmission (although total volume of data is captured by the total bandwidth requirement for different types of transaction); quantity for the transaction exceed a threshold volume (this is also captured in terms of bandwidth); blocking transaction (although selectively issuing is same as blocking other transactions).
Dodson, however, teaches quantity representing a data volume of at least one of a request represented by the transaction (col 5 lines 9-20 read request, specifies data size for the read request), counter assigned to the time slot that represents a total volume of data transfer that would be caused by including the plurality of transactions in the transmission (fig. 3 col 10 lines 10-49 monitor utilization of bus, time window, bandwidth used for reads, multiple clock cycles for reads and writes, fetching data, writing data to memory); quantity for the transaction exceed a threshold volume (col 6 lines 45-65 monitor the utilization of bus 124, utilization exceeds the threshold).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the claimed invention was made to combine the teachings of Mace with the teachings of Dodson of request specifying data size, monitoring bus utilization of the bus by the read/write request during a time window of multiple read/write clock cycles, utilization exceeding the threshold to improve efficiency and allow quantity representing a data volume of at least one of a request represented by the transaction, counter assigned to the time slot that represents a total volume of data transfer that would be caused by including the plurality of transactions in the transmission; quantity for the transaction exceed a threshold volume to the method of Mace as in the instant invention.
The combination would have been because applying the known method of transaction specifying data size, monitoring bus utilization by the transaction during a time window, utilization exceeding a threshold as taught by Dodson to the method of Mace to convert the taught metrics in volume / size of data transfer instead of bandwidth to yield usability and improved efficiency.
Mace and Dodson, in combination, do not specifically teach blocking transaction.
Krueger, however, teaches blocking transaction based at least on the transaction causing to exceed a threshold volume of data transfer ( [0188] limit met or exceeded, transaction will not be forwarded [0029] resources for handling transactions, interconnects i.e. bus, amount of bandwidth available for handling memory transaction [0177] limit, bandwidth limit, memory system component, bandwidth, expressed as an amount of data transferred in, out or in and out of the at least one memory system component over a period of time [0178] current bandwidth usage of said memory system components, exceeds said maximum bandwidth [0184] usage against a limit can be determined, counter, count usage of a resource limited by said limit [0189] counter associated with a period of time; counter and limit could be directed towards data transferred over a period of time [0186] fig. 16 current bandwidth> maximum bandwidth-y 362, set preference =3 364 [0033] [0192] fig. 20 384 386).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to combine the teachings of Mace with the teachings of Krueger and Dodson of using counter to determine resource usage against a limit for a period of time e.g. counter limit counter and limit could be directed towards data transferred over a period of time and not forwarding transaction if the limit is met to improve efficiency and allow a counter that represents a total volume of data transfer of the transmission that is consumed by the plurality of transaction, and filtering based on threshold volume of data transfer to the method of Mace and Dodson as in the instant invention.
The combination would have been obvious because using counter for the bus bandwidth usage and identifying and controlling progression of transaction with usage exceeding maximum limit as taught by Krueger to the amount of bus bandwidth usage taught by Mace and Dodson to yield predictable result of blocking transaction causing exceeding the threshold and improved efficiency.
As per claim 2, Mace teaches wherein the plurality of transactions are upstream transactions ([0035] write transaction i.e. upstream), and the volume of data transfer corresponds to a downstream data volume that would be caused by including the plurality of transactions in the transmission ([0004] slave device, performs requested service and send a response to the master device i.e. downstream [0091] slave, bandwidth, available for use by respective master device, divided evenly, may require more bandwidth [0011] amount of bus or slave device bandwidth, occupied, transaction request, rate at which transaction requests are issued [0012] number of outstanding transaction requests, i.e. number of transaction requests that have been issued to the bus system and are awaiting servicing by the slave device, measure of the bus bandwidth occupied i.e. amount of data being transferred).
Krueger teaches remaining claim elements of total volume of data transferred ([0184] counter, count usage of a resource limited by said limit [0189] counter associated with a period of time; counter and limit could be directed towards data transferred over a period of time [0188] downstream).
As per claim 3, Mace teaches wherein the time slot and the one or more time slots are of a plurality of sequential time slots each corresponding to respective sequential processing cycles ([0019] bus system, clocked, processing cycles [0020] number of processing cycles, [0029] following processing cycles i.e. sequential).
Krueger teaches remaining claim elements of resetting the counter for the one or more processing resources based at least on detecting an end to the time slot and a beginning of a subsequent tile slot in the plurality of sequential time slots ([0184] usage against a limit can be determined, counter, count usage of a resource limited by said limit, counter resets every predetermined period of time).
As per claim 4, Krueger teaches wherein the counter is a first counter corresponding to a first volume of downstream data allocated to the one or more processing resources for the time slot ([0184] counter, count usage of a resource limited by said limit, counter resets every predetermined period of time [0188] counter, keep track of number of outstanding transactions, downstream [0189] counter associated with a period of time; counter and limit could be directed towards data transferred over a period of time), and the method further includes updating a second counter corresponding to a second volume of upstream data allocated to the one or more processing resources for the time slot based at least on the respective transaction type ([0184] counter, count usage of a resource limited by said limit, counter resets every predetermined period of time [0188] counter, keep track of number of outstanding transactions, response received, counter is decremented i.e. upstream can be separately tracked [0189] counter associated with a period of time; counter and limit could be directed towards data transferred over a period of time [0165] upstream response).
As per claim 5, Dodson teaches data volume represented by the corresponding quantity for the first transaction is further of the request (col 5 lines 9-20 read request, specifies data size for the read request).
As per claim 6, Mace teaches receiving the data generated from the transaction ([0138] response to a transaction request, data required); and
determine the corresponding transaction type (([0034] transaction request, types).
Kruger teaches remaining claim elements of receiving the decoded packet data generated from one or more packets representing the transaction ([0037] fetch instruction, decoding the fetched instructions, queuing instructions );
analyzing the decoded packet data ([0186] next transaction, analyzed).
As per claim 7, Mace teaches wherein the one or more processing resources connect to a bus interface corresponding to the one or more buses ([0097] fig. 4 master devices M0, M1, transaction I/F0, I/F1 transaction interface 18 receives a transaction request from the master device and selectively issues the transaction request to the bus system 8, from where the transaction request can be forwarded to a further interconnect 10 or to a slave device 6 coupled to the interconnect 10),
Dodson teaches plurality of send and receive lines of a bus interface (col 4 lines 11-20 memory interface bus, multiple parallel lines, to communicate), and the threshold volume of data transfer corresponds to a total volume of data transfer allocated to the one or more processing resources for the plurality of send and receive lines (col 4 lines 11-20 memory interface bus, multiple parallel lines, to communicate col 8 lines 41-50 core 210 214 218 sending request, return data, col 6 lines 45-65 monitor the utilization of bus 124, utilization exceeds the threshold).
As per claim 8, Mace teaches wherein the total volume of data transfer allocated to the time slot is proportional to a partition size of a partition of host device ([0093] fig. 3 input to the queue, multiple sources, different rates, queue length for items form input sources is proportional to the input rate for that input rate [0094] queue length, indication of the queue bandwidth used by a particular input source), the partition represented by the one or more processing resources ( [0093] multiple sources [0034] graphics processor).
As per claim 9, Mace teaches wherein the one or more buses correspond to a memory interface that is shared amongst the plurality of processing resources (fig. 1 master devices 4-0, 4-1 interconnect 10-0 10-1 bus system 8).
As per claim 10, Mace teaches wherein the one or more processing resources are of one or more graphics processing units (GPUs) ([0140] master device, graphics processor) and the one or more buses connect the one or more GPUs to one or more central processing units (CPUs) (fig. 1 master devices 4, bus 8, external device 11 slave device 6 [0089] external device 11 processor ([0140] master device, graphics processor).
As per claim 11, Mace teaches upstream requests from the one or more processing resources ([0011] amount, bus, bandwidth, occupied, transaction requests, master device [0089] fig. 1 master devices 4 [0035] read transaction / write transaction request [0140] different types of the transaction requests, requiring different amount of bandwidth), and the method further includes downstream traffic send to the one or more processing resources ([0011] amount, bus, bandwidth, occupied, transaction requests, master device [0089] fig. 1 master devices 4 [0035] read transaction / write transaction request) based at least on receiving at least one or one or more responses to the request ([0138] response to transaction request, delivery to the master device, response and any data required to the master device), filter the downstream traffic ([0114] prevent additional transaction request being issued).
Dodson teaches remaining claim elements of counter is a first counter corresponding to upstream requests (col 6 line 49-60 monitor the utilization, interface bus, during the time window, write request); incrementing a second counter corresponding to downstream traffic (col 6 line 49-60 monitor the utilization, interface bus, during the time window, read request, fetch data block).
Claim 12 recites system for elements similar to claim 1. Therefore, it is rejected for the same rationale.
As per claim 14, Mace teaches incrementing includes adding the corresponding quantity to the counter ([0011] amount of bus or slave device bandwidth, occupied, transaction request, rate at which transaction requests are issued [0012] number of outstanding transaction requests, i.e. number of transaction requests that have been issued to the bus system and are awaiting servicing by the slave device, measure of the bus bandwidth occupied i.e. amount of data being transferred [0019] accumulator, increment the accumulation value, amount, proportional, number of outstanding transaction requests greater than N [0021] modifies, accumulation value, per processing cycle).
Claim 15 recites elements similar to claim 11. Therefore, it is rejected for the same rationale.
Claim 16 recites elements similar to combination of part of claim 1 and claim 4. Therefore, it is rejected for the same rationale.
As per claim 17, Mace teaches the data transfer corresponds to one or more downstream transactions to be received, responsive to including the plurality of transactions in the time slot ([0019] fig. 19 read/write transaction [0138] response to a transaction request [0034] type of transaction requests [0006] master device, time slots).
Krueger teaches remaining claim elements of data transfer in one or more time slots subsequent to the time slot ([0184] usage against a limit can be determined, counter, count usage of a resource limited by said limit, counter resets every predetermined period of time [0188] counter, keeps track, counter, transaction forward, incremented, received response, counter, decremented [0189] counter associated with a period of time; counter and limit could be directed towards data transferred over a period of time ).
As per claim 18, Mace teaches wherein the blocking ([0109] prevent issue of transaction request ) is based at least on reducing the threshold volume of data transfer allocated to the time slot ([0024] predetermined threshold value, decrementing [0012]) in response to a determination that incoming traffic initiated by an entity that is separate from the one or more processing resources is directed to the one or more processing resources ([0004] slave device, sends response to the master device via the bus system [0097] ).
Dodson teaches remaining claim elements of reducing the threshold value of data transfer allocated to the time slot (col 10 lines 66-67 col 11 lines 1-8 threshold settings 312, identify different threshold levels, different bus utilization).
As per claim 19, Krueger teaches wherein the system is comprised in at least one of:
a control system for an autonomous or semi-autonomous machine;
a perception system for an autonomous or semi-autonomous machine;
a system for performing simulation operations;
a system for performing digital twin operations;
a system for performing light transport simulation;
a system for performing collaborative content creation for 3D assets;
a system for performing deep learning operations;
a system implemented using an edge device;
a system implemented using a robot;
a system for performing conversational Al operations;
a system for generating synthetic data;
a system incorporating one or more virtual machines (VMs) ([0002] software execution environments, applications or virtual machines);
a system implemented at least partially in a data center ([0030] data center server application); or
a system implemented at least partially using cloud computing resources.
Claim 20 recites at least one processor comprising: one or more circuits for elements similar to claim 1. Therefore, it is rejected for the same rationale.
As per claim 21, Mace teaches wherein a second time slot uses the threshold volume of data transfer reduced volume of data transfer ([0006] master device, generate transaction requests at a higher rate than the other master device, master receives, more time slots than another master device, bus system [0012] higher the number of outstanding transaction requests associated with the master device, the higher the proportion i.e. increasing / decreasing of the bus/slave bandwidth occupied by that master device).
Krueger teaches remaining claim elements of at least on the one or more processing resource exceeding the threshold volume of data transfer in the time slot ([0186] fig. 16 current bandwidth> maximum bandwidth-y 362, set preference =3 364 [0033] [0184] usage against a limit can be determined, counter, count usage of a resource limited by said limit, counter resets every predetermined period of time [0188] counter, keeps track, transaction forward, received response [0189] counter associated with a period of time; counter and limit could be directed towards data transferred over a period of time [0029] resources for handling transactions, interconnects, amount of bandwidth available for handling memory transaction).
Claim 23 recites elements similar to claim 19. Therefore, it is rejected for the same rationale.
Claims 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mace in view of Dodson, and further in view of Krueger, as applied to above claims, and further in view of Park et al. (US 2021/0034296 A1, hereafter Park).
Park was cited in the last office action.
As per claim 13, Dodson teaches where in the data volume corresponds to a data size is included in corresponding transaction and is extracted to determine the corresponding quantity (fig. 6 read queue 600 data size 612 col 13 lines 7-11 amount of data fetched for each request is specified by the selected data size 612).
Mace, Dodson and Krueger, in combination, do not specifically teach data size included in a header of the transaction and is extracted from the header.
Park, however, teaches wherein the data size is included in a header of the transaction and is extracted from the header ([0190] read operation, command UPIU, received [0192] header, transaction type, expected data transfer length ).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to combine the teachings of Mace, Dodson and Krueger with the teachings of Park of read operation UPIU command with header comprising expected data transfer length corresponding to improve efficiency and allow the data volume is included in a header of the transaction and is extracted from the header to the method of Mace, Dodson and Krueger as in the instant invention. The combination would have been obvious because supplementing the teachings of managing bus bandwidth by Mace, Dodson and Krueger with the teachings of Park of command header for the read operation including expected data transfer length to yield predictable results of determining the data volume to be transferred based on the transaction header including expected length of data transfer with reasonable expectation of success and improved efficiency.
Claims 22 is rejected under 35 U.S.C. 103 as being unpatentable over Mace in view of Dodson, and further in view of Krueger, as applied to above claims, and further in view of Watanbe (US 2023/0043990 A1).
Watanbe was cited in the last office action.
As per claim 22, Mace teaches wherein the volume of data transfer is a first volume of downstream data transfer allocated to the one or more processing resources for the time slot ([0011] amount, bus, bandwidth, occupied, transaction requests, master device [0089] fig. 1 master devices 4 [0140] different types of the transaction requests, requiring different amount of bandwidth, a type of transaction request which does not require much bus bandwidth is not unnecessarily allocated a large amount of bandwidth, whilst a type of transaction request from the same master device that requires a higher rate of bandwidth can still receive its required allocation i.e. bandwidth allocation based on transaction type from same master device [0141] fig. 19 read transaction i.e. downstream), and
the one or more circuits are further to enforce a second volume of upstream data transfer allocated to the one or more processing resources for the time slot based at least on the transaction type ([0011] amount, bus, bandwidth, occupied, transaction requests, master device [0089] fig. 1 master devices 4 [0140] different types of the transaction requests, requiring different amount of bandwidth, a type of transaction request which does not require much bus bandwidth is not unnecessarily allocated a large amount of bandwidth, whilst a type of transaction request from the same master device that requires a higher rate of bandwidth can still receive its required allocation i.e. bandwidth allocation based on transaction type from same master device [0141] fig. 19 write transaction i.e. upstream).
Krueger teaches remaining claim elements of threshold volume of data transfer ([0186] minimum / maximum bandwidth limits [0033] [0184] usage against a limit can be determined, counter, count usage of a resource limited by said limit, counter resets every predetermined period of time [0188] counter, keeps track, counter, transaction, received response [0189] counter associated with a period of time; counter and limit could be directed towards data transferred over a period of time [0029] resources for handling transactions, interconnects, amount of bandwidth available for handling memory transaction).
Mace, Krueger, and Dodson, in combination, don’t specifically teach the threshold volume is downstream transfer and second threshold volume of upstream data transfer.
Watanbe, however, teaches the threshold volume is downstream transfer and second threshold volume of upstream data transfer (fig. 10 bandwidth / IOPS, read/write thresholds).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to combine the teachings of Mace, Krueger and Dodson with the teachings of Watanbe for different threshold corresponding to the different read/write operations to improve efficiency and allow the threshold volume is downstream transfer and second threshold volume of upstream data transfer to the method of Mace, Krueger and Dodson as in the instant invention. The combination would have been obvious because supplementing the teachings of managing bus bandwidth by Mace, Krueger and Dodson with the teachings of Watanbe of different threshold corresponding to the different operation i.e. read/write to yield predictable results of different thresholds for upstream / downstream data volume transfer and improved efficiency.
Response to Arguments
The previous objections under 35 USC 112 (b) have been withdrawn.
Applicant's arguments filed on 07/15/2026 have been fully considered but they are moot in view of new ground of rejections.
Examiners Note
Applicant is further reminded of that the cited paragraphs and in the references as applied to the claims above for the convenience of the applicant(s) and although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider all of the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABU ZAR GHAFFARI whose telephone number is (571)270-3799. The examiner can normally be reached on Monday-Thursday 9:00 - 17:00 Hrs.
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/ABU ZAR GHAFFARI/Primary Examiner, Art Unit 2195
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