DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This non-final office action is responsive to the RCE filed on 08/14/2025.
Claims 1-23 are pending.
Response to Amendment
Applicant has amended independent claims 1, 12, 20 and dependent claims 2-5, 7, 11, 13-18, 21-22 to include new/old limitations in a form not previously presented necessitating new search and considerations.
Claim Objections
Claim 1 objected to because of the following informalities:
-- busses -- should be -- buses -- in claim 1 line 6.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-23 are rejected under 35 U.S.C. 112 (b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or joint inventor regards as the invention.
The following terms lack proper antecedent basis:
-- the time period -- in claims 1, and 12.
The following claim language is not clearly understood:
Claim 1 recites “quantity that indicates a data volume, … that is attributable to transmitting the transaction over the one or more bus”. It is not definite if “attributable” refers to the data volume that is attributed or not yet attributed to the transaction. It is also unclear “data volume” is referring to the amount of data corresponding to the transaction or available bandwidth for transfer of data.
Claim 1 recites “counter that tracks for a time slot, a total volume of data transfer over the one or more buses, the total volume attributable to a plurality of transaction issued”. It is unclear if the counter is tracking the total volume before or during or after the transaction is processed/transmitted. It is also not definite if “attributable” is referring to “attributed” or “not yet attributed” to the transaction and if the volume is referring to the data transferred over the buses or the amount of bandwidth consumed or would be consumed for the plurality of transaction.
Claim 1 recites “counter … for a time slot” and later recites “filtering, during the time period”. It is unclear if the time slot and time period is referring to same or different time duration and if these time durations are arbitrarily selected.
Claims 12 and 20 recite elements of claim 1 and have similar deficiency as claim 1. Therefore, they are rejected for the same rational. Remaining dependent claims 2-11, 13-19 and 21-23 are also rejected due to their dependency on the rejected independent claims.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-4, 6-23 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more or integrating into practical application.
Based upon at least the decision by the United States Supreme Court in Alice Corp. v. CLS Bank Int'l, 134 S. Ct. 2347, 2354 (2014), post-Alice precedential court decisions, and 2019 Revised Patent Subject Matter Eligibility Guidance, claims 1-4, 6-23 are determined to be directed to an abstract idea. Examples of abstract ideas include at least Mathematical concepts, Mental process and Certain Methods of organizing human activity. Independent claim 1 is directed to “filtering transaction using the updated counter corresponding to amount of allocated bandwidth to processing resource over one or more buses for a time interval” at a high level of generality.
Step 1
As described in MPEP § 2106, subsection III, Step 1 of the eligibility analysis asks: Is the claim to a process, machine, manufacture or composition of matter?
Claim 1 recites a method, which falls within the “process” category of 35 U.S.C. § 101. Claim 12 recites a system comprising circuits, which falls within the “machine / manufacture” category of 35 U.S.C. § 101. Claim 20 recites a processor, which falls within the “machine / manufacture” category of 35 U.S.C. § 101. Thus, the analysis determines whether the claims recite a judicial exception and fail to integrate the exception into practical application. See Memorandum, 84 Fed. Re. 54-55. If both elements are satisfied, the claims are directed to a judicial exception under the first step of the Alice/Mayo test, See id.
Step 2A Prong One
As described in MPEP § 2106, subsection III, Step 2A of the Office’s eligibility analysis is the first part of the Alice/Mayo test, i.e., the Supreme Court’s "framework for distinguishing patents that claim laws of nature, natural phenomena, and abstract ideas from those that claim patent-eligible applications of those concepts." Alice Corp. Pty. Ltd. v. CLS Bank Int'l, 573 U.S. 208, 217-18, 110 USPQ2d 1976, 1981 (2014) (citing Mayo, 566 U.S. at 77-78, 101 USPQ2d at 1967-68).
Step 2A is a two-prong inquiry, in which examiners determine in Prong One whether a claim recites a judicial exception, and if so, then determine in Prong Two if the recited judicial exception is integrated into a practical application of that exception.
Claim Elements
1. A method comprising:
generic method
Identifying, from a plurality of transaction types, a transaction type of a transaction from one or more processing resources of a plurality of processing resources sharing one or more buses;
Mental process abstract idea
determining, based on the identified transaction type, a quantity that indicates a data volume, over the one or more buses, of one or more of downstream data or upstream data that is attributable to transmitting the transaction over the one or more buses;
Mental process abstract idea
updating, by the determined quantity, a counter that tracks for a time slot, a total volume of data transfer over the one or more processing resources during the time slot,
Mental process abstract idea
the plurality of transactions including the transaction and at least two different types of the plurality of transaction types;
Mental Process abstract idea
determining, using the counter, that transmitting one or more transaction associated with the one or more processing resources over the one or more buses would exceed a threshold volume of data transfer allocated to the time slot for the one or more processing resources; and
Mental process abstract idea
based at least on determining, filtering, during the time period, the one or more transactions with respect to transmission over the one or more buses.
Mental process abstract idea
The overall process described by claim elements [ii]-[vii] describes “concepts performed in the human mind” or “observation, evaluation, judgement, opinion.” Memorandum, 84 Fed. Reg, 52. Thus claim element [ii]-[vii] recite the abstract concept of [m]ental processes.” Id. For example, claim element [ii] recites “identifying from a plurality of transaction types, a transaction type of a transaction from one or more processing resources of a plurality of processing resources sharing one or more buses”, which is a combination of observation, evaluation, judgement and opinion, and may be performed by human mind alone or with the help of pen and paper. Claim 1 limitation [iii] recites “determining, based on the identified transaction type, a quantity that indicates a data volume, over the one or more buses, of one or more of downstream data or upstream data that is attributable to transmitting the transaction over the one or more buses;”, which is directed to determining quantity of data transfer based on the transaction type, according to the broadest reasonable interpretation of the claim, and can be performed by human mind with or without the help of pen and paper because quantity of data can be determined based on observing the transaction type. Claim 1 step [iv] recites “updating, by the determined quantity, a counter that tracks for a time slot, a total volume of data transfer over the one or more processing resources during the time slot”, which is directed to updating a counter based on an observation i.e. total volume of data transfer, and therefore can be performed by human mind with or without the help of pen and paper. Similarly, claim 1 limitation [v] recites “the plurality of transactions including the transaction and at least two different types of the plurality of transaction types;”, which is a combination of observation, evaluation, judgement and opinion, and may be performed by human mind alone or with the help of pen and paper. Claim 1 step [vi] recites “determining, using the counter, that transmitting one or more transaction associated with the one or more processing resources over the one or more buses would exceed a threshold volume of data transfer allocated to the time slot for the one or more processing resources;”, which is a combination of one or more of observation, evaluation, judgement and opinion, and can be performed by human mind alone or with the help of pen and paper. Claim 1 step [vii] recites “based at least on determining, filtering, during the time period, the one or more transactions with respect to transmission over the one or more buses”, which is directed to filter based on a given condition e.g. counter and can be performed by human mind alone or with the help of pen and paper. Therefore, steps [ii]-[vii] resembles the idea of performing observation, evaluation, judgement and opinion according to the broadest reasonable interpretations of the claim elements and can be performed by human mind alone or with the aid of pen and paper. The courts consider a mental process (thinking) that "can be performed in the human mind, or by a human using a pen and paper" to be an abstract idea. CyberSource Corp. v. Retail Decisions, Inc., 654 F.3d 1366, 1372, 99 USPQ2d 1690, 1695 (Fed. Cir. 2011). Thus, claim 1 recites a judicial exception. Based on similar analysis and rationales, claims 12 and 20 also recite judicial exception.
Step 2A, Prong Two
As described in MPEP § 2106, subsection III, Step 2A of the Office’s eligibility analysis is the first part of the Alice/Mayo test, i.e., the Supreme Court’s "framework for distinguishing patents that claim laws of nature, natural phenomena, and abstract ideas from those that claim patent-eligible applications of those concepts." Alice Corp. Pty. Ltd. v. CLS Bank Int'l, 573 U.S. 208, 217-18, 110 USPQ2d 1976, 1981 (2014) (citing Mayo, 566 U.S. at 77-78, 101 USPQ2d at 1967-68).
Step 2A is a two-prong inquiry, in which examiners determine in Prong One whether a claim recites a judicial exception, and if so, then determine in Prong Two if the recited judicial exception is integrated into a practical application of that exception.
Because claims 1, 12 and 20 recite a judicial exception, Analysis determines if the claims recite additional elements that integrate the judicial exception into practical application. In addition to the limitations of claim 1 discussed above that recite the abstract concepts, claim 1 also recites additional claim elements e.g. limitations [i] recites “method”, which is generic computing method; limitation [ii] recites additional claim elements “plurality of processing resources sharing one or more buses”. However, these additional claim elements are available in common computing resources (See Background of the disclosure) and is neither inventive nor provide improvement to the technology / technical field and therefore these additional limitations do not integrate the abstract idea into practical application. The Specification doesn’t provide additional details that would distinguish the additional limitations recited in claim 1 from a generic implementation of the abstract idea. Thus, the claim elements recited in steps [i]-[vii] , under broadest reasonable interpretation, do not integrate the judicial exception into a practical application.
Thus, claim 1 recites a judicial exception without integrating into practical application. Based on similar analysis and rationales as above, claims 12 and 20 also recites judicial exception without integrating into practical application.
Step 2B
As described in MPEP § 2106, subsection III, Step 2B of the Office’s eligibility analysis is the second part of the Alice/Mayo test, i.e., the Supreme Court’s "framework for distinguishing patents that claim laws of nature, natural phenomena, and abstract ideas from those that claim patent-eligible applications of those concepts." Alice Corp. Pty. Ltd. v. CLS Bank Int'l, 573 U.S. 208, 217, 110 USPQ2d 1976, 1981 (2014) (citing Mayo, 566 U.S. 66, 101 USPQ2d 1961 (2012)).
Step 2B asks: Does the claim recite additional elements that amount to significantly more than the judicial exception.
Because claims 1, and 12 and 20 are directed to judicial exception, analysis must determine, according to Alice, whether these claims recite an element, or combination of elements that is enough to ensure that the claim is directed to significantly more than a judicial exception.
The Memorandum, Section III (B) (footnote 36) states:
In accordance with existing guidance, an Examiner’s conclusion that an additional element (or combination of elements) is well understood, routine, conventional activity must be supported with a factual determination. For more information concerning evaluation of well-understood, routine, convention activity, see MPEP 2106.05(d), as modified by the USPTO Berkheimer Memorandum.
The Berkheimer Memorandum, Section III(A)(1) states:
A Specification demonstrates the well-understood, routine, conventional nature of additional elements when it describes the additional elements as well-understood or routine or conventional (or an equivalent term), as a commercially available product, on in a manner that indicates that the additional elements are sufficiently well-known that the specification does not need to describe the particulars of such additional elements to satisfy 35 §U.S.C. 112(a). A finding that an element is well-understood, routine, or conventional cannot be based only on the fact that the specification is silent with respect to describing such element.
Additional claim elements “processing resource sharing one or more buses” as recited in limitations [ii] above is merely reciting common computing method / elements (See background of instant invention, cited prior arts). As such, these conventional or generalized function terms by which the computer components are described reasonably indicate that Specification discloses conventional component, and describes the component in a manner that indicates that these elements are sufficient well-known that the Specification does not need to describe the particulars of such additional elements to satisfy 35 U.S.C. §112(a). Further, the Specification does not provide additional details that would distinguish the recited components from generic implementation in the combination. These limitations either alone or in combination simply append well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception. It has been recognized by court that receiving, processing, and storing data as well as receiving or transmitting data over a network are a well-understood, routine and conventional activities. Mortg. Grader, Inc. v. First choice Loan Servs. Inc., 811 F.3d 1314 (Fed. Cir. 2016) (generic computer components, such as interface, “network”, and “database,” fail to satisfy the inventive concept requirement); see also TLI Commc’ns, 823 F.3d 607; Elec. Power, 830 F.3d at 1350. There is no indication that the recited claim elements override the conventional use of known features or involve an unconventional arrangement or combination of elements such that the particular combination of generic technology results in anything beyond well-understood, routine, and conventional data gathering and output. Alice, 573 U.S. at 223 (“[T]he mere recitation of a generic computer cannot transform a patent ineligible abstract idea into a patent-eligible invention.”) See also Customedia Techs. LLC v. Dish Network Corp., 951 F.3d 1359, 1366(Fed. Cir. 2020) (“[T]he invocation of ‘already-available computers that are not themselves plausibly asserted to be an advance…amounts to a recitation of what is well-understood, routine, and conventional.”)(quoting SAP Am., Inc. v. InvestPic, LLC, 898F3.d 1161, 1170 (Fed. Cir. 2018)); and buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355(Fed. Cir 2014)(“That a computer receives and sends the information over a network -- with no further specification -- is not even arguably inventive.”).
Thus, claims 1, 12 and 20 are directed to abstract idea without integrating into practical application and / or amount to significantly more than abstract idea.
Dependent claim 2 further describes the counter as amount of downstream bandwidth without further imposing meaningful limitation to the abstract idea.
Dependent claim 3 is directed to time slot description and resetting the counter upon end/beginning of the time slot”. Resetting the counter upon end/beginning of the time slot is a combination of one or more of observation, evaluation, judgement and opinion, and may be performed by human mind alone or with the help of pen and paper. Slot description is providing information without further limiting the claim in such a manner to overcome the abstract idea rejections.
Dependent claim 4 recites “wherein the counter is a first counter corresponding to a first volume of downstream data allocated to the one or more processing resources for the time slot, and the method further includes updating a second counter corresponding to a second volume of upstream data allocated to the one or more processing resources for the time slot based at least on the transaction being of the transaction type”. Claim element describing the counter corresponding to the first volume of downstream data allocated to the processing resource doesn’t impose a limitations on the abstract idea to make the abstract idea patent eligible. Remaining claim elements recite “updating a second counter corresponding to a second volume of upstream data allocated to the one or more processing resources for the time slot based at least on the transaction being of the transaction type”, which is a combination of one or more of observation, evaluation, judgement and opinion, and may be performed by human mind alone or with the help of pen and paper.
Claim 6 recites “receiving decoded packet data generated from one or more packets representing the transaction”, which is directed to information gathering and don’t amount to significantly more. Claim 6 further recites “analyzing the decoded packet data to determine the transaction type”, which is a combination of one or more of observation, evaluation, judgement and opinion, and may be performed by human mind alone or with the help of pen and paper.
Claim 7 is directed to transmission lines of bus interface and neither inventive nor provide improvements to the technology because it merely describes the common computing component. Rest of the claim elements “counter corresponds to the total volume of data transfer allocated to the one or more processing resources for the plurality of send and receive lines”, which merely describes the counter without imposing further meaningful limitations to make the abstract idea patent eligible.
Claim 8 recites transaction type of read operation or atomic operation type, which is well-understood, routine and conventional to one skilled in the art.
Claim 9 describes the bus corresponds to the memory interface that is shared amongst the plurality of processing resources and is neither inventive nor amount to significantly more.
Claim 10 describe the one or more processing resources are of one or more graphics processing units (GPUs) and the one or more buses connect the one or more GPUs to one or more central processing units (CPUs) and is merely describes the generic computing component is neither inventive nor amount to significantly more.
Claim 11 recites “the filtering includes blocking the one or more transactions from reaching the one or more buses based at least on the counter exceeding a threshold value” and is a combination of one or more of observation, evaluation, judgement and opinion, and may be performed by human mind alone or with the help of pen and paper.
Based on similar analysis/ rationales as above, dependent claims 13-19 and 21-23 recite claim elements that are either abstract idea or additional claim elements, that individually or in combination, are either generic computing methods/ components or insignificant pre-post solution activity and neither integrate into practical application nor amount to significantly more.
Therefore, the claim(s) 1-4, 6-23 are rejected under 35 U.S.C. 101 as being directed to judicial exception without integrating into practical application or amount to significantly more.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-12, 14-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mace et al. (US 2012/0011291 A1, hereafter Mace) in view of Krueger (US 2018/0203723 A1, hereafter Krueger).
Mace was cited in the last office action.
As per claim 1, Mace teaches the invention substantially as claimed including a method comprising:
identifying, from a plurality of transaction types ([0034] transaction requests may comprise a plurality of types of transaction requests), a transaction type of a transaction from one or more processing resources of a plurality of processing resources ([0034] master device graphics processor, generate transaction requests, type of graphics processing, types of transaction requests, associated, different type identifier [0089] several master devices 4-0, 4-1, 4-2, transaction requests from the master devices) sharing one or more buses ([0089] fig. 1 master devices 4 slave devices 6 bus system 8 comprises a number of interconnects 10 routing transactions requests between master and slave devices i.e. sharing of bus system);
determining, based on the identified transaction type, a quantity that indicates a data volume, over the one or more busses, of one or more of downstream data or upstream data that is attributable to transmitting the transaction over the one or more buses ([0061] bus system, transferring transaction requests from master device to slave device [0092] amount of bandwidth i.e. data volume per unit time, allocated [0140] graphics processor, performing different kinds of graphics processing requiring different amounts of bandwidth, transaction requests, different kinds of processing, different type identifiers, different bandwidth requirements, types of transaction requests, doesn’t require bandwidth is not allocated a large amount, while a type of transaction request that requires higher rate of bandwidth can receive its required allocation);
updating, by the determined quantity, a counter that tracks for a time slot, a total volume of data transfer over the one or more buses, the total volume attributable ([0033] rate, transaction requests, issued, proportion of bandwidth of the bus system [0140] transaction requests, different kinds, requiring different amount of bandwidth, types of transaction requests, doesn’t require bandwidth is not allocated a large amount, while a type of transaction request that requires higher rate of bandwidth can receive its required allocation) to a plurality of transactions issued by the one or more processing resources issuing the transaction over the one or more buses during the time slot ([0011] rate at which transmission requests are issued from that master device to the bus system [0033] rate at which transaction requests are issued from a master device to a bus system, hence the proportion of bandwidth of the bus system used by the master device [0034] graphics processor, generate, transaction requests at different rates, types of transaction [0140] multiple issue control circuits, controlling rate at which transaction requests of different types are issued), the plurality of transactions including the transaction ([0034] transaction requests, plurality of types of transaction requests) and at least two different transaction types of the plurality of transaction types ([0035] transaction requests, read transaction requests, write transaction requests);
determining, using the counter, that transmitting one or more transactions associated with the one or more processing resources over the one or more buses would exceed a threshold volume of data transfer allocated to the time slot for the one or more processing resources; and
based at least on the determining, filtering, during the time period, the one or more transactions with respect to transmission over the one or more buses ([0008] selectively issue, transaction requests to, bus system [0009] target outstanding transaction value N.x having an integer portion N and a fractional portion x [0010] issue circuit, issue transaction request to bus system, transaction outstanding value [0013] N.x average number of outstanding requests [0014] N: outstanding transaction value, integer, x: fractional portion, target outstanding value, fractional value, select any desired fractional or integer target number [0031] accumulator, update, accumulation value, selected in dependence upon the current number of outstanding transaction requests [0034] transaction requests, plurality of target outstanding transaction, types of transaction requests, control, interface, issue the transaction requests, time averaged number of outstanding transaction requests, type of transaction request, target outstanding transaction value for the type, different type identifiers, control issuing of the transaction request, target outstanding request, type identified by the type identifier [0036] read/write transaction requests, arbiter, current number of outstanding transaction request being equal to N-1 to select one of pending read transaction and write transaction to issue, selection criteria to select one of the pending read and write transaction requests, selection criterion could be favor write over read, at random, round robin).
Mace doesn’t specifically teach a counter that tracks for a time slot, a total volume of data transfer over the one or more buses; determining, using the counter, that transmitting one or more transactions associated with the one or more processing resources over the one or more buses would exceed a threshold volume of data transfer allocated to the time slot for the one or more processing resources; and based at least on the determining, filtering.
Kreuger, however, teaches updating, by the determined quantity, a counter that tracks for a time slot, a total volume of data transfer over the one or more buses ([0184] usage against a limit can be determined, counter, count usage of a resource limited by said limit, counter resets every predetermined period of time [0188] counter, keeps track, counter, transaction forward, incremented, received response, counter, decremented [0189] counter associated with a period of time; counter and limit could be directed towards data transferred over a period of time [0029] resources for handling transactions, interconnects, amount of bandwidth available for handling memory transaction);
determining, using the counter, that transmitting one or more transactions associated with the one or more processing resources over the one or more buses would exceed a threshold volume of data transfer allocated to the time slot for the one or more processing resources ([0029] resources for handling transactions, interconnects i.e. bus, amount of bandwidth available for handling memory transaction [0177] limit, bandwidth limit, memory system component, bandwidth, expressed as an amount of data transferred in, out or in and out of the at least one memory system component over a period of time [0178] current bandwidth usage of said memory system components, exceeds said maximum bandwidth [0184] usage against a limit can be determined, counter, count usage of a resource limited by said limit [0189] counter associated with a period of time; counter and limit could be directed towards data transferred over a period of time [0186] fig. 16 current bandwidth> maximum bandwidth-y 362, set preference =3 364 [0033]); and
based at least on the determining ([0029] resources for handling transactions, interconnects i.e. bus, amount of bandwidth available for handling memory transaction [0177] limit, bandwidth limit, memory system component, bandwidth, expressed as an amount of data transferred in, out or in and out of the at least one memory system component over a period of time [0178] current bandwidth usage of said memory system components, exceeds said maximum bandwidth [0184] usage against a limit can be determined, counter, count usage of a resource limited by said limit [0189] counter associated with a period of time; counter and limit could be directed towards data transferred over a period of time [0186] fig. 16 current bandwidth> maximum bandwidth-y 362, set preference =3 364 [0033]), filtering, during the time period, the one or more transactions with respect to transmission over the one or more buses ([0109] filters, monitor, monitor that counts bytes transferred to memory might filter to only count reads [0110] control allocation of memory system resources such as bandwidth [0178] reduce a preference for access to bandwidth of transaction [0180] transaction routing, current bandwidth usage, higher limit, set preference, transaction, lower importance / preference i.e. set preference dictate allocation of bandwidth to the transaction [0186] fig. 16 362-yes 366 [0188] limit met or exceeded, transaction will not be forwarded [0192] fig. 20 384 386).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to combine the teachings of Mace with the teachings of Krueger of using counter to determine resource usage against a limit for a period of time e.g. counter limit counter and limit could be directed towards data transferred over a period of time, reducing priority of transaction based on transaction exceeding the maximum bandwidth and controlling progression of transaction in dependence on selected transaction priority to improve efficiency and allow a counter that tracks for a time slot, a total volume of data transfer over the one or more buses; determining, using the counter, that transmitting one or more transactions associated with the one or more processing resources over the one or more buses would exceed a threshold volume of data transfer allocated to the time slot for the one or more processing resources; and based at least on the determining, filtering to the method of Mace as in the instant invention. The combination would have been obvious because using counter for the bus bandwidth usage and identifying and controlling progression of transaction with usage exceeding maximum limit as taught by Krueger to the amount of bus bandwidth usage taught by Mace to yield predictable result with reasonable expectation of success and improved efficiency.
As per claim 2, Mace teaches wherein the transaction is an upstream transaction ([0035] write transaction i.e. upstream), and the counter tracks downstream data volume associated with one or more responses to the upstream transaction ([0004] slave device, performs requested service and send a response to the master device i.e. downstream [0091] slave, bandwidth, available for use by respective master device, divided evenly, may require more bandwidth).
Krueger teaches remaining claim elements of counter ([0184] counter, count usage of a resource limited by said limit [0189] counter associated with a period of time; counter and limit could be directed towards data transferred over a period of time).
As per claim 3, Mace teaches wherein the time slot is of a plurality of sequential time slots each corresponding to respective sequential processing cycles ([0019] bus system, clocked, processing cycles [0020] number of processing cycles, [0029] following processing cycles i.e. sequential).
Krueger teaches remaining claim elements of resetting the counter for the one or more processing resources based at least on detecting an end to the time slot and a beginning of a subsequent tile slot in the plurality of sequential time slots ([0184] usage against a limit can be determined, counter, count usage of a resource limited by said limit, counter resets every predetermined period of time).
As per claim 4, Krueger teaches wherein the counter is a first counter corresponding to a first volume of downstream data allocated to the one or more processing resources for the time slot ([0184] counter, count usage of a resource limited by said limit, counter resets every predetermined period of time [0188] counter, keep track of number of outstanding transactions, downstream [0189] counter associated with a period of time; counter and limit could be directed towards data transferred over a period of time), and the method further includes updating a second counter corresponding to a second volume of upstream data allocated to the one or more processing resources for the time slot based at least on the transaction being of the transaction type ([0184] counter, count usage of a resource limited by said limit, counter resets every predetermined period of time [0188] counter, keep track of number of outstanding transactions, response received, counter is decremented i.e. upstream can be separately tracked [0189] counter associated with a period of time; counter and limit could be directed towards data transferred over a period of time [0165] upstream response).
As per claim 5, Mace teaches wherein the transaction is an upstream transaction ([0035] write transaction requests i.e. upstream), the data volume corresponds to bandwidth downstream to the one or more processing resources ([0035] read transaction i.e. downstream transaction [0011] amount of bus bandwidth occupied by transaction requests from a particular master device, dependent upon the rate at which transaction requests are issued), and the filtering includes:
permitting at least one transaction of the one or more transactions to be transmitted over the one or more buses based at least on the at least one transaction corresponding to an upstream write operation ([0034] transaction requests, plurality of target outstanding transaction, types of transaction requests, control, interface, issue the transaction requests, time averaged number of outstanding transaction requests, type of transaction request, target outstanding transaction value for the type, different type identifiers, control issuing of the transaction request, target outstanding request, type identified by the type identifier [0035] transaction request, write transaction requests, manage, write transaction request, separately, separate target outstanding transaction value [0036] issue control, arbiter, select, pending read/write transaction, issue to the bus system).
As per claim 6, Mace teaches receiving the decoded packet data generated from one or more packets representing the transaction ([0138] response to a transaction request, data required); and
analyzing the decoded packet data to determine the transaction type (([0034] transaction request, types).
Kruger teaches remaining claim elements of receiving the decoded packet data generated from one or more packets representing the transaction ([0037] fetch instruction, decoding the fetched instructions, queuing instructions );
analyzing the decoded packet data ([0186] next transaction, analyzed).
As per claim 8, Mace teaches wherein the transaction type indicates a read operation or an atomic operation ([0035] request, comprise, read transaction, write transaction request).
As per claim 9, Mace teaches wherein the one or more buses correspond to a memory interface that is shared amongst the plurality of processing resources (fig. 1 master devices 4-0, 4-1 interconnect 10-0 10-1 bus system 8).
As per claim 10, Mace teaches wherein the one or more processing resources are of one or more graphics processing units (GPUs) ([0140] master device, graphics processor) and the one or more buses connect the one or more GPUs to one or more central processing units (CPUs) (fig. 1 master devices 4, bus 8, external device 11 slave device 6 [0089] external device 11 processor ([0140] master device, graphics processor).
As per claim 11, Krueger teaches wherein the filtering includes blocking at least one transaction of the one or more transactions from reaching the one or more buses based at least on the counter exceeding a threshold volume of data transfer ([0109] filters, monitor, monitor that counts bytes transferred to memory might filter to only count reads [0110] control allocation of memory system resources such as bandwidth [0178] reduce a preference for access to bandwidth of transaction [0180] transaction routing, current bandwidth usage, higher limit, set preference, transaction, lower importance / preference i.e. set preference dictate allocation of bandwidth to the transaction and therefore which transaction is forwarded and which is not [0186] fig. 16 362-yes 366 [0188] limit met or exceeded, transaction will not be forwarded [0192] fig. 20 384 386).
Claim 12 recites system for elements similar to claim 1. Therefore, it is rejected for the same rationale.
As per claim 14, Mace teaches wherein the operations include associating a transaction type of the transaction with the upstream transaction based at least on the analysis ([0034] types of transaction request associated with different type identifier [0141] write transaction i.e. upstream), and the determining the upstream transaction indicates the transfer is based at least on the transaction type ( [0097] fig. 4 issuing of transaction request to the bus system, transaction from the master device, to the bus system and forwarded to further interconnect or slave device [0035] transaction request, read i.e. downstream / write i.e. upstream transaction, manage transaction requests separately [0141] write transaction requests).
Claim 15 recites elements similar to combination of part of claims 5 and 11. Therefore, it is rejected for the same rationale.
Claim 16 recites elements similar to combination of part of claim 4. Therefore, it is rejected for the same rationale.
As per claim 17, Mace teaches the data volume corresponds to one or more downstream transactions to be received, responsive to the upstream transaction ([0019] fig. 19 read/write transaction [0138] response to a transaction request [0034] type of transaction requests requiring the most bandwidth i.e. data size).
Krueger teaches remaining claim elements of data volume in one or more time slots subsequent to the time slot ([0184] usage against a limit can be determined, counter, count usage of a resource limited by said limit, counter resets every predetermined period of time [0188] counter, keeps track, counter, transaction forward, incremented, received response, counter, decremented [0189] counter associated with a period of time; counter and limit could be directed towards data transferred over a period of time ).
As per claim 18, Mace teaches wherein the filtering is based at least on reducing an allocation of data transfer volume to the one or more processing resources for the time slot in response to a determination that incoming traffic from an entity is directed to the one or more processing resources ([0012] measure of the bus bandwidth occupied by the master device, higher the number of outstanding transaction requests, associated with master device; higher the proportion i.e. increasing/decreasing of the bus bandwidth occupied by the master device [0097] allowed to issue a received transaction request).
As per claim 19, Krueger teaches wherein the system is comprised in at least one of:
a control system for an autonomous or semi-autonomous machine;
a perception system for an autonomous or semi-autonomous machine;
a system for performing simulation operations;
a system for performing digital twin operations;
a system for performing light transport simulation;
a system for performing collaborative content creation for 3D assets;
a system for performing deep learning operations;
a system implemented using an edge device;
a system implemented using a robot;
a system for performing conversational Al operations;
a system for generating synthetic data;
a system incorporating one or more virtual machines (VMs) ([0002] software execution environments, applications or virtual machines);
a system implemented at least partially in a data center ([0030] data center server application); or
a system implemented at least partially using cloud computing resources.
Claim 20 recites at least one processor comprising: one or more circuits for elements similar to claim 1. Therefore, it is rejected for the same rationale.
As per claim 21, Mace teaches wherein a second time slot uses the threshold volume of data transfer reduced based at least on the one or more processing resource exceeding the threshold volume of data transfer in the time slot ([0006] master device, generate transaction requests at a higher rate than the other master device, master receives, more time slots than another master device, bus system [0012] higher the number of outstanding transaction requests associated with the master device, the higher the proportion i.e. increasing / decreasing of the bus/slave bandwidth occupied by that master device).
Krueger teaches remaining claim elements of at least on the one or more processing resource exceeding the threshold volume of data transfer in the time slot ([0186] fig. 16 current bandwidth> maximum bandwidth-y 362, set preference =3 364 [0033] [0184] usage against a limit can be determined, counter, count usage of a resource limited by said limit, counter resets every predetermined period of time [0188] counter, keeps track, transaction forward, received response [0189] counter associated with a period of time; counter and limit could be directed towards data transferred over a period of time [0029] resources for handling transactions, interconnects, amount of bandwidth available for handling memory transaction).
As per claim 22, Mace teaches wherein the threshold volume of data transfer is a first threshold volume of downstream data transfer allocated to the one or more processing resources for the time slot ([0011] amount, bus, bandwidth, occupied, transaction requests, master device [0089] fig. 1 master devices 4 [0140] different types of the transaction requests, requiring different amount of bandwidth, a type of transaction request which does not require much bus bandwidth is not unnecessarily allocated a large amount of bandwidth, whilst a type of transaction request from the same master device that requires a higher rate of bandwidth can still receive its required allocation i.e. bandwidth allocation based on transaction type from same master device [0141] fig. 19 read transaction i.e. downstream), and
the one or more circuits are further to enforce a second threshold volume of upstream data transfer allocated to the one or more processing resources for the time slot based at least on the transaction type ([0011] amount, bus, bandwidth, occupied, transaction requests, master device [0089] fig. 1 master devices 4 [0140] different types of the transaction requests, requiring different amount of bandwidth, a type of transaction request which does not require much bus bandwidth is not unnecessarily allocated a large amount of bandwidth, whilst a type of transaction request from the same master device that requires a higher rate of bandwidth can still receive its required allocation i.e. bandwidth allocation based on transaction type from same master device [0141] fig. 19 write transaction i.e. upstream).
Krueger teaches remaining claim elements of threshold volume of data transfer ([0186] minimum / maximum bandwidth limits [0033] [0184] usage against a limit can be determined, counter, count usage of a resource limited by said limit, counter resets every predetermined period of time [0188] counter, keeps track, counter, transaction, received response [0189] counter associated with a period of time; counter and limit could be directed towards data transferred over a period of time [0029] resources for handling transactions, interconnects, amount of bandwidth available for handling memory transaction).
Claim 23 recites elements similar to claim 19. Therefore, it is rejected for the same rationale.
Claims 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mace in view of Krueger, as applied to above claims, and further in view of Gower et al. (US 2008/0034148 A1, hereafter Gower).
Gower was cited in the last office action.
As per claim 7, Mace teaches wherein the one or more processing resources connect to a plurality of send and receive lines of a bus interface corresponding to the one or more buses ([0097] fig. 4 master devices M0, M1, transaction I/F0, I/F1 transaction interface 18 receives a transaction request from the master device and selectively issues the transaction request to the bus system 8, from where the transaction request can be forwarded to a further interconnect 10 or to a slave device 6 coupled to the interconnect 10), and the counter corresponds to the total volume of data transfer allocated to the one or more processing resources for the plurality of send and receive lines ([0011] amount of bus bandwidth, transaction request, rate of transaction being issues to the bus system [0096] allocate fractional amount of bus bandwidth, master device, allocated amount of bandwidth, number of outstanding transaction, master device, maintain an integer number, fractional number N.x [0104] total amount, length of time transaction was pending).
Kruger teaches remaining claim elements of counter corresponds to total volume of data transfer allocated to the one or more processing resources ([0188] counter, keep track of number of outstanding transactions, downstream [0189] counter associated with a period of time; counter and limit could be directed towards data transferred over a period of time )
Mace and Krueger, in combination, do not specifically teach send and receive lines.
Gower, however, teaches send and receive lines ([0071] bus, include, plurality of signal lines, transmitters and/or receivers).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to combine the teachings of Mace and Krueger with the teachings of Gower of bus including plurality of signal transmitters / receivers to improve efficiency and allow bus with send and receive lines as in the instant invention. The combination would have been obvious because supplementing the teachings of bus bandwidth by Mace and Krueger with the teachings of Gower of bus including transmission / receiving lines to yield predictable results of allocating bandwidth to the send / receive lines with reasonable expectation of success and improved efficiency.
Claims 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mace in view of Krueger, as applied to above claims, and further in view of Park et al. (US 2021/0034296 A1, hereafter Park).
As per claim 13, Mace teaches wherein the data volume is included in a header of the transaction and is extracted from the header to determine the quantity used for updating of the counter ( [0033] rate, transaction requests, issued, proportion of bandwidth of the bus system [0140] transaction requests, different kinds, requiring different amount of bandwidth, types of transaction requests, doesn’t require bandwidth is not allocated a large amount, while a type of transaction request that requires higher rate of bandwidth can receive its required allocation).
Mace and Krueger, in combination, do not specifically teach wherein the data volume is included in a header of the transaction and is extracted from the header.
Park, however, teaches wherein the data volume is included in a header of the transaction and is extracted from the header ([0190] read operation, command UPIU, received [0192] header, transaction type, expected data transfer length ).
It would have been obvious to one of ordinary skills in the art before the effective filing date of the invention was made to combine the teachings of Mace and Krueger with the teachings of Park of read operation UPIU command with header comp