Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment/Arguments made in Amendment
Applicant’s arguments, see page 7 in “Applicant Arguments/Remarks Made in an Amendment” dated 12/05/2025, with respect to the 35 U.S.C. 112(b) rejection of claim 3 have been fully considered and are persuasive. The 35 U.S.C. 112(b) rejection of claim 3 has been withdrawn.
Applicant's arguments see page 7 in “Applicant Arguments/Remarks Made in an Amendment” dated 12/05/2025 with respect to the 35 U.S.C. 102 rejection of claim 1 and tis dependent claims have been fully considered but they are not persuasive.
Applicant correctly points out that previous Office Action dated 09/08/2025 includes Examiner making rejections where the prior art from Ikedas has Mold Resin (40) at different points corresponding to instant applications first mold resin and/or Second mold resin, as well as having mold resin (60) corresponding to instant applications first mold resin and/or Second mold resin, where in both of these scenarios it would only be proper that a single mold resin from Ikedas corresponds to a single mold resin from the instant application. Examiner agrees that this oversight may have caused some confusion, however it was obvious that this was a mistake of labeling and as such, applicant has argued both scenarios in an effort to properly argue what was intended by the original rejection.
The intended correspondence was to have mold resin (60) from Ikedas correspond to first mold resin from the instant application and to have mold resin (40) from Ikedas correspond to second mold resin from the instant application. This means that the rejection of claim 1 was mislabeled and the dependent claims were correctly labeled. The arguments that applicant made in the opposite conclusion located towards the middle of page 8 in “Applicant Arguments/Remarks Made in an Amendment” dated 12/05/2025 are unnecessary.
The arguments that applicant made about when equating Ikedas mold resin (60) to instant applications first mold resin and Ikedas mold resin (40) being equated to instant applications second mold resin are made toward the bottom of page 7 in “Applicant Arguments/Remarks Made in an Amendment” dated 12/05/2025, it is improper to say that the mold resins cover the limitations of claim 1. More specifically, applicant argues that claim 1 requires that the second mold resin covers part of the metallic plate, the first semiconductor chip, and another part of the first lead terminal,” and that the mold resin (40) from Ikedas fails cover a lead terminal. Respectfully, Examiner disagrees with this assessment as Ikedas mold resin (40) does at least partially cover the first lead terminal (32), albeit, covering a portion of the underside (not that underside and top side have been decided yet regardless). Looking at figure 10 from Ikedas, it is apparent that mold resin 40 absolutely covers at least a portion of first lead terminal (32).
As this is the totality of the arguments presented in regard to the rejection of claim 1, where mold resin (60) from Ikedas correspond to first mold resin from the instant application and to have mold resin (40) from Ikedas correspond to second mold resin from the instant application, the rejection will be maintained, just with a correction to more fix the confusion.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 9-15, and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by United States Patent by Ikeda et al. (US 10319704 B2; Ikeda).
Regarding Clam 1, Ikeda discloses a semiconductor device (1) comprising:
a heatsink (15);
an insulating resin layer (11), a surface of which includes a first region and a second region different from the first region (the only weight that can be given at this point to the first and second region is that they are on A surface of the insulating resin layer), the insulating resin layer being formed on the heatsink (Fig. 10, where insulating resin layer 11 is formed on heatsink 15);
a metallic plate (12/13) including a first surface and a second surface opposite the first surface, with the first surface in contact with the first region of the surface of the insulating resin layer (Fig. 10, the bottom of the metal plate 12/13 is in contact with the top of insulating resin layer 11, where at least some of the top of insulating resin layer is the first region);
a first semiconductor chip (20/20a/20d//820) adhered to the second surface (Fig. 10, where the semiconductor chip 20 is adhered to the top second surface, opposite the first surface, of metal plate 12);
a first lead terminal (32) connected to the metallic plate (Fig. 10, where the lead terminal is connected to metallic plate 13);
a first mold resin (60) covering a part of the metallic plate and a part of the first lead terminal (Col 8, Lines 57-64); and
a second mold resin (40) formed of a resin material with a different property from that of the first mold resin (Col 8, Lines 60-64, where different resin materials can be used), the second mold resin covering another part of the metallic plate, the first semiconductor chip, and another part of the first lead terminal (Fig. 10, where the second mold resin 40, is disposed above and covering part of the metallic plate 12/13, the first semiconductor chip 20a, and another part of the first lead terminal 32 [The other part would be part of the underside]), wherein:
the first mold resin includes a third surface located in a same plane as that of the first surface of the metallic plate, the third surface extending from an outer peripheral edge of the metallic plate to an outer peripheral edge of the insulating resin layer or outside thereof in plan view (Fig. 10 where the bottom of the metallic plate 12/13 constitute the first surface of the metallic plate and the top of the resin insulating layer 11 and first surface make a plane. The same plane has first mold resin 60 disposed on a side of metallic plate 12/13), and
the third surface is in contact with the second region on the surface of the insulating resin layer (The first region would be the top of insulating resin member 11 where at least part of it includes the metallic plate. The second region can be another part where at least some of it is the top of insulating resin member that includes where first mold resin 60 is deposited over and in contact with the insulating resin member).
Regarding Clam 2, Ikeda discloses the semiconductor device according to claim 1, wherein:
the first mold resin (60) includes a fourth surface opposite the third surface, and
the fourth surface is parallel to the third surface (The fourth surface can be understood to be the horizontal surface that is the top of the vertical portion 34 in Fig. 10, where it is parallel to the third surface below it).
Regarding Clam 3, Ikeda discloses the semiconductor device according to claim 2, wherein the first lead terminal (32) includes:
a first portion (37) extending in parallel to a reference plane including the second surface of the metallic reference plane includes the metallic plate and is between the first portion and the insulating resin layer); and
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Figure 1: Annotated Fig. 10 from Ikeda
a second portion (34) that joins the first portion and the metallic plate together (Fig. 10, where second portion 34 joins extending portion 37 and metallic plate 13, together), and
the fourth surface of the first mold resin 60 is located in a same plane as a surface of the first portion, the surface of the first portion not facing the reference plane (see example below highlighting the third and fourth surfaces).
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Figure 2: Annotated Fig. 10 from Ikeda showing example third and fourth surfaces
Regarding Clam 4, Ikeda discloses the semiconductor device according to claim 3, wherein an entirety of a surface of the second portion (34) of the first lead terminal (32) is covered by the first mold resin (Fig. 10, where the left side surface of the second portion 34 is covered by first mold resin 60).
Regarding Clam 5, Ikeda discloses the semiconductor device according to claim 2, and further wherein:
the first mold resin has a fifth surface connecting the third surface and the fourth surface to each other (Fig. 10, the portion along the surface of the second portion 34 of first lead terminal 32), and
at least a part of the fifth surface is covered by the second mold resin (The second mold resin 40, is in part touching the second portion 34 of first lead terminal 32).
Regarding Clam 6, Ikeda discloses the semiconductor device according to claim 2, and further comprising:
a second lead terminal (35a) extending in parallel to a reference plane including the second surface of the metallic plate, the second lead terminal being spaced apart from the reference plane such that the reference plane is between the second lead terminal and the insulating resin layer (Because the reference plane is between the second lead terminal and the insulating resin layer, the reference plane will be lower than the second lead terminal and spaced apart from it); and
a second semiconductor chip (20d) adhered to a surface of the second lead terminal (The upper surface in Fig. 10), the surface not facing the reference plane (The reference plane is below the second surface and the second surface is facing up), wherein:
the metallic plate is between the second lead terminal and the first portion of the first lead terminal in plan view (Fig. 10, vertically the metallic plate 12/13 is between the second lead terminal 35a and the first portion of the first lead terminal 37), and
the fourth surface of the first mold resin is located in a same plane as the surface of the second lead terminal, to which surface the second semiconductor chip is adhered (by interpreting the fourth surface to be the example below, which still anticipates previous limitations above, the fourth surface fourth surface of the first mold resin is located in a same plane to which surface the second semiconductor chip is adhered).
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Figure 3: Alternate Annotated Fig. 10 from Ikeda showing example fourth surfaces
Regarding Clam 9, Ikeda discloses the semiconductor device according to claim 1, wherein an outer peripheral edge of the first mold resin (60), an outer peripheral edge of the heatsink (15), and an outer peripheral edge of the insulating resin layer (11) are aligned in plan view (looking at Fig. 10, the outer peripheral edges of the above elements are all aligned in parallel using vertical lines).
Regarding Clam 10, Ikeda discloses the semiconductor device according to claim 1, wherein an outer peripheral surface of the metallic plate is covered by the first mold resin (Fig. 10, in plan view either the left edge of metallic plate 13 or the right of metallic plate 12 are both covered by the first mold resin).
Regarding Clam 11, Ikeda discloses the semiconductor device according to claim 1, wherein:
an outer peripheral edge of the second surface of the metallic plate includes a first portion adjacent to the first lead terminal and a second portion on a side opposite the first portion (Fig. 10, see where the outer peripheral edge has a portion at least adjacent to the first lead terminal 32), and
at least a part of the first portion of the outer peripheral edge of the second surface of the metallic plate and at least a part of the second portion
of the outer peripheral edge of the second surface of the metallic plate are covered by the first mold resin (Fig. 11, where at least the first and second portion opposite the first would be covered by the first mold resin 60).
Regarding Clam 12, Ikeda discloses the semiconductor device according to claim 1, wherein an outer peripheral surface of the heatsink is covered by the second mold resin (Fig. 10, While the outer peripheral surface of the heatsink is not directly in contact with the first mold resin, under broadest reasonable interpretation, it is reasonable to see that first mold resin 60 is disposed over and covering heatsink 15).
Regarding Clam 13, Ikeda discloses the semiconductor device according to claim 1, and further wherein an outer peripheral surface of the insulating resin layer is covered by the second mold resin (Fig. 10, where outer peripheral of the top surface of the insulating resin layer 11 is covered by second mold resin [60 – see below])
First and second mold resin can be flipped from claim 1, as all of the limitations in claim 1 for the first and second mold resins are met by both the first and second mold resin. They both cover part of the metallic plate, the semiconductor chip, and the first lead terminal. They both include a third surface located in the same plane as that of the first surface of the metallic plate. For this claim we can understand the first mold resin to be resin 40 and second mold resin to be resin 60.
Regarding Clam 14, Ikeda discloses the semiconductor device according to claim 1, and further wherein:
a plurality of metallic plates (Fig. 5, the upper and lower metallic plate 13) are in contact with a surface of the insulating resin layer, a plurality of first lead terminals are each provided to correspond to a respective metallic plate (Fig. 5, where each metallic plate 13 has its own lead terminal 34), and
the first mold resin (60) is formed as a single piece across the plurality of metallic plates.
Regarding Clam 15, Ikeda discloses the semiconductor device according to claim 14, and further wherein:
a region sandwiched between outer peripheral surfaces of adjacent ones of the plurality of metallic plates is covered by the first mold resin (Because the entirety of all of the metallic plates and all areas between the metallic plates are covered by first mold resin 60, so is the region between the adjacent metallic plates), and
a surface of the first mold resin in the region sandwiched by the outer peripheral surfaces is dented or protruded with respect to the second surface of the metallic plates (See annotated Fig. 5 from Ikeda example below, where a bottom surface of the first mold resin 60, which is deposited over all parts in the figure, is in the region between metallic plates and it creates a protrusion with respect to the second surface of the metallic plate) .
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Figure 4: Annotated Fig. 5 from Ikeda
Regarding Clam 17, Ikeda discloses the semiconductor device according to claim 1, and further wherein the heatsink, the insulating resin layer, the metallic plate, the first semiconductor chip, the first lead terminal, and the first mold resin (40 – see below) are all covered by the second mold resin (60 – see below) except for a part of the heatsink (Fig. 10, where the bottom of heatsink 15 is exposed) and a part of the first lead terminal (The part of the first lead terminal that is instead covered by first mold resin 40)
First and second mold resin can be flipped from claim 1, as all of the limitations in claim 1 for the first and second mold resins are met by both the first and second mold resin. They both cover part of the metallic plate, the semiconductor chip, and the first lead terminal. They both include a third surface located in the same plane as that of the first surface of the metallic plate. For this claim we can understand the first mold resin to be resin 40 and second mold resin to be resin 60.
Regarding Clam 18, Ikeda discloses the semiconductor device according to claim 1, wherein a surface on a side of the heatsink opposite a surface on which the insulating resin layer is formed is exposed on a surface of the semiconductor device (Fig. 10, where the bottom of heat sink 15, the side opposite the insulating resin layer 11, is exposed, from resin or other things).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable as obvious by Ikeda in view of Patent Application Publication by Lee et al. (US 20210272880 A1; Lee).
Regarding claim 16, Ikeda fails to explicitly disclose wherein the thermal conductivity of the first mold resin is higher than that of the second mold resin.
In [0006], however, Lee discloses a semiconductor device with double encapsulation where the mold resins are different and have a different thermal conductivity from each other.
Accordingly, before the effective filling date of the invention, it would have been obvious to one having ordinary skill in the art to select a mold resin with a different thermal conductivity, as shown by Lee in [0006], since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. See MPEP § 2144.07 (citing In re Leshin, 277 F.2d 197 (C.C.P.A. 1960)). One would be motivated to choose a mold resin with different thermal conductivity from the first over other materials depending on manufacturing considerations such as cost of materials or time it takes to process the layer.
Allowable Subject Matter
Claims 7-8, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J HIBBERT whose telephone number is (703)756-1562. The examiner can normally be reached Monday - Friday 8am-5pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL J HIBBERT/Examiner, Art Unit 2899 /ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899