Prosecution Insights
Last updated: September 17, 2026
Application No. 17/872,850

Inactive Structure on SOIC

Non-Final OA §103
Filed
Jul 25, 2022
Priority
Feb 12, 2021 — divisional of 11/756,933
Examiner
GOODWIN, DAVID J
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semicondutor Manufacturing Co. Ltd.
OA Round
3 (Non-Final)
67%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
84%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allowance Rate
551 granted / 819 resolved
-0.7% vs TC avg
Strong +16% interview lift
Without
With
+16.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
53 currently pending
Career history
892
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
60.2%
+20.2% vs TC avg
§102
17.9%
-22.1% vs TC avg
§112
18.6%
-21.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 819 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/10/2026 has been entered. Information Disclosure Statement The information disclosure statement (IDS) submitted on 2/16/2026 was filed after the mailing date of the final rejection on 12/29/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Status Previous action: 1 through 7, 13 through 17 and 20 allowed, 8 through 12 rejected, 18 and 19 objected Present action: 1 through 7, 13 through 20 allowed, 8 through 12 rejected, Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s). Claim(s) 8, 10, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (2018/0138101) in view of Modi (US 2022/0102231) in view of Bowles (US 2008/0246126) Regarding claim 8. Yu teaches: A package device comprising: a first device die (fig 10:70; [para 0019]); a second device die (fig 10:68; [para 0018]) bonded to a first surface of the first device die (fig 10:70; [para 0019]); one or more inactive structures (fig 10:106; [para 0037]) bonded to the first device die (fig 10:70; [para 0019]), wherein a cumulative area of the second device die (fig 13:68; [para 0018]) and the one or more inactive structures (fig 13:106; [para 0037]) is greater than 50% of an area of the first device die (fig 10:70; [para 0019]), wherein a top surface of at least one of the one or more inactive structures (fig 10:106; [para 0037]) is at a height than a top surface of the second device die (fig 10:68; [para 0018]), wherein the one or more inactive structures (fig 10:106; [para 0037]) are electrically isolated (fig 10:104; [para 0037]) from active devices of the first device die (fig 10:70; [para 0019]); Yu does not teach in the embodiment the height top surface of the inactive structure is at a different height than the height of the second device Modi teaches an embodiment comprising: a top surface of at least one of the one or more inactive structures (fig 10a:840; [para 0104]) is at a different height than a top surface of the second device die (fig 10a:830; [para 0103]), PNG media_image1.png 359 530 media_image1.png Greyscale It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the height of the inactive structure and device die to be different to accommodate different prefabricated structures and manufacturing artifacts (paragraph 0105). Yu does not teach a dielectric layer over the first surface of the first die and laterally surrounding the second die. Bowles teaches: a dielectric layer (fig 3:370; [para 0043]) on the first surface of the first device die (fig 3:320; [para 0044]) and laterally surrounding the second device die (fig 3:310; [para 0045]) and the one or more inactive structures (fig 3:367; [para 0043]); and a connector structure (fig 3:380,383,398; [para 0040]) disposed over the dielectric layer (fig 3:370; [para 0043]), the connector structure (fig 3:380,383,398; [para 0040]) electrically coupled to the second device die (fig 3:310; [para 0045]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed in order to provide protection, support, and insulation to the individual components of the package Regarding claim 10. Yu in view of Modi in view of Bowles teaches the package device of claim 8, further Yu teaches: a first inactive structure (fig 10,13:106; [para 0037]) of the one or more inactive structures (fig 10,13:106; [para 0037])has a first sidewall aligned to a sidewall of the first device die (fig 14:70; [para 0055]). Regarding claim 12. Yu in view of Modi in view of Bowles teaches the package device of claim 8, above Yu teaches: the cumulative area of the second device die (fig 10:68; [para 0018]) and the one or more inactive structures (fig 10:106; [para 0037]) is less than 95% of the area of the first device die (fig 10:70; [para 0019]). Differences in area covered will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such area covered are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). Since the applicant has not established the criticality (see next paragraph), and this area covered has been used in similar devices in the art (see, e.g., Yu) it would have been obvious to one of ordinary skill in the art to use these values in the device. CRITICALITY The specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (2018/0138101) in view of Bowles (US 2008/0246126) as applied to claim 8 and further in view of Yu (US 2019/0006263) Regarding claim 9. Yu (101) in view of Modi in view of Bowles teaches the package device of claim 8, above Yu (101) teaches: wherein a first inactive structure of the one or more inactive structures (fig 10:106; [para 0037]) comprises a semiconductor substrate ([para 0038]), a dielectric bonding layer (fig 6b:104; [para 0040]), Yu (101) in view of Modi in view of Bowles does not teach through vias. Yu (263) teaches: a first inactive structure of the one or more inactive structures comprises a semiconductor substrate (fig 27:112; [para 0029]),and through-vias (fig 27:132; [para 0066]) disposed in the semiconductor substrate (fig 27:112; [para 0029]) It would have been obvious to one of ordinary skill in the art before the effective fling date of the claimed invention in order to improve the thermal conductivity of the component and the structure (paragraph 66) Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu (2018/0138101) in view of Modi (US 2022/0102231) in view of Bowles (US 2008/0246126) as applied to claim 8 and further in view of Wang (US 9373605) Regarding claim 11 Yu in view of Modi in view of Bowles teaches the package device of claim 8, above Yu in view of Modi in view of Bowles does not teach a connector of the connector structure is electrically coupled to the first device die through a first inactive structure. Wang teaches a connector of the connector structure (fig 1:120[column 4 lines 5-15])is electrically coupled to the first device die (fig 1:108a[column 2 lines 35-45]) through a first inactive structure (fig 1,2:122[column 4 lines 25-35]) of the one or more inactive structures (fig 1,2:122[column 4 lines 25-35]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to electrically connect through the inactive structure in order to for high functional density with relatively low cost and high performance packages (column 1 lines 15-20). Response to Arguments Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Previous objections to claims 18 and 19 have been overcome by the amendment to claim 18. Allowable Subject Matter Claims 1 through 7 and 13 through 20 are allowed. The following is an examiner’s statement of reasons for allowance: Regarding claim 1, the prior art does not teach in combination with other elements of the claim, a package device comprising: one or more inactive structures bonded to the first device die adjacent the second device die, the one or more inactive structures comprising a semiconductor substrate free of any active devices, wherein the one or more inactive structures comprise a first inactive structure including a tensile film and a second inactive structure free of a tensile film. Regarding claim 13, the prior art does not teach in combination with other elements of the claim, a device comprising: a first device die, the first device die comprising an active device disposed therein; a second device die bonded to the first device die, one or more inactive structures bonded to the first device die, wherein at least one of the one or more inactive structures comprises a tensile film having a tensile stress between 20 MPa and 200 MPa. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /D.J.G/Examiner, Art Unit 2817 /Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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Prosecution Timeline

Jul 25, 2022
Application Filed
May 13, 2025
Non-Final Rejection mailed — §103
Aug 11, 2025
Response Filed
Dec 29, 2025
Final Rejection mailed — §103
Feb 02, 2026
Response after Non-Final Action
Feb 10, 2026
Request for Continued Examination
Feb 19, 2026
Response after Non-Final Action
Sep 11, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
67%
Grant Probability
84%
With Interview (+16.4%)
3y 2m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 819 resolved cases by this examiner. Grant probability derived from career allowance rate.

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