DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment/Argument
Applicant’s arguments, see remarks, filed 08/26/2025, with respect to the rejection(s) of claim(s) 1-11 and 20 under 35 U.S.C. 102 and 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of an updated prior art search.
Claim Objections
Claims 1 and 20 are objected to because of the following informalities: The claimed “a side region” is written twice in the claimed language and is grammatically incorrect. This is believed to be a typographical error. Please amend claims 1 and 20 for clarity and grammatical correctness. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-4 and 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US-20060051954-A1 – hereinafter Lin) in view of Hiatt et al. (US-20060001141-A1 – hereinafter Hiatt).
Regarding claim 1, Lin teaches a semiconductor device (Fig.5A; ¶0044), comprising:
a package substrate (Fig.4L 2; ¶0042) comprising one or more layers (Fig.4L 20; ¶0034);
a plurality of posts (Fig.5A 1; ¶0044), each post comprising a proximal end, a pillar portion (Fig.4L 53; ¶0042), a distal end (the posts 1 comprise these features), and a solder anchor portion (Fig.4L 55; ¶0042), each post (1) being coupled at the proximal end to a conductive point on a layer (Fig.4L 25; ¶0035) among the one or more layers (20) of the package substrate (2), each pillar portion (53) having a length extending along its axis between the proximal end and the distal end and a width at the distal end that is orthogonal to the length (Fig.4L geometry of post 1), each solder anchor portion (55) being coupled to the distal end of a corresponding post, wherein each solder anchor portion (55) has a width that is larger than the width of the distal end of the pillar portion (53) to which it is coupled (55 is wider than 53); and
a plurality of solder balls (Fig.4L 17; ¶0041), each solder ball (17) being disposed on and around the solder anchor portion (55) of a corresponding post (1), one or more solder balls (130) among the plurality of solder balls (17) and corresponding one or more posts (1) among the plurality of posts (1) forming conductive interconnects between corresponding conductive points on the package substrate (2) and corresponding contact points on a printed circuit board ("PCB") device (Fig.5A 3; ¶0044);
wherein the solder anchor portion (55) comprises a top region, a side region, and a bottom region, and a side region, a solder ball (17) of the plurality of solder balls (17) interfaces with the bottom region.
Lin does not teach wherein a solder ball of the plurality of solder balls interfaces with the top region and the side region.
Hiatt teaches an embodiment (Fig.9; ¶0050) with a solder anchor portion (Fig.9 39; ¶0050) having a top region, a bottom region and a side region with a solder ball (Fig.9 42; ¶0047) that interfaces with the top region, bottom region and side region.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the solder ball of Lin (17 of Lin) interface with the top, bottom and side regions of the solder anchor portion (55 of Lin) of Lin as taught by Hiatt (Fig.9 of Hiatt) to arrive at the claimed invention. A practitioner of ordinary skill would have been motivated to make this modification for the benefit of improving the mechanical integrity of the solder connection (¶0005 of Lin).
Regarding claim 2, the aforementioned combination of Lin in view of Hiatt from claim 1 teaches the semiconductor device of claim 1, wherein the conductive points (25 of Lin) on the package substrate (2 of Lin) comprise a plurality of conductive pads (Fig.4L 11; ¶0026 of Lin), each conductive pad (11 of Lin) being coupled to the proximal end of a corresponding post among the plurality of posts (1 of Lin).
Regarding claim 3, the aforementioned combination of Lin in view of Hiatt from claim 2 teaches the semiconductor device of claim 2, wherein the plurality of posts (1 of Lin) is formed on the plurality of conductive pads (11 of Lin) using semiconductor package manufacturing processes comprising at least one of one or more photoresist film application processes, one or more image transfer processes, one or more pattern transfer processes, one or more material plating processes, one or more photoresist film stripping processes, or one or more reflow processes (Lin discloses electroplating ¶0006).
Regarding claim 4, the aforementioned combination of Lin in view of Hiatt from claim 3 teaches the semiconductor device of claim 3, wherein the plurality of posts (1 of Lin) is formed on the package substrate (2 of Lin) extending from a bottom layer of the package substrate (Fig.5A 2 of Lin), such that the plurality of solder balls (17 of Lin) is formed by forming a solder shell (¶0016 of Lin) around the solder anchor portion (55 of Lin) of each post (1 of Lin).
Regarding claim 7, the aforementioned combination of Lin in view of Hiatt from claim 1 teaches the semiconductor device of claim 1, wherein the solder anchor portion (55 of Lin) has a shape comprising one of a sphere, an ellipsoid, a hemisphere, a cylinder, a cone, a truncated cone, a triangular prism, a cube, a rectangular prism, a pentagonal prism, a hexagonal prism, an octagonal prism, or other three-dimensional polygon (Fig.4L of Lin depicts a rectangular shape for 55).
Regarding claim 8, the aforementioned combination of Lin in view of Hiatt from claim 1 teaches the semiconductor device of claim 1, wherein one or more posts among the plurality of posts (1 of Lin) are formed through two or more substrate layers (Fig.4L 20 of Lin has multiple layers) among the one or more layers of the package substrate (2 of Lin), wherein a cross-section of each of the one or more posts (1 of Lin) is continuous as it extends through the two or more substrate layers (20 of Lin), without geometrical transitions in the cross-section of each post that exceeds a proportion of a width of the cross-section as each post extends between adjacent substrate layers among the two or more substrate layers (20 of Lin).
Regarding claim 9, the aforementioned combination of Lin in view of Hiatt from claim 8 teaches the semiconductor device of claim 8, wherein the cross-section of each of the one or more posts is one of the same within a threshold amount of deviation of 10%, continuously expanding, or continuously contracting as it extends through the two or more substrate layers (Fig.5A of Lin posts 1 are uniform).
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Hiatt, and further in view of Fjelstad. (US-8148199-B2).
Regarding claim 5, the aforementioned combination of Lin in view of Hiatt from claim 2 teaches the semiconductor device of claim 2.
Lin does not teach wherein the plurality of posts is formed on the plurality of conductive pads using wire bonding processes.
Fjelstad teaches wire bonding processes being a common way to connect semiconductor components such as die bond pads (col 1 line 53-55 of Fjelstad).
It would be obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use a wire bonding process (col.1 line 53-55 of Fjelstad) to connect the posts (1 of Lin) and conductive pads (11 of Lin) as this is a common practice in the art as proven by the teaching reference.
Regarding claim 6, the aforementioned combination of Lin in view of Hiatt, and further in view of Fjelstad from claim 5 teaches the semiconductor device of claim 5, wherein the plurality of posts (1 of Lin) is formed on the package substrate (2 of Lin) extending from a bottom layer of the package substrate (Fig.5A 2 of Lin), such that the plurality of solder balls (17 of Lin) is formed by applying molten solder material (¶0016 of Lin) to the solder anchor portion (55 of Lin) of each post (1 of Lin).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Hiatt, and further in view of Jones et al. (US-20220208670-A1 – hereinafter Jones).
Regarding claim 10, the aforementioned combination of Lin in view of Hiatt from claim 1 teaches the semiconductor device of claim 1.
Lin does not teach wherein two or more posts among the plurality of posts are connected to each other via one or more cross bars.
Jones teaches a device (Fig.5C 200'"; ¶0075 of Jones) with multiple conductive posts (Fig.5C 595; ¶0075 of Jones) connected via a cross bar (Fig.5C 591; ¶0075 of Jones).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to add the cross bar of Jones (591 of Jones) to the posts taught by Lin (1 of Lin) to arrive at the claimed invention. A practitioner would be motivated to make this modification for additional of signal redistribution between the conductive posts.
Claim(s) 11 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Linin view of Hiatt, and further in view of Yeruva et al. (US-20180122762-A1 – hereinafter Yeruva).
Regarding claim 11, the aforementioned combination of Lin in view of Hiatt from claim 1 teaches the semiconductor device of claim 1.
Lin does not teach wherein the length of the pillar portion of each of the plurality of posts is different from that of one or more adjacent posts, wherein the length of the pillar portion of each post is based on heights of corresponding contact points on the PCB and is not solely based on warpage of the package substrate, wherein the heights of the corresponding contact points on the PCB are determined based on a scan of a surface of the PCB.
Yeruva teaches a semiconductor device assembly (Fig.2B 100; ¶0014 of Yeruva) having a die (Fig.2A 111; ¶0015 of Yeruva) with conductive structures (Fig.2B 115a and 115b; ¶0016 of Yeruva) of different lengths for matching a corresponding substrate (Fig.2A 130 ¶0016 of Yeruva).
It would be obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use a conductive structure arrangement taught by Yeruva (100 of Yeruva) with conductive structures of different lengths on the structure taught by Lin (Fig.4L of Lin) to arrive at the claimed invention. A practitioner would use this arrangement to complement the varying profile of an irregular substrate if needed (¶0011 of Yeruva).
Regarding claim 20, Lin teaches a semiconductor device (Fig.5A; ¶0044), comprising:
a package substrate (Fig.4L 2; ¶0042) comprising one or more bottom layers (Fig.4L 20; ¶0034);
a plurality of posts (Fig.5A 1; ¶0044), each post comprising a proximal end, a pillar portion (Fig.4L 53; ¶0042), and a distal end, each post (1) being coupled at the proximal end to a conductive point (Fig.4L 25; ¶0035) on a bottom layer among the one or more bottom layers of the package substrate (Fig.5A 2), each pillar portion (53) having a length extending along its axis between the proximal end and the distal end and a width at a distal end of thereof that is orthogonal to the length (cylinder geometry);
a solder anchor portion (Fig.5A 55; ¶0042), each solder anchor portion (55) being coupled to the distal end of a corresponding post among the plurality of posts (1), wherein each solder anchor portion (55) has a width that is larger than the width of the distal end of the pillar portion to which it is coupled (Fig.4L 55 is wider than 55); and
a plurality of solder balls (Fig.4L 17), each solder ball (17) being disposed on and around the solder anchor portion (55) of a corresponding post (1), one or more solder balls (17) among the plurality of solder balls (17) and corresponding one or more posts among the plurality of posts (1) forming conductive interconnects between corresponding conductive points on the package substrate (2) and corresponding contact points on a printed circuit board ("PCB") device (Fig.5A 3; ¶0044);
wherein the solder anchor portion (55) comprises a top region, a side region, and a bottom region, and a side region, a solder ball (17) of the plurality of solder balls (17) interfaces with the bottom region.
Lin does not teach wherein a solder ball of the plurality of solder balls interfaces with the top region and the side region; and
wherein the length of the pillar portion of each of the plurality of posts is different from that of one or more adjacent posts, wherein the length of the pillar portion of each post is based on heights of corresponding contact points on the PCB and is not solely based on warpage of the package substrate, wherein the heights of the corresponding contact points on the PCB are determined based on a scan of a surface of the PCB.
Hiatt teaches an embodiment (Fig.9; ¶0050) with a solder anchor portion (Fig.9 39; ¶0050) having a top region, a bottom region and a side region with a solder ball (Fig.9 42; ¶0047) that interfaces with the top region, bottom region and side region.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the solder ball of Lin (17 of Lin) interface with the top, bottom and side regions of the solder anchor portion (55 of Lin) of Lin as taught by Hiatt (Fig.9 of Hiatt). A practitioner of ordinary skill would have been motivated to make this modification for the benefit of improving the mechanical integrity of the solder connection (¶0005 of Lin).
Lin does not teach wherein the length of the pillar portion of each of the plurality of posts is different from that of one or more adjacent posts, wherein the length of the pillar portion of each post is based on heights of corresponding contact points on the PCB and is not solely based on warpage of the package substrate, wherein the heights of the corresponding contact points on the PCB are determined based on a scan of a surface of the PCB.
Yeruva teaches a semiconductor device assembly (Fig.2B 100; ¶0014 of Yeruva) having a die (Fig.2A 111; ¶0015 of Yeruva) with conductive structures (Fig.2B 115a and 115b; ¶0016 of Yeruva) of different lengths for matching a corresponding substrate (Fig.2A 130 ¶0016 of Yeruva).
It would be obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use a conductive structure arrangement taught by Yeruva (100 of Yeruva) with conductive structures of different lengths on the structure taught by Lin (Fig.4L of Lin) to arrive at the claimed invention. A practitioner would use this arrangement to complement the varying profile of an irregular substrate if needed (¶0011 of Yeruva).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/T.J.K./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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