DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/8/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9, 11, 13 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 9704818 B1, newly cited), and further in view of Huang et al. (US 10916510 B1, of record).
Re Claim 9, Lin teaches a semiconductor device (Fig. 30) comprising:
a semiconductor substrate (101, Fig. 30, Col 4, lines 4-10) having a top surface (101a, Fig. 30); and
an interconnection structure (104a+104b+106, Fig. 30, Col 5, lines 43-45 and 58-60, and Col 6, lines 60-67) electrically coupled to the semiconductor substrate at the top surface (see Fig. 30), the interconnection structure including:
an inner metallic pillar (marked “104b inner pillar” in annotated Fig. 30 below),
a continuous metallic bridging layer (marked “104b bridge layer” in annotated Fig. 30 below) over and connected with the inner metallic pillar (“104b inner pillar”), wherein the continuous metallic bridging layer has a planar upper surface (planar upper surface of “104b bridge layer”) parallel to the top surface of the semiconductor substrate (101a, Fig. 30), and
a dielectric liner (104a, Fig. 30, which can be a polymer, Col 5, lines 43-45),
a seed layer (106, Fig. 30, Col 6, lines 60-67 and Col 7, lines 1-4) formed over the dielectric liner (104a, Fig. 30) such that the seed layer is positioned between the dielectric liner (104a) and the inner metallic pillar (“104b inner pillar”, see annotated Fig. 30 below), and between the dielectric liner (104a) and the continuous metallic bridging layer (“104b bridge layer”, see annotated Fig. 30 below).
Lin shows a vertical cross-sectional view of the interconnection structure (104a+104b+106) in Fig. 30 but does not show a top view. Lin teaches that the non-conducting dielectric structure 104a can be patterned into pillars, and hence does not explicitly teach the following:
an outer metallic shell surrounding and spaced from the inner metallic pillar,
a continuous metallic bridging layer over and connected with the outer metallic shell
a dielectric liner between the inner metallic pillar and the outer metallic shell.
a seed layer between the dielectric liner and the outer metallic shell.
Related art, Huang teaches an interconnection structure (401, Fig. 1, Col. 5, lines 35-41) with patterned conductive (403+407, Col. 8, lines 28-32) structures and non-conductive supporting layers (405, Col. 8, lines 28-44) embedded within. The interconnection structure (401) can have various horizontal cross-sectional shapes and structures (Figs. 4-6, Col. 10, lines 1-49). For example, the non-conductive supporting layers (405, Fig. 4) can be rectangular pillars (Fig. 4) similar to the one shown by Lin (see Fig. 30 of Lin), or the non-conductive layers (405, Fig. 6, Huang) can be concentric (Fig. 6, Huang) with the conductive layers (407, Fig. 6, Huang).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the interconnection structure of Lin according to the teachings of Huang, such that the conductive and dielectric layers of the interconnection structure are concentric. Huang teaches that the interconnection structure can have various horizontal cross-sectional shapes and structures, where the non-conductive supporting layers can be rectangular pillars, similar to the one shown by Lin, or the non-conductive/dielectric layers can be concentric with the conductive layers. One of ordinary skill would realize that these are art-recognized alternate interconnection structures for bonding two substrates, and one of ordinary skill in the art would have found it obvious to substitute the concentric structure instead of pillar-shaped structure. The use of a known interconnection structure for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Thus, Lin modified by Huang teaches an interconnection structure with:
an outer metallic shell (marked “104b outer shell” in annotated Fig. 30 of Lin below) surrounding and spaced from the inner metallic pillar (“104b inner pillar”, see annotated Fig. 30 of Lin below),
a continuous metallic bridging layer (marked “104b bridge layer” in annotated Fig. 30 of Lin below) over and connected with the outer metallic shell (“104b outer shell”),
a dielectric liner (104a, Fig. 30, Lin) between the inner metallic pillar (“104b inner pillar”) and the outer metallic shell (“104b outer shell”), and
a seed layer (106, Fig. 30) between the dielectric liner (104a) and the outer metallic shell (“104b outer shell”), and between the dielectric liner (104a) and the continuous metallic bridging layer (“104b bridge layer”).
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Re Claim 11, Lin modified by Huang teaches the semiconductor device of claim 9, wherein the inner metallic pillar (“104b inner pillar”, see annotated Fig. 30 of Lin above) and the outer metallic shell (“104b outer shell” in annotated Fig. 30 of Lin below) extend from portion of the seed layer (106, Fig. 30, Lin) formed over a bond pad (102, Fig. 30, Col 4, lines 4-10) on the semiconductor substrate (101).
Re Claim 13, Lin modified by Huang teaches the semiconductor device of claim 9, wherein the inner metallic pillar, the outer metallic shell, and the continuous metallic bridging layer include a copper material (104b can be made of copper, Fig. 30, Col 5, lines 58-60, Lin).
Re Claim 15, Lin modified by Huang teaches the semiconductor device of claim 9, wherein the dielectric liner (104a, Fig. 30, Lin) includes a material with a greater flexibility than a flexibility of a material included by the inner metallic pillar and/or the outer metallic shell (104a can be made of polymer, Col 5, lines 43-45, while material for inner metallic pillar 104b can be copper, Col 5, lines 58-60, where flexibility of polymer is greater than the flexibility of copper).
Re Claim 16, Lin modified by Huang teaches the semiconductor device of claim 9, wherein the dielectric liner includes a polymer material (104a can be made of polymer, Col 5, lines 43-45, Lin).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 9704818 B1, newly cited) and Huang et al. (US 10916510 B1, of record), and further in view of Shih et al. (US 2016/0358868 A1, newly cited).
Re Claim 10, Lin modified by Huang teaches the semiconductor device of claim 9, wherein the outer metallic shell (“104b outer shell”, annotated Fig. 30 above, Lin) is a first outer metallic shell and the dielectric liner (104a, Fig. 30 Lin) is a first dielectric liner, but does not disclose that the interconnection structure further includes:
a second outer metallic shell surrounding and spaced from the first outer metallic shell, and
a second dielectric liner between the first outer metallic shell and the second outer metallic shell, and wherein the continuous metallic bridging layer is further over and connected with the second outer metallic shell.
Related art Shih discloses similar stress relieving polymer structures 142b (Figs. 1-2C, para [0038]) embedded within the interconnection structure 140 (Figs. 1-2C, para [0038]). The stress relieving structure 142b can have an annular shape comprising of one concentric cylinder (Fig. 1, para [0040]) or can be made of multiple concentric polymer cylinders alternating with the conductive cylinders (Fig. 2C, para [0040]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the interconnection structure of Lin modified by Huang, such that the interconnection structure comprises of multiple concentric cylinders of alternating conducting metallic layers and non-conducting polymer layers as shown by Shih, thus satisfying the claim limitation above. Shih teaches that the stress relieving structure can be made of a single concentric cylinder (also shown by Lin modified by Huang) or can comprise of multiple concentric cylinder (Fig. 2C, Shih). One of ordinary skill would realize that these are art-recognized alternate stress relieving structures embedded within an interconnection structure, and one of ordinary skill in the art would have found it obvious to substitute multiple concentric alternating rings of conducting and non-conducting cylinders instead of only one pair. The use of a known stress relieving structure for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 9704818 B1, newly cited) and Huang et al. (US 10916510 B1, of record), and further in view of Kuo et al. (US 2016/0300808 A1, of record).
Re Claim 17, Lin modified by Huang teaches the semiconductor device of claim 9 but does not disclose that the interconnection structure (104a+104b+106, Fig. 30, Lin) further includes a solder material over the continuous metallic bridging layer (“104b bridge layer”, see annotated Fig. 30 of Lin above).
Related art Kuo teaches a similar interconnection structure (36+114, Fig. 8, Kuo) between two substrate devices (10 and 40, Fig. 8), where the interconnection structure further includes a solder material (54, Fig. 8, para [0022], Kuo).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to include a solder material over the “104 bridge layer” of the interconnection structure of Lin modified by Huang (see annotated Fig. 30-v2 below) as shown by Kuo, because when the interconnection structure is being connected to a second device substrate, the solder material provides reduced thermal stress in the bonded structure while providing reliable electrical connection between the two connected devices.
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Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 9704818 B1, newly cited), Huang et al. (US 10916510 B1, of record) and Kuo et al. (US 2016/0300808 A1, of record) as applied to claim 17 above, and further in view of Chiu et al. (US 2016/0307864 A1, newly cited)
Re Claim 18, Lin modified by Huang and Kuo teaches the semiconductor device of claim 17 but does not disclose that the interconnection structure further includes a metallic interconnection layer between the solder material and the continuous metallic bridging layer.
Kuo discloses that a nickel layer can be formed (para [0020]) between the connection structure (36+114, Fig. 8) and the solder layer (54, Fig. 8).
Furthermore, Chiu discloses that a nickel layer (1045/1055, Fig. 12a, para [0070]) between copper pillars (1043/1053, Fig. 12a, para [0070]) and solder layers (1047/1057, Fig. 12a, para [0070]) is useful because the nickel layer acts as a barrier layer and stops copper diffusion from the copper pillars to the solder layers (para [0070]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to include a metallic interconnection layer like a nickel layer between the solder layer and the “104b bridge layer” of Lin modified by Huang and Kuo, as taught by Kuo and Chiu, because the nickel layer acts as a barrier layer and stops copper diffusion from the 104b layer (Fig. 30, Lin, which is made of copper, Col 5, lines 58-60) to the solder layer (see annotated Fig. 30-v2 above in claim 17).
Re Claim 19 Lin modified by Huang, Kuo and Chiu teaches the semiconductor device of claim 18, wherein the metallic interconnection layer includes a nickel material (the metal interconnection layer is nickel layer, see claim 18 above).
Allowable Subject Matter
Claims 1 and 3-8 are allowed.
Claim 12 is objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 1 is allowable for following reasons. Most of the limitations of claim 1 are taught by Kuo (US 2016/0300808 A1, of record), and further in view of Huang (US 10916510 B1, of record), as stated in the office action dated 1/9/2026. The amended claim 1 further includes the limitation wherein “the interconnection structure is formed on a first bond pad at a surface of the first semiconductor die” and “at least a portion of a top surface of the bond pad is exposed peripheral to the outer metallic shell”. Kuo teaches that the interconnection structure (36+114, Fig. 8) is formed on a first bond pad (16, Fig. 8, para [0018], Kuo) of the first semiconductor die (10, Kuo) but does not teach that “at least a portion of a top surface of the bond pad is exposed peripheral to the outer metallic shell”. Lin et al. (US 9704818 B1, newly cited) in view of Huang (US 10916510 B1, of record) also teaches most of the limitations of claim 1 (see claim 9 rejection above), including an interconnection structure (104a+104b+106, Fig. 30, Lin) formed on a first bond pad (102, Fig. 30, Lin) on a semiconductor substrate (101, Fig. 30), but also fails to teach that “at least a portion of a top surface of the bond pad is exposed peripheral to the outer metallic shell”. This limitation is neither anticipated nor made obvious by the prior art of record in the Examiner’s opinion, when viewed in the context of the whole claim. Claims 3-8 depend from claim 1 and are allowable for at least the reasons above.
Claim 12 is allowable for at least the reasons of, “wherein the inner metallic pillar and the outer metallic shell extend a same distance from the bond pad”. Lin et al. (US 9704818 B1, newly cited) as applied to claim 11 above discloses different heights for the inner metallic pillar and the outer metallic shell (see Fig. 30) and hence does not teach the above limitation. This limitation is neither anticipated nor made obvious by the prior art of record in the Examiner’s opinion, when taken in context of the independent claim 9 and intervening dependent claim 11, as a whole.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claim 9 has been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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