DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Prior objection to drawings in related to claim 10 is withdrawn in view of applicant’s argument filed on 10/6/2025.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-13 and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo (US 2016/0300808 A1, of record), and further in view of Huang (US 10916510 B1, of record).
Re Claim 1, Kuo teaches a semiconductor device (Fig. 8) assembly comprising:
a first semiconductor die (10, Fig. 8, para [0018]);
a second semiconductor die (40, Fig. 8, para [0021]); and
an interconnection structure (36+114, Fig. 8, para [0020]) directly electrically coupling the first and the second semiconductor dies (see Fig. 8), the interconnection structure including:
an inner metallic pillar (marked “inner-pillar” in annotated Fig. 8 below),
a continuous metallic bridging layer (marked “bridge-layer” in annotated Fig. 8 below) over and connected with the inner metallic pillar (“inner-pillar”), wherein the continuous metallic bridging layer has a first surface (top surface of “bridge-layer”) and a second surface (bottom surface of “bridge-layer”) opposite the first surface, wherein the first surface (top surface of “bridge-layer”) faces the inner metallic pillar (“inner-pillar”), and wherein the second surface (bottom surface of “bridge-layer”) is planar and parallel to a top surface of the first semiconductor die (top surface of 10), and
a dielectric liner (114, Fig. 8, paras [0020] and [0025]).
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Kuo shows a vertical cross-sectional view of the interconnection structure (36+114) in Fig. 8 but does not show a top view. Kuo teaches that the dielectric structure 114 can be patterned into numerous layers (para [0023]) or textures (para [0025]) surrounded by conductive layers 36, and their cross-sections can be circle, rectangle or trapezoid (para [0025]). However, Kuo does not show a top-view, and hence does not explicitly teach the following:
an outer metallic shell surrounding and spaced from the inner metallic pillar,
a continuous metallic bridging layer over and connected with the outer metallic shell
a dielectric liner between the inner metallic pillar and the outer metallic shell.
Related art, Huang teaches an interconnection structure (401, Fig. 1, Col. 5, lines 35-41) with patterned conductive (403+407, Col. 8, lines 28-32) structures and non-conductive supporting layers (405, Col. 8, lines 28-44) embedded within. The interconnection structure (401) can have various horizontal cross-sectional shapes and structures (Figs. 4-6, Col. 10, lines 1-49). For example, the non-conductive supporting layers (405, Fig. 4) can be rectangular pillars (Fig. 4) similar to the one shown by Kuo (see Fig. 8 of Kuo), or the non-conductive layers (405, Fig. 6, Huang) can be concentric (Fig. 6, Huang) with the conductive layers (407, Fig. 6, Huang). Thus, Huang teaches an interconnection structure (401, Fig. 1, Col. 5, lines 35-41) with:
an outer metallic shell (marked “407-outer” in annotated Figs. 1 and 6 below, Col. 8, lines 28-32) surrounding and spaced from the inner metallic pillar (marked “407-inner” in annotated Figs. 1 and 6 below),
a continuous metallic bridging layer (marked “407-bridge” in annotated Figs. 1 and 6 below, Col. 8, lines 28-32) over and connected with the outer metallic shell (“407-outer”), and
a dielectric liner (405, Figs. 1 and 6, Col. 8, lines 28-44) between the inner metallic pillar (“407-inner”) and the outer metallic shell (“407-outer”).
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It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the interconnection structure of Kuo according to the teachings of Huang, such that the conductive and dielectric layers of the interconnection structure are concentric. Huang teaches that the interconnection structure can have various horizontal cross-sectional shapes and structures, where the non-conductive supporting layers can be rectangular pillars, similar to the one shown by Kuo, or the non-conductive/dielectric layers can be concentric with the conductive layers. One of ordinary skill would realize that these are art-recognized alternate interconnection structures for bonding two substrates, and one of ordinary skill in the art would have found it obvious to substitute the concentric structure instead of pillar-shaped structure. The use of a known interconnection structure for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Re Claim 2, Kuo modified by Huang teaches the semiconductor device assembly of claim 1, wherein the interconnection structure (36+114, Fig. 8, Kuo) is formed on a first bond pad (16, Fig. 8, para [0018], Kuo) of the first semiconductor die (10, Kuo).
Re Claim 3, Kuo modified by Huang teaches the semiconductor device assembly of claim 1, wherein the continuous metallic bridging layer (“bridge-layer”, Fig. 8, Kuo) carries a solder material (54, Fig. 8, para [0022], Kuo).
Re Claim 4, Kuo modified by Huang teaches the semiconductor device assembly of claim 3, wherein the solder material (54, Fig. 8, Kuo) physically and electrically couples the second semiconductor die (40, Fig. 8, Kuo) to the interconnection structure (36+114, Fig. 8, Kuo).
Re Claim 5, Kuo modified by Huang teaches the semiconductor device assembly of claim 1, wherein the inner metallic pillar, the outer metallic shell, and the continuous metallic bridging layer are a monolithic metallic material (all the conductive metallic parts, 36, of the interconnection structure, 36+114, of Kuo are made of one monolithic structure, see Fig. 8 of Kuo).
Re Claim 6, Kuo modified by Huang teaches the semiconductor device assembly of claim 1, wherein the inner metallic pillar (“407-inner”, see annotated Fig. 6 of Huang above) has a cylindrical shape (see Fig. 6 of Huang), wherein the outer metallic shell (“407-outer”, see annotated Fig. 6 of Huang above) has an annular column shape (see Fig. 6 of Huang), and wherein the dielectric liner (405+409, Huang) has an annular column shape (see Fig. 6 of Huang).
Re Claim 7, Kuo modified by Huang teaches the semiconductor device assembly of claim 6, wherein an exterior surface of the dielectric liner (outer surface of 405+409, Huang) is coincident (see Fig. 6, Huang) with an interior surface of the outer metallic shell (inner surface of “407-outer”, Huang).
Re Claim 8, Kuo modified by Huang teaches the semiconductor device assembly of claim 6, wherein an exterior surface of the inner metallic pillar (outer surface of “407-inner”, Huang) is coincident (see Fig. 6, Huang) with an interior surface of the dielectric liner (inner surface of 405+409, Huang).
Re Claim 9, Kuo teaches a semiconductor device (Fig. 8) comprising:
a semiconductor substrate (10, Fig. 8, para [0018]) having a top surface (top surface of 10); and
an interconnection structure (36+114, Fig. 8, para [0020]) electrically coupled to the semiconductor substrate at the top surface (see Fig. 8), the interconnection structure including:
an inner metallic pillar (marked “inner-pillar” in annotated Fig. 8 above),
a continuous metallic bridging layer (marked “bridge-layer” in annotated Fig. 8 above) over and connected with the inner metallic pillar (“inner-pillar”), wherein the continuous metallic bridging layer has a planar upper surface (bottom surface of “bridge-layer”) parallel to the top surface of the semiconductor substrate (top surface of 10), and
a dielectric liner (114, Fig. 8, paras [0020] and [0025]).
Kuo shows a vertical cross-sectional view of the interconnection structure (36+114) in Fig. 8 but does not show a top view. Kuo teaches that the dielectric structure 114 can be patterned into numerous layers (para [0023]) or textures (para [0025]) surrounded by conductive layers 36, and their cross-sections can be circle, rectangle or trapezoid (para [0025]). However, Kuo does not show a top-view, and hence does not explicitly teach the following:
an outer metallic shell surrounding and spaced from the inner metallic pillar,
a continuous metallic bridging layer over and connected with the outer metallic shell
a dielectric liner between the inner metallic pillar and the outer metallic shell.
Related art, Huang teaches an interconnection structure (401, Fig. 1, Col. 5, lines 35-41) with patterned conductive (403+407, Col. 8, lines 28-32) structures and non-conductive supporting layers (405, Col. 8, lines 28-44) embedded within. The interconnection structure (401) can have various horizontal cross-sectional shapes and structures (Figs. 4-6, Col. 10, lines 1-49). For example, the non-conductive supporting layers (405, Fig. 4) can be rectangular pillars (Fig. 4) similar to the one shown by Kuo (see Fig. 8 of Kuo), or the non-conductive layers (405, Fig. 6, Huang) can be concentric (Fig. 6, Huang) with the conductive layers (407, Fig. 6, Huang). Thus, Huang teaches an interconnection structure (401, Fig. 1, Col. 5, lines 35-41) with:
an outer metallic shell (marked “407-outer” in annotated Figs. 1 and 6 above, Col. 8, lines 28-32) surrounding and spaced from the inner metallic pillar (marked “407-inner” in annotated Figs. 1 and 6 above),
a continuous metallic bridging layer (marked “407-bridge” in annotated Figs. 1 and 6 above, Col. 8, lines 28-32) over and connected with the outer metallic shell (“407-outer”), and
a dielectric liner (405, Figs. 1 and 6, Col. 8, lines 28-44) between the inner metallic pillar (“407-inner”) and the outer metallic shell (“407-outer”).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the interconnection structure of Kuo according to the teachings of Huang, such that the conductive and dielectric layers of the interconnection structure are concentric. Huang teaches that the interconnection structure can have various horizontal cross-sectional shapes and structures, where the non-conductive supporting layers can be rectangular pillars, similar to the one shown by Kuo, or the non-conductive/dielectric layers can be concentric with the conductive layers. One of ordinary skill would realize that these are art-recognized alternate interconnection structures for bonding two substrates, and one of ordinary skill in the art would have found it obvious to substitute the concentric structure instead of pillar-shaped structure. The use of a known interconnection structure for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Re Claim 10, Kuo modified by Huang teaches the semiconductor device of claim 9, wherein the outer metallic shell (“407-outer”, Huang) is a first outer metallic shell and the dielectric liner (405, Huang) is a first dielectric liner, but does not disclose that the interconnection structure (401, Huang) further includes:
a second outer metallic shell surrounding and spaced from the first outer metallic shell, and
a second dielectric liner between the first outer metallic shell and the second outer metallic shell, and wherein the continuous metallic bridging layer is further over and connected with the second outer metallic shell.
However, Huang discloses that the conduction structure 401 and the stress-relieving structure 201, help in reducing stress to the devices below during the manufacturing process (Col. 9, lines 39-50), and the width of the 401 structure (w3, Col. 8, lines 14-22) can be greater than the stress-relieving structure (Col. 8, lines 14-22). Thus, one of ordinary skill would realize that the width of the stress-relieving structure and in-turn the width of conduction structure 401, is dependent on design choice and depends on the surface area occupied by the active devices within the substrate below. If the width is larger, it would be obvious to one of ordinary skill to increase the width of the conduction structure 401, by forming a second and/or a third outer metallic shell (2nd and/or 3rd “407-outer”), and a 2nd dielectric liner between 1st and 2nd outer metallic shell (and/or a 3rd dielectric liner between 2nd and 3rd outer metallic shells), which will further elevate stress from the devices below and increase their longevity.
Re Claim 11, Kuo modified by Huang teaches the semiconductor device of claim 9, wherein the inner metallic pillar and the outer metallic shell extend from a bond pad (16, Fig. 8, para [0018], Kuo, also see annotated Fig. 8 of Kuo below) on the semiconductor substrate (10, Fig. 8, Kuo).
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Re Claim 12, Kuo modified by Huang teaches the semiconductor device of claim 11, wherein the inner metallic pillar and the outer metallic shell extend a same distance (see annotated Fig. 8 of Kuo above) from the bond pad (16, Kuo).
Re Claim 13, Kuo modified by Huang teaches the semiconductor device of claim 9, wherein the inner metallic pillar, the outer metallic shell, and the continuous metallic bridging layer include a copper material (conductive layers/pillars 36 can be made of copper, para [0024], Kuo).
Re Claim 15, Kuo modified by Huang teaches the semiconductor device of claim 9, wherein the dielectric liner (114, Kuo) includes a material with a greater flexibility than a flexibility of a material included by the inner metallic pillar and/or the outer metallic shell (elastic modulus of 114 is greater than the elastic modulus of the conductive material 36, para [0024], Kuo).
Re Claim 16, Kuo modified by Huang teaches the semiconductor device of claim 9, wherein the dielectric liner includes a polymer material (114 can be polymer, para [0025], Kuo).
Re Claim 17, Kuo modified by Huang teaches the semiconductor device of claim 9, wherein the interconnection structure (36+114, Kuo modified by Huang, Fig. 8) further includes a solder material (54, Fig. 8, para [0022], Fig. 8) over the continuous metallic bridging layer (“bridge-layer”, see annotated Fig. 8 of Kuo, above).
Re Claim 18, Kuo modified by Huang teaches the semiconductor device of claim 17, wherein the interconnection structure (36+114, Kuo modified by Huang, Fig. 8) further includes a metallic interconnection layer between the solder material and the continuous metallic bridging layer (a nickel layer can be formed between the interconnection structure and the solder layer, para [0020], Kuo).
Re Claim 19, Kuo modified by Huang teaches the semiconductor device of claim 18, wherein the metallic interconnection layer includes a nickel material (a nickel layer can be formed between the interconnection structure and the solder layer, para [0020], Kuo, see claim 18 above).
Response to Arguments
Applicant’s arguments with respect to claims 1 and 9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898