Attorney Docket Number: 93452
Filing Date: 07/27/2002
Claimed Priority Date: 07/07/2022 (CN 202210803581.7)
Inventors: Hu et al.
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the amendment filed on 08/28/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The amendment filed on 08/28/2025 in reply to the previous Office action mailed on 05/28/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-18.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7, 9, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Dai (US 2016/0351595) in view of Sun (US 2021/0036078).
Regarding claim 1, Dai (see, e.g., figs. 1-2) shows most aspects of the instant invention, including an array substrate comprising:
a substrate layer (area below 15); and
a thin-film transistor structure layer (area above 13) disposed on the substrate layer
wherein the substrate layer comprises:
a first substrate layer 10;
a metal layer 22 disposed on the first substrate layer, and the metal layer comprising a plurality of light-shading blocks 121, 122 arranged at intervals; and
a second substrate layer 13 disposed on the metal layer and covering the plurality of light-shading blocks arranged at intervals; and
wherein the thin-film transistor structure layer (area above 13) comprises:
a plurality of thin-film transistor devices, wherein each of the thin-film transistor devices has a source/drain electrode layer 181/183, 182/184 and a pixel electrode layer 19 disposed on the source/drain electrode layer; and
wherein:
an orthographic projection of a source/drain electrode layer and a source electrode layer 181/183, 182 on the first substrate layer 10 falls within an orthographic projection of corresponding each of the plurality of light-shading blocks 121, 122 on the first substrate layer;
a part of an orthographic projection of the pixel electrode layer 19 on the first substrate layer 10 overlaps an orthographic projection of each of the plurality of light-shading blocks 121, 122 on the first substrate layer; and
another part of the orthographic projection of the pixel electrode layer on the first substrate layer partially corresponds to a gap between adjacent two ones of the plurality of light-shading blocks
Dai shows most aspects of the instant invention, including that an orthographic projection of a source/drain electrode layer 181/183 on the first substrate layer 10 falls within an orthographic projection of a corresponding one of the plurality of light-shading blocks 121 on the first substrate layer (see, e.g., fig. 1) for one of Dai’s thin-film transistor devices. Furthermore, Dai teaches that Dai’s plurality of thin-film transistor devices are not limited to being two distinct forms and that Dai’s array substrate can include variations and modifications without departing from the scope of the device (see, e.g., pars.0039/ll.12-13 and 0068). However, Dai fails to explicitly illustrate that such an orthographic projection arrangement applies to all of (i.e., a plurality of) Dai’s thin-film transistor devices. Sun, in the same field of endeavor and in a similar device to Dai, teaches an array substrate 10 comprising a plurality of thin-film transistor devices 210, wherein for all of Sun’s thin-film transistor devices an orthographic projection of each source/drain electrode layer 211/212 on a first substrate layer 240 falls within an orthographic projection of corresponding each of a plurality of light shading blocks 600 on the first substrate layer (see, e.g., Sun: fig. 1).
Sun and Dai are both evidence showing that one of ordinary skill in the art would appreciate that having an orthographic projection of each source/drain electrode layer on a first substrate layer falling within an orthographic projection of corresponding each of a plurality of light-shading blocks on the first substrate layer would be equivalent to having a structure comprising both an orthographic projection of a source/drain electrode layer on a first substrate layer falling within an orthographic projection of a corresponding one of a plurality of light-shading blocks on a first substrate layer and an orthographic projection of a source/drain electrode layer on a first substrate layer falling partially outside of an orthographic projection of a corresponding one of a plurality of light-shading blocks on a first substrate layer, and that such differences would result in no unexpected changes in the performance of array substrate of Dai. That is, the orthographic projection orientations of both Dai (as seen in figure 1 of Dai’s leftmost thin-film transistor device) and Sun or Dai (as seen in figure 1 of Dai’s rightmost thin-film transistor device) would yield the predictable result of providing functional source/drain electrode layers in a plurality of thin-film transistor devices such that the source/drain electrode layers are capable of connecting to a pixel electrode layer.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either an orthographic projection of each source/drain electrode layer on a first substrate layer falling within an orthographic projection of corresponding each of a plurality of light-shading blocks on the first substrate layer, as taught by Dai and Sun, or a structure comprising both an orthographic projection of a source/drain electrode layer on a first substrate layer falling within an orthographic projection of a corresponding one of a plurality of light-shading blocks on a first substrate layer and an orthographic projection of a source/drain electrode layer on a first substrate layer falling partially outside of an orthographic projection of a corresponding one of a plurality of light-shading blocks on a first substrate layer, as taught by Dai, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing functional source/drain electrode layers in a plurality of thin-film transistor devices such that the source/drain electrode layers are capable of connecting to a pixel electrode layer. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Furthermore, as Dai’s disclosure suggests that Dai’s thin-film transistor devices are not limited to comprise different forms, Dai itself implicitly teaches an orientation of Dai wherein an orthographic projection of each source/drain electrode layer on a first substrate layer falls within an orthographic projection of corresponding each of a plurality of light-shading blocks on a first substrate layer (see, e.g., pars.0039/ll.12-13 and 0068).
Additionally, although Dai/Sun shows most aspects of the instant invention, Dai fails to specify that Dai’s substrate layer includes a first barrier layer disposed on the first substrate layer such that Dai’s metal layer is disposed on the first barrier layer. Sun, in the same field of endeavor, teaches an array substrate 10 having a substrate layer 220/230/240/250/260 comprising a first substrate layer 240, a first barrier layer 250 disposed on the first substrate layer, and a metal (see, e.g., Sun: par.0039/ll.26) layer 600 disposed on the first barrier layer comprising a plurality of light-shading blocks (see, e.g., Sun: fig. 1). Sun teaches that the inclusion of a first barrier layer between a first substrate layer and a metal layer/plurality of light-shading blocks prevents water and/or oxygen contamination and erosion in the array substrate (see, e.g., Sun: pars.0038/ll.9-13 and 0047/ll.1-2).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a first barrier layer in Dai’s array substrate, such that the first barrier layer is disposed on Dai’s first substrate layer and Dai’s metal layer/plurality of light-shading blocks is disposed on the first barrier layer, as taught by Sun, so as to prevent water and/or oxygen contamination and erosion in Dai’s array substrate.
Regarding claim 18, Dai/Sun shows most aspects of the instant invention, including the array substrate according to claim 1 (see paragraphs 5-11 above). Furthermore, Dai (see, e.g., Dai: figs. 1-2) teaches a manufacturing method S1-S13 for preparing the array substrate according to claim 1, wherein the manufacturing method comprises:
preparing S1-S6 the substrate layer (area below 15); and
preparing S7-S13 the thin-film transistor structure layer (area above 13) on the substrate layer
wherein a step of preparing the substrate layer comprises:
preparing S1 the first substrate layer 10;
preparing S1 the metal layer 22 on the first substrate layer;
patterning S3 the metal layer to form a plurality of light-shading blocks 121, 122 arranged at intervals; and
preparing S5 the second substrate layer 13 on the metal layer, wherein the second substrate covers the plurality of light-shading blocks arranged at intervals; and
wherein a step S7-S13 of preparing the thin-film transistor structure layer (area above 13) on the substrate layer (area below 15) comprises:
preparing S7-S13 a plurality of thin-film transistor devices, wherein each of the thin-film transistor devices has a source/drain electrode layer 181/183, 182/184 and a pixel electrode layer 19 disposed on the source/drain electrode layer;
wherein:
an orthographic projection of a source/drain electrode layer and a source electrode layer 181/183, 182 on the first substrate layer 10 falls within an orthographic projection of corresponding each of the plurality of light-shading blocks 121, 122 on the first substrate layer;
a part of an orthographic projection of the pixel electrode layer 19 on the first substrate layer overlaps an orthographic projection of each of the plurality of light-shading blocks on the first substrate layer; and
another part of the orthographic projection of the pixel electrode layer on the first substrate layer partially corresponds to a gap between adjacent two ones of the plurality of light-shading blocks
Dai shows most aspects of the instant invention, including that an orthographic projection of a source/drain electrode layer 181/183 on the first substrate layer 10 falls within an orthographic projection of a corresponding one of the plurality of light-shading blocks 121 on the first substrate layer (see, e.g., fig. 1) for one of Dai’s thin-film transistor devices. Furthermore, Dai teaches that Dai’s thin-film transistor devices are not limited to being two distinct forms and that Dai’s array substrate can include variations and modifications without departing from the scope of the device (see, e.g., pars.0039/ll.12-13 and 0068). However, Dai fails to explicitly illustrate that such an orthographic projection arrangement applies to all of (i.e., a plurality of) Dai’s thin-film transistor devices. Sun, in the same field of endeavor and in a similar device to Dai, teaches an array substrate 10 comprising a plurality of thin-film transistor devices 210, wherein for all of Sun’s thin-film transistor devices an orthographic projection of each source/drain electrode layer 211/212 on a first substrate layer 240 falls within an orthographic projection of corresponding each of a plurality of light shading blocks 600 on the first substrate layer (see, e.g., Sun: fig. 1 and par.0035/ll.4-5).
Sun and Dai are both evidence showing that one of ordinary skill in the art would appreciate that having an orthographic projection of each source/drain electrode layer on a first substrate layer falling within an orthographic projection of corresponding each of a plurality of light-shading blocks on the first substrate layer would be equivalent to having a structure comprising both an orthographic projection of a source/drain electrode layer on a first substrate layer falling within an orthographic projection of a corresponding one of a plurality of light-shading blocks on a first substrate layer and an orthographic projection of a source/drain electrode layer on a first substrate layer falling partially outside of an orthographic projection of a corresponding one of a plurality of light-shading blocks on a first substrate layer, and that such differences would result in no unexpected changes in the performance of array substrate of Dai. That is, the orthographic projection orientations of both Dai (as seen in figure 1 of Dai’s leftmost thin-film transistor device) and Sun or Dai (as seen in figure 1 of Dai’s rightmost thin-film transistor device) would yield the predictable result of providing functional source/drain electrode layers in a plurality of thin-film transistor devices such that the source/drain electrode layers are capable of connecting to a pixel electrode layer.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either an orthographic projection of each source/drain electrode layer on a first substrate layer falling within an orthographic projection of corresponding each of a plurality of light-shading blocks on the first substrate layer, as taught by Dai and Sun, or a structure comprising both an orthographic projection of a source/drain electrode layer on a first substrate layer falling within an orthographic projection of a corresponding one of a plurality of light-shading blocks on a first substrate layer and an orthographic projection of a source/drain electrode layer on a first substrate layer falling partially outside of an orthographic projection of a corresponding one of a plurality of light-shading blocks on a first substrate layer, as taught by Dai, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing functional source/drain electrode layers in a plurality of thin-film transistor devices such that the source/drain electrode layers are capable of connecting to a pixel electrode layer. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Furthermore, as Dai’s disclosure suggests that Dai’s thin-film transistor devices are not limited to comprise different forms, Dai itself implicitly teaches an orientation of Dai wherein an orthographic projection of each source/drain electrode layer on a first substrate layer falls within an orthographic projection of corresponding each of a plurality of light-shading blocks on a first substrate layer (see, e.g., pars.0039/ll.12-13 and 0068).
Additionally, although Dai/Sun shows most aspects of the instant invention, Dai fails to specify that Dai’s method includes a step of preparing a first barrier layer disposed on the first substrate layer such that Dai’s metal layer is disposed on the first barrier layer. Sun, in the same field of endeavor, teaches an array substrate 10 having a substrate layer 220/230/240/250/260 comprising a first substrate layer 240, a first barrier layer 250 disposed on the first substrate layer, and a metal (see, e.g., Sun: par.0039/ll.26) layer 600 disposed on the first barrier layer comprising a plurality of light-shading blocks (see, e.g., Sun: fig. 1). Sun teaches that the inclusion of a first barrier layer between a first substrate layer and a metal layer/plurality of light-shading blocks prevents water and/or oxygen contamination and erosion in the array substrate (see, e.g., Sun: pars.0038/ll.9-13 and 0047/ll.1-2).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a step of preparing a first barrier layer in Dai’s array substrate, such that the first barrier layer is disposed on Dai’s first substrate layer and Dai’s metal layer/plurality of light-shading blocks is disposed on the first barrier layer, as taught by Sun, so as to prevent water and/or oxygen contamination and erosion in Dai’s array substrate. See the comments stated in paragraphs 5-11 above with respect to claim 1, which are considered to be repeated here.
Regarding claim 2, Dai (see, e.g., fig. 1) shows that parts of the second substrate layer 13 located between the light shading blocks 121, 122 form a plurality of bumps facing the first substrate layer 10. Sun (see, e.g., Sun: fig. 1) also shows that parts of the second substrate layer 260 located between the light-shading blocks 600 form a plurality of bumps facing the first substrate layer 240.
Regarding claim 3, Dai (see, e.g., fig. 1) shows that the light-shading blocks 121, 122 are arranged corresponding to the thin-film transistor devices one-to-one. Sun (see, e.g., Sun: fig. 1) also shows that the light-shading blocks 600 are arranged corresponding to the thin-film transistor devices 210 one-to-one.
Regarding claim 4, Dai appears to illustrate that a sectional shape of each of Dai’s light-shading blocks is a square (see, e.g., fig. 1). However, it is noted that the specification fails to provide teachings about the criticality of having a sectional shape of each of the light-shading blocks be a square, a trapezoid, or a cone, as claimed in the instant application.
Therefore, absent any criticality, this limitation is only considered to be an obvious modification of the light-shading block sectional shape disclosed by Dai as the courts have held that a change in shape or configuration, without any criticality, is within the level of skill in the art, and the particular light-shading block sectional shape claimed by applicant is nothing more than one of numerous light-shading block sectional shapes that a person having ordinary skill in the art will find obvious to provide using routine experimentation as a matter of choice or based on its suitability for the intended use of the invention. See In re Daily, 149 USPQ 47 (CCPA 1976).
Furthermore, the claimed light-shading block sectional shape is known in the art: Sun, in the same field of endeavor teaches that the sectional shape of light-shading blocks can be square (see, e.g., Sun: fig. 1). Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the shape of a square in the light-shading block structure of Dai, because square-sectional-shape light-shading blocks are known in the semiconductor art for their use as light-blocking structures, as suggested by Sun, and implementing a known structure shape for its conventional use/purpose would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Regarding claim 7, Dai shows most aspects of the instant invention, including that Dai’s array substrate includes a substrate layer comprising a first substrate layer 10 (see, e.g., fig. 1). However, Dai fails to specify that the substrate layer further comprises a base and a first isolation layer disposed on the base, wherein the first substrate layer is disposed on the first isolation layer. Sun, in the same field of endeavor, teaches an array substrate 10 having a substrate layer 220/230/240/250/260 comprising a base 220 and a first isolation layer 230 disposed on the base, wherein a first substrate layer 240 is disposed on the first isolation layer 230 (see, e.g., Sun: fig. 1). Sun teaches that such a stacked base/isolation layer/substrate structure provides a substrate layer with better flexibility and better water and oxygen resistance (see, e.g., Sun: par.0038/ll.1-6).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Dai’s substrate layer further comprise a base and a first isolation layer disposed on the base, wherein Dai’s first substrate layer is disposed on the first isolation layer, as taught by Sun, so as to improve the flexibility and water and oxygen resistance of Dai’s substrate layer.
Regarding claim 7, Sun (see, e.g., Sun: fig. 1) shows that the substrate layer 220/230/240/250/260 further comprises:
a base 220; and
a first isolation layer 230 disposed on the base
wherein:
the first substrate layer 240 is disposed on the first isolation layer 230
Regarding claim 9, Sun (see, e.g., Sun: fig. 1) shows that the thin-film transistor structure layer (area above 260) further comprises:
an active layer 214 disposed on the substrate layer 220/230/240/250/260;
a gate insulating layer 270 disposed on the active layer;
a gate electrode layer 213 disposed on the gate insulating layer;
an interlayer dielectric layer 280 disposed on the gate electrode layer; and
a source/drain electrode layer (horizontal portions of 211/212) disposed on the interlayer dielectric layer
wherein:
the interlayer dielectric layer 280 is defined with contact holes (vertical portions of 211 and 212)
the contact holes extend from a side of the interlayer dielectric layer away from the substrate layer 220/230/240/250/260 to a surface of the active layer 214 away from the substrate layer; and
the source/drain electrode layer (horizontal portions of 211/212) is connected to the active layer 214 through the contact holes (vertical portions of 211 and 212) to form the thin-film transistor devices 210
Claims 5, 10-13, 15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Dai/Sun in view of Ma (CN 114420705A).
Regarding claim 10, Dai (see, e.g., figs. 1-2) shows most aspects of the instant invention, including an array substrate comprising:
a substrate layer (area below 15); and
a thin-film transistor structure layer (area above 13) disposed on the substrate layer
wherein the substrate layer comprises:
a first substrate layer 10;
a metal layer 22 disposed on the first substrate layer, the metal layer comprising a plurality of light-shading blocks 121, 122 arranged at intervals, wherein the light-shading blocks have a thickness; and
a second substrate layer 13 disposed on the metal layer and covering the plurality of light-shading blocks arranged at intervals, and parts of the second substrate layer located between the light-shading blocks form a plurality of bumps facing the first substrate layer; and
wherein the thin-film transistor structure layer (area above 13) comprises:
a plurality of thin-film transistor devices, wherein each of the thin-film transistor devices has a source/drain electrode layer 181/183, 182/184 and a pixel electrode layer 19 disposed on the source/drain electrode layer;
wherein:
an orthographic projection of a source/drain electrode layer and a source electrode layer 181/183, 182 on the first substrate layer 10 falls within an orthographic projection of corresponding each of the plurality of light-shading blocks 121, 122 on the first substrate layer;
a part of an orthographic projection of the pixel electrode layer 19 on the first substrate layer 10 overlaps an orthographic projection of each of the plurality of light-shading blocks 121, 122 on the first substrate layer; and
another part of the orthographic projection of the pixel electrode layer on the first substrate layer partially corresponds to a gap between adjacent two ones of the plurality of light-shading blocks
Dai shows most aspects of the instant invention, including that an orthographic projection of a source/drain electrode layer 181/183 on the first substrate layer 10 falls within an orthographic projection of a corresponding one of the plurality of light-shading blocks 121 on the first substrate layer (see, e.g., fig. 1) for one of Dai’s thin-film transistor devices. Furthermore, Dai teaches that Dai’s thin-film transistor devices are not limited to being two distinct forms and that Dai’s array substrate can include variations and modifications without departing from the scope of the device (see, e.g., pars.0039/ll.12-13 and 0068). However, Dai fails to explicitly illustrate that such an orthographic projection arrangement applies to all of (i.e., a plurality of) Dai’s thin-film transistor devices. Sun, in the same field of endeavor and in a similar device to Dai, teaches an array substrate 10 comprising a plurality of thin-film transistor devices 210, wherein for all of Sun’s thin-film transistor devices an orthographic projection of each source/drain electrode layer 211/212 on a first substrate layer 240 falls within an orthographic projection of corresponding each of a plurality of light shading blocks 600 on the first substrate layer (see, e.g., Sun: fig. 1 and par.0035/ll.4-5).
Sun and Dai are both evidence showing that one of ordinary skill in the art would appreciate that having an orthographic projection of each source/drain electrode layer on a first substrate layer falling within an orthographic projection of corresponding each of a plurality of light-shading blocks on the first substrate layer would be equivalent to having a structure comprising both an orthographic projection of a source/drain electrode layer on a first substrate layer falling within an orthographic projection of a corresponding one of a plurality of light-shading blocks on a first substrate layer and an orthographic projection of a source/drain electrode layer on a first substrate layer falling partially outside of an orthographic projection of a corresponding one of a plurality of light-shading blocks on a first substrate layer, and that such differences would result in no unexpected changes in the performance of array substrate of Dai. That is, the orthographic projection orientations of both Dai (as seen in figure 1 of Dai’s leftmost thin-film transistor device) and Sun or Dai (as seen in figure 1 of Dai’s rightmost thin-film transistor device) would yield the predictable result of providing functional source/drain electrode layers in a plurality of thin-film transistor devices such that the source/drain electrode layers are capable of connecting to a pixel electrode layer.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either an orthographic projection of each source/drain electrode layer on a first substrate layer falling within an orthographic projection of corresponding each of a plurality of light-shading blocks on the first substrate layer, as taught by Dai and Sun, or a structure comprising both an orthographic projection of a source/drain electrode layer on a first substrate layer falling within an orthographic projection of a corresponding one of a plurality of light-shading blocks on a first substrate layer and an orthographic projection of a source/drain electrode layer on a first substrate layer falling partially outside of an orthographic projection of a corresponding one of a plurality of light-shading blocks on a first substrate layer, as taught by Dai, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing functional source/drain electrode layers in a plurality of thin-film transistor devices such that the source/drain electrode layers are capable of connecting to a pixel electrode layer. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Furthermore, as Dai’s disclosure suggests that Dai’s thin-film transistor devices are not limited to comprise different forms, Dai itself implicitly teaches an orientation of Dai wherein an orthographic projection of each source/drain electrode layer on a first substrate layer falls within an orthographic projection of corresponding each of a plurality of light-shading blocks on a first substrate layer (see, e.g., pars.0039/ll.12-13 and 0068). See the comments stated in paragraphs 5-11 above with respect to claim 1, which are considered to be repeated here.
Additionally, although Dai/Sun shows most aspects of the instant invention, Dai fails to specify that Dai’s substrate layer includes a first barrier layer disposed on the first substrate layer such that Dai’s metal layer is disposed not the first barrier layer. Sun, in the same field of endeavor, teaches an array substrate 10 having a substrate layer 220/230/240/250/260 comprising a first substrate layer 240, a first barrier layer 250 disposed on the first substrate layer, and a metal (see, e.g., Sun: par.0039/ll.26) layer 600 disposed on the first barrier layer comprising a plurality of light-shading blocks (see, e.g., Sun: fig. 1). Sun teaches that the inclusion of a first barrier layer between a first substrate layer and a metal layer/plurality of light-shading blocks prevents water and/or oxygen contamination and erosion in the array substrate (see, e.g., Sun: pars.0038/ll.9-13 and 0047/ll.1-2).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a first barrier layer in Dai’s array substrate, such that the first barrier layer is disposed on Dai’s first substrate layer and Dai’s metal layer/plurality of light-shading blocks is disposed on the first barrier layer, as taught by Sun, so as to prevent water and/or oxygen contamination and erosion in Dai’s array substrate.
Furthermore, although Dai/Sun shows most aspects of the invention, Dai fails to specify the thickness of the light shading blocks. Ma, in a similar device to Dai, teaches suitable thickness for light-shading blocks to be greater than 0 angstrom and less than 3000 angstroms (see, e.g., Ma: par.0051/ll.3-4). Ma is evidence that one of ordinary skill in the art would have appreciated that appreciated that having light-shading blocks with thickness between 0 and 3000 angstroms would be equivalent to a device having light-shading blocks of any other thickness, and that such differences would result in no unexpected changes in the device of Dai. That is, both the light-shading blocks of Dai and Ma would yield the predictable result of providing a suitable light-blocking layer for an array substrate.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to use a light-shading block thickness between 0 and 3000 angstroms, as taught by Ma, or to use any other light-shading block thickness, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing a suitable light-blocking layer for an array substrate. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Nevertheless, differences in thickness will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph below) of the claimed thickness, i.e., 0 angstroms to 3000 angstroms, it would have been obvious to one of ordinary skill in the art to use these values in the device of Dai.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 11, Dai (see, e.g., fig. 1) shows that the light-shading blocks 121, 122 are arranged corresponding to the thin-film transistor devices one-to-one. Sun (see, e.g., Sun: fig. 1) also shows that the light-shading blocks 600 are arranged corresponding to the thin-film transistor devices 210 one-to-one.
Regarding claim 12, Dai appears to illustrate that a sectional shape of each of Dai’s light-shading blocks is a square (see, e.g., fig. 1). However, it is noted that the specification fails to provide teachings about the criticality of having a sectional shape of each of the light-shading blocks be a square, a trapezoid, or a cone, as claimed in the instant application.
Therefore, absent any criticality, this limitation is only considered to be an obvious modification of the light-shading block sectional shape disclosed by Dai as the courts have held that a change in shape or configuration, without any criticality, is within the level of skill in the art, and the particular light-shading block sectional shape claimed by applicant is nothing more than one of numerous light-shading block sectional shapes that a person having ordinary skill in the art will find obvious to provide using routine experimentation as a matter of choice or based on its suitability for the intended use of the invention. See In re Daily, 149 USPQ 47 (CCPA 1976).
Furthermore, the claimed light-shading block sectional shape is known in the art: Sun, in the same field of endeavor teaches that the sectional shape of light-shading blocks can be square (see, e.g., Sun: fig. 1). Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the shape of a square in the light-shading block structure of Dai, because square-sectional-shape light-shading blocks are known in the semiconductor art for their use as light-blocking structures, as suggested by Sun, and implementing a known structure shape for its conventional use/purpose would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Regarding claims 5 and 13, Dai/Sun and Dai/Sun/Ma teaches most aspects of the invention (see paragraphs 5-11 and 29-40 above, respectively). Dai, however, is silent with respect to the thickness of the light-shading blocks and the specific metal material. Ma, in a similar device to Dai, teaches suitable thickness for light-shading blocks to be greater than 0 angstrom and less than 3000 angstroms and suitable material to include titanium alloy (see, e.g., Ma: par.0051/ll.3-4).
Ma is evidence that one of ordinary skill in the art would have appreciated that appreciated that having light-shading blocks with thickness between 0 and 3000 angstroms would be equivalent to a device having light-shading blocks of any other thickness, and that such differences would result in no unexpected changes in the device of Dai. That is, both the light-shading blocks of Dai and Ma would yield the predictable result of providing a suitable light-blocking layer for an array substrate.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to use a light-shading block thickness between 0 and 3000 angstroms, as taught by Ma, or to use any other light-shading block thickness, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing a suitable light-blocking layer for an array substrate. Furthermore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to use titanium alloy in Dai’s light-shading blocks because titanium alloy was recognized in the semiconductor art for its use as light-shading block material, as taught by Ma, and selecting a material for its known conventional use would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007). See also the comments stated above in paragraphs 29-40, which are considered to be repeated here.
Regarding claim 15, Dai shows most aspects of the instant invention, including that Dai’s array substrate includes a substrate layer comprising a first substrate layer 10 (see, e.g., fig. 1). However, Dai fails to specify that the substrate layer further comprises a base and a first isolation layer disposed on the base, wherein the first substrate layer is disposed on the first isolation layer. Sun, in the same field of endeavor, teaches an array substrate 10 having a substrate layer 220/230/240/250/260 comprising a base 220 and a first isolation layer 230 disposed on the base, wherein a first substrate layer 240 is disposed on the first isolation layer 230 (see, e.g., Sun: fig. 1). Sun teaches that such a stacked base/isolation layer/substrate structure provides a substrate layer with better flexibility and better water and oxygen resistance (see, e.g., Sun: par.0038/ll.1-6).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Dai’s substrate layer further comprise a base and a first isolation layer disposed on the base, wherein Dai’s first substrate layer is disposed on the first isolation layer, as taught by Sun, so as to improve the flexibility and water and oxygen resistance of Dai’s substrate layer.
Regarding claim 15, Sun (see, e.g., fig. 1) shows that the substrate layer 220/230/240/250/260 further comprises:
a base 220; and
a first isolation layer 230 disposed on the base
wherein:
the first substrate layer 240 is disposed on the first isolation layer 230
Regarding claim 17, Sun shows that the thin-film transistor structure layer (area above 260) further comprises:
an active layer 214 disposed on the substrate layer 220/230/240/250/260;
a gate insulating layer 270 disposed on the active layer;
a gate electrode layer 213 disposed on the gate insulating layer;
an interlayer dielectric layer 280 disposed on the gate electrode layer; and
a source/drain electrode layer (horizontal portions of 211/212) disposed on the interlayer dielectric layer
wherein:
the interlayer dielectric layer 280 is defined with contact holes (vertical portions of 211 and 212)
the contact holes extend from a side of the interlayer dielectric layer away from the substrate layer 220/230/240/250/260 to a surface of the active layer 214 away from the substrate layer; and
the source/drain electrode layer (horizontal portions of 211/212) is connected to the active layer 214 through the contact holes (vertical portions of 211 and 212) to form the thin-film transistor devices 210
Claims 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Dai/Sun in view of You (CN 212113725U).
Regarding claim 6, Dai/Sun teaches most aspects of the invention (see paragraphs 5-11 and 19 above). Sun (see, e.g., Sun: fig. 1) further teaches that a plurality of light-shading blocks 600 are arranged at intervals on the first barrier layer 250, and that the plurality of bumps are in contact with the first barrier layer. Sun, however, is silent with respect to the material of the first barrier layer. You, in the same field of endeavor, teaches inorganic insulating material to be suitable for a barrier layer below a metal light-shading layer.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to use inorganic insulating material in Dai/Sun’s first barrier layer because inorganic material was recognized in the semiconductor art for its use as barrier layer material, as taught by You, and selecting a material for its known conventional use would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Regarding claim 8, Dai/Sun shows most aspects of the invention (see paragraphs 5-11 and 24-26 above). Furthermore, although Dai teaches a substrate layer (area below 15) under a thin-film transistor structure layer (area above 13), Dai fails to show that the substrate layer further comprises a second barrier layer arranged on Dai’s second substrate layer 13, wherein the second barrier layer comprises a first silicon oxide layer disposed on the second substrate layer, a silicon nitride layer disposed on the first silicon oxide layer, and a second silicon oxide layer disposed on the silicon nitride layer, wherein the thin-film transistor structure layer is disposed on the second silicon oxide layer.
You, in the same field of endeavor, teaches a stacked-layer barrier layer, wherein the barrier layer comprises, from bottom-to-top, a substrate layer 10, a first silicon oxide layer 202, a second silicon oxide layer 230, and a thin-film transistor layer 50 (see, e.g., You: fig. 3 and par.0038). You further teaches an inorganic insulating layer 40 in between the first and second silicon oxide layers. You teaches that such a multi-layer barrier layer structure can prevent impurities and moisture from penetrating into the thin-film transistor structure layer (see, e.g., You: par.0043/ll.1-2).
Although You does not disclose the inorganic insulating layer 40 to explicitly be a silicon nitride layer, You teaches silicon nitride to be suitable inorganic insulating material for barrier layers (see, e.g., You: par.0038/ll.1). Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to use silicon nitride as You’s inorganic material, or to use any other suitable inorganic material, because these were recognized as equivalents in the semiconductor art, and selecting a material for its known conventional use would be within the level of ordinary skill in the art. Furthermore, both structures would provide the predictable result of providing a middle inorganic insulating barrier layer to assist in protecting a thin-film transistor structure layer. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the first silicon oxide/silicon nitride/second silicon oxide second barrier layer of You in the substrate layer of Dai/Sun (which is inherently disposed below the thin-film transistor structure layer), as taught by You, so as to protect the thin-film transistor structure layer from impurities and moisture.
Claims 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Dai/Sun/Ma in view of You.
Regarding claim 14, Dai/Sun/Ma shows most aspects of the invention (see paragraphs 29-40 above). Sun (see, e.g., fig. 1) further teaches that a plurality of light-shading blocks 600 are arranged at intervals on the first barrier layer 250, and that the plurality of bumps are in contact with the first barrier layer. Sun, however, is silent with respect to the material of the first barrier layer. You, in the same field of endeavor, teaches inorganic insulating material to be suitable for a barrier layer below a metal light-shading layer.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to use inorganic material in Dai/Sun/Ma’s first barrier layer because inorganic insulating material was recognized in the semiconductor art for its use as barrier layer material, as taught by You, and selecting a material for its known conventional use would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007). See the comments stated above in paragraphs 53-54 with respect to claim 6, which are considered to be repeated here.
Regarding claim 16, Dai/Sun/Ma shows most aspects of the invention (see paragraphs 29-40 and 48-50 above). Furthermore, although Dai teaches a substrate layer (area below 15) under a thin-film transistor structure layer (area above 13), Dai fails to show that the substrate layer further comprises a second barrier layer arranged on Dai’s second substrate layer 13, wherein the second barrier layer comprises a first silicon oxide layer disposed on the second substrate layer, a silicon nitride layer disposed on the first silicon oxide layer, and a second silicon oxide layer disposed on the silicon nitride layer, wherein the thin-film transistor structure layer is disposed on the second silicon oxide layer.
You, in the same field of endeavor, teaches a stacked-layer barrier layer, wherein the barrier layer comprises, from bottom-to-top, a substrate layer 10, a first silicon oxide layer 202, a second silicon oxide layer 230, and a thin-film transistor layer 50 (see, e.g., You: fig. 3 and par.0038). You further teaches an inorganic insulating layer 40 in between the first and second silicon oxide layers. You teaches that such a multi-layer barrier layer structure can prevent impurities and moisture from penetrating into the thin-film transistor structure layer (see, e.g., You: par.0043/ll.1-2).
Although You does not disclose the inorganic insulating layer 40 to explicitly be a silicon nitride layer, You teaches silicon nitride to be suitable inorganic insulating material for barrier layers (see, e.g., You: par.0038/ll.1). Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to use silicon nitride as You’s inorganic material, or to use any other suitable inorganic material, because these were recognized as equivalents in the semiconductor art, and selecting a material for its known conventional use would be within the level of ordinary skill in the art. Furthermore, both structures would provide the predictable result of providing a middle inorganic insulating barrier layer to assist in protecting a thin-film transistor structure layer. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include the first silicon oxide/silicon nitride/second silicon oxide second barrier layer of You in the substrate layer of Dai/Sun/Ma (which is inherently disposed below the thin-film transistor structure layer), as taught by You, so as to protect the thin-film transistor structure layer from impurities and moisture. See also the comments stated above in paragraphs 55-58 with respect to claim 8, which are considered to be repeated here.
Response to Arguments
Applicant’s amendments to the drawings filed on 08/28/2025 have overcome the objections to the drawings presented in the Office action mailed on 05/28/2025. Accordingly, the objections to the drawings put forth in the previous Office action are hereby withdrawn.
Applicant’s arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant’s amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action.
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/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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