DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-17 and 21-23 are pending in the application and are currently being examined. Claims 1, 3, 10, and 21have been amended. No new claims have been added.
EXAMINER’S AMENDMENT
The application has been amended as follows:
22. (Previously Presented)The semiconductor device of claim 21, further comprising:
a third semiconductor die coupled to the redistribution structure, wherein the third semiconductor die is in electrical contact with the second semiconductor die via the first interconnect structure;
a fourth semiconductor die coupled to the redistribution structure, wherein the fourth semiconductor die is in electrical contact with the second semiconductor die via the second interconnect structure; and
a fifth semiconductor die coupled to the redistribution structure, wherein the fifth semiconductor die is in electrical contact with the second semiconductor die via the third interconnect structure.
23. (Previously Presented) The semiconductor device of claim 21, further comprising:
a through via structure in the second semiconductor die, wherein the through via structure is in electrical contact with at least one of the first interconnect structure, the second interconnect structure, or the third interconnect structure.
Authorization for this examiner’s amendment was given in an interview with James Radwill on 9/25/2026.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-17 and 21-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Examiner agrees that the previously cited prior art fails to teach the newly amended limitations. However, Examiner respectfully disagrees with the assertion that the claims are now allowable, and has brought in new art in the rejection to follow.
Claim Objections
Claims 10-23 objected to because of the following informalities:
Independent claims 10 and 21 appear to have a typo, as the references to the first, second, and third directions appear to be missing the article “a” preceding (i.e. “a first direction” is written as “first direction”). For the purposes of examination, the article “a” is assumed present.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 5 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 5 states.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brun (US 2023/0307341 A1) in view of Colgan et al. (US 2022/0084969 A1, hereafter Colgan).
Regarding claim 1, Fig. 2A (flipped upside down from presented orientation) of Brun teaches a semiconductor package, comprising:
a plurality of bottom semiconductor dies (108 labeled in Fig. 1A, [0075]);
a plurality of top semiconductor dies (128, labeled in Fig. 1A, [0083]), each of the plurality of top semiconductor dies (128) bonded (bonded through interconnects 126, [0083]) to a corresponding one of the plurality of bottom semiconductor dies (108).
Brun fails to explicitly show a plurality of semiconductor bridges, each of the plurality of semiconductor bridges interposed between neighboring ones of the plurality of top semiconductor dies. However, Brun depicts a semiconductor bridge (132, [0083]) in Fig. 2A. However, one of ordinary skill in the art would know to duplicate the top semiconductors, bottom semiconductors, and semiconductor bridges in order to have a higher capacity device (see MPEP 2144.04 for duplication of parts). This duplication of parts is known in the art and is shown in Fig. 11 of Colgan with the semiconductor chips interconnected to adjacent chips through the interconnects similar to the bridge semiconductors of Brun (1104, [0044]).
Brun in view of Colgan fail to teach a contiguous redistribution structure disposed over the plurality of top semiconductor dies, opposite from the plurality of bottom semiconductor dies and comprising a plurality of interconnect structures; wherein a first one of the plurality of top semiconductor dies is connected to a non-adjacent second one of the plurality of top semiconductor dies via a first subset of the plurality of interconnect structures.
However, Colgan teaches in Figs. 6 and 7 teach a redistribution layer on top of the device (second wafer 302, [0050]) which contains interconnect structures to connect non-adjacent top semiconductor dies (lines 701-704 in Fig. 7, [0050]) Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Brun in view of Colgan to have the redistribution layer and interconnects as taught by Colgan in order to get the expected result of chip-to-chip communication between semiconductor dies that are in the same row or column.
Regarding claim 2, Brun in view of Colgan teach the semiconductor package of claim 1, wherein the first subset of the interconnect structures each extend along a first direction tilted from a second direction along (see annotated Fig. 7 of Colgan) which a third one (see annotated Fig. 7 of Colgan) of the plurality of top semiconductor dies (128, labeled in Fig. 1A of Brun, [0083], 305 of Fig. 3 of Colgan, [0035]) is arranged and from a third direction (see annotated Fig. 7 of Colgan) along which a fourth one of the plurality of top semiconductor dies (see annotated Fig. 7 of Colgan) is arranged.
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Regarding claim 3, Brun in view of Colgan teach semiconductor package of claim 1, wherein the bottom semiconductor dies are hybrid bonded with the top semiconductor dies. While not explicitly stated, Brun describes the process of hybrid bonding at a due-to-die level (which includes top dies 128 and bottom dies 108) in [0048].
Regarding claim 4, Brun in view of Colgan teach the semiconductor package of claim 2, wherein the third top semiconductor die is disposed immediately next to the first top semiconductor die along the second direction, and the fourth top semiconductor die is disposed immediately next to the first top semiconductor die along the third direction (see annotated Fig. 7 of Colgan, top dies being 128, labeled in Fig. 1A of Brun, [0083], 305 of Fig. 3 of Colgan, [0035]).
Regarding claim 5, Brun in view of Colgan teach the semiconductor package of claim 2, wherein the second top semiconductor die is disposed non-adjacent to the first top semiconductor die along the first direction (see annotated Fig. 7 of Colgan, top dies being 128, labeled in Fig. 1A of Brun, [0083], 305 of Fig. 3 of Colgan, [0035]).
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Regarding claim 6, Brun in view of Colgan teach the semiconductor package of claim 1, wherein the first top semiconductor die (128, labeled in Fig. 1A of Brun, [0083]) includes at least a first through via structure (130, [0083]) and the second top semiconductor die direction (see annotated Fig. 7 of Colgan, top dies being 128, labeled in Fig. 1A of Brun, [0083], 305 of Fig. 3 of Colgan, [0035]) includes at least a second through via structure (130), and wherein the first through via structure and the second through via structure are electrically coupled to each other through the first subset of the interconnect structures (lines 702 [0050] of Cogan depict the connection of non-adjacent dies through interconnect lines along the first direction).
Regarding claim 7, Brun in view of Colgan teach the semiconductor package of claim 1. While Brun does not explicitly teach a plurality of connectors disposed opposite the plurality of bottom semiconductor dies from the plurality of top semiconductor dies, Fig. 9 depicts an assembly that show multiple IC packages (similar to the package depicted in Fig. 2A) stacked together. Thus it would have been obvious to modify Brun in view of Colgan to comprise a plurality of connectors (coupling components 2328, [0124]) disposed opposite the plurality of bottom semiconductor dies (108, [0075]) from the plurality of top semiconductor dies (128, [0083]) in order to get the expected result of a device assembly built to facilitate communication between package levels.
Regarding claim 8, Brun in view of Colgan teach the semiconductor package of claim 1, wherein the first top semiconductor die (128, labeled in Fig. 1A of Brun, [0083], see annotated Fig. 7 of Colgan) is connected to a fifth one of the plurality of top semiconductor dies (128, see annotated Fig. 7 of Colgan) via a second subset of the plurality of interconnect structures (lines 702 [0050] of Cogan depict the connection of non-adjacent dies through interconnect lines along the first direction, most specifically 702 show lines that would extend from 1 to 2 and 1 to 5).
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Regarding claim 9, Brun in view of Colgan teach the semiconductor package of claim 8, wherein the first subset of the interconnect structures and the second subset of the interconnect structures extend in parallel with each other (lines 702 in Fig. 7 of Colgan all run in the first direction, and thus parallel to one another).
Claim(s) 10-17 and 21-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brun in view of Colgan, and further in view of Yu et al. (US 2020/0006089 A1, hereafter Yu).
Regarding claim 10, Fig. 2A of Brun teaches a semiconductor package, comprising:
a plurality of bottom semiconductor dies (108 labeled in Fig. 1A, [0075]);
a plurality of top semiconductor dies (128, labeled in Fig. 1A, [0083]), each of the plurality of top semiconductor dies (128) having a lower surface hybrid-bonded to an upper surface of a corresponding one of the plurality of bottom semiconductor dies (108) (while not explicitly stated, Brun describes the process of hybrid bonding at a due-to-die level (which includes top dies 128 and bottom dies 108) in [0048]); and
While Brun fails to explicitly teach the plurality of bottom semiconductor dies to be regularly tiled, one of ordinary skill in the art would know to duplicate the top semiconductors, bottom semiconductors, and semiconductor bridges in order to have a higher capacity device (see MPEP 2144.04 for duplication of parts). This duplication of parts is known in the art and is shown in Fig. 11 of Colgan with the semiconductor chips disposed in a regular tile pattern.
Brun in view of Colgan fail to teach a redistribution structure disposed over the plurality of bottom semiconductor dies and comprising a plurality of interconnect structures; wherein the plurality of interconnect structures at least include a first interconnect structure extending in first direction, a second interconnect structure extending in second direction.
However, Colgan teaches in Figs. 6 and 7 teach a redistribution layer on top of the device (second wafer 302, [0050]) which contains interconnect structures to connect non-adjacent top semiconductor dies (lines 701-704 in Fig. 7, [0050]) Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Brun in view of Colgan to have the redistribution layer and interconnects as taught by Colgan in order to get the expected result of chip-to-chip communication between semiconductor dies that are in the same row or column.
Brun in view of Colgan are silent on a third interconnect structure extending in third direction, the first to third directions being different from one another according to a nominal position of the regularly tiled bottom semiconductor dies.
However, Fig. 21 of Yu Show interconnects extending in a third direction, and the first to third directions being different from one another according to a nominal position of the regularly tiled bottom semiconductor dies (see annotated Fig. 21). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the interconnects of Brun in view of Colgan to include interconnects that extend in a third direction different from the first and second directions like taught by Yu in order to get the expected result of connecting semiconductor dies that are in different rows or columns from one another.
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Regarding claim 11, Brun in view of Colgan in view of Yu teach the semiconductor package of claim 10, wherein a first one of the plurality of top semiconductor dies (128 labeled in Fig. 1A, [0083]) is connected to a second one of the plurality of top semiconductor dies (128) via the first interconnect structure, and wherein the first top semiconductor die is disposed immediately next to the second top semiconductor die along the first direction (see annotated Fig. 7 of Colgan, top dies being 128, labeled in Fig. 1A of Brun, [0083], 305 of Fig. 3 of Colgan, [0035] and lines 704 [0050] of Cogan depict the connection of dies through interconnect lines along the second direction, but can be extrapolated to the first direction as well).
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Regarding claim 12, Brun in view of Colgan in view of Yu teach the semiconductor package of claim 10, wherein a first one of the plurality of top semiconductor dies (128 labeled in Fig. 1A, [0083]) is connected to a third one of the plurality of top semiconductor dies (128) via the second interconnect structure, and wherein the first top semiconductor die is disposed immediately next to the third top semiconductor die along the second direction (see annotated Fig. 7 of Colgan, top dies being 128, labeled in Fig. 1A of Brun, [0083], 305 of Fig. 3 of Colgan, [0035] and lines 704 [0050] of Cogan depict the connection of dies through interconnect lines along the second direction).
Regarding claim 13, Brun in view of Colgan in view of Yu teach the semiconductor package of claim 10, wherein a first one of the plurality of top semiconductor dies (128 of Brun labeled in Fig. 1A, [0083]) is connected to a fourth one of the plurality of top semiconductor dies (128 of Brun) via the third interconnect structure (depicted in Fig. 21 of Yu), and wherein the first top semiconductor die is disposed next to the fourth top semiconductor die along the third direction (see annotated Fig. 7 of Colgan).
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Regarding claim 14, Brun in view of Colgan in view of Yu teach the semiconductor package of claim 10, wherein the third direction is tilted from any of the first direction or the second direction with an angle less than 90 degrees (see annotated Fig. 7 of Colgan).
Regarding claim 15, Brun in view of Colgan in view of Yu teach the semiconductor package of claim 10. While Brun does not explicitly teach a plurality of connectors disposed opposite the plurality of bottom semiconductor dies from the plurality of top semiconductor dies, Fig. 9 depicts an assembly that show multiple IC packages (similar to the package depicted in Fig. 2A) stacked together. Thus it would have been obvious to modify Brun in view of Colgan to comprise a plurality of connectors (coupling components 2328, [0124]) disposed opposite the plurality of bottom semiconductor dies (108, [0075]) from the plurality of top semiconductor dies (128, [0083]) in order to get the expected result of a device assembly built to facilitate communication between package levels.
Regarding claim 16, Brun in view of Colgan in view of Yu teach the semiconductor package of claim 10, wherein each of the plurality of top semiconductor dies (128 labeled in Fig. 1A, [0083]) includes at least one through via structure (130, [0083]) connecting to a corresponding one of the interconnect structures (lines 701-704 in Fig. 7 of Colgan, [0050]).
Regarding claim 17, Brun in view of Colgan in view of Yu teach the semiconductor package of claim 10, wherein each of the top semiconductor dies (128 labeled in Fig. 1A, [0083]) is bonded to the corresponding bottom semiconductor die (108 labeled in Fig. 1A, [0075]) through a hybrid bonding technique (while not explicitly stated, Brun describes the process of hybrid bonding at a due-to-die level (which includes top dies 128 and bottom dies 108) in [0048]).
Regarding claim 21, Brun teaches a semiconductor device, comprising:
a first semiconductor die (108, [0075]) disposed over a first substrate (106 in Fig. 1A); and
a second semiconductor die (128, [0083]) bonded to the first semiconductor die (108) by a hybrid bond between a first surface of the first semiconductor die and a second surface of the second semiconductor die (while not explicitly stated, Brun describes the process of hybrid bonding at a due-to-die level (which includes second die 128 and first die 108) in [0048]),
Brun fails to teach a contiguous redistribution structure including a plurality of interconnect structures laterally surrounding and vertically offset from a second semiconductor die coupled with the redistribution structure, and the second semiconductor die coupled with the redistribution structure.
However, Colgan teaches in Figs. 6 and 7 teach a redistribution layer on top of the device (second wafer 302, [0050]) which contains interconnect structures to connect non-adjacent first semiconductor dies (lines 701-704 in Fig. 7, [0050]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Brun in view of Colgan to have the redistribution layer and interconnects as taught by Colgan in order to get the expected result of chip-to-chip communication between semiconductor dies that are in the same row or column. Brun also teaches the top semiconductors containing through via structures (130, [0083]) which would facilitate coupling between the second semiconductor and the redistribution layer.
Further, Colgan teaches the plurality of interconnect structures (lines 701-704 in Fig. 7, [0050]) include a first interconnect structure (such as lines 702 extending) in first direction (see annotated Fig. 7), and a second interconnect structure (such as lines 704) extending in second direction (see annotated Fig. 7).
Brun in view of Colgan are silent on a third interconnect structure extending in third direction, the first to third directions being different from one another.
However, Fig. 21 of Yu Show interconnects extending in a third direction, and the first to third directions being different from one another (see annotated Fig. 21). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the interconnects of Brun in view of Colgan to include interconnects that extend in a third direction different from the first and second directions like taught by Yu in order to get the expected result of connecting semiconductor dies that are in different rows or columns from one another.
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Regarding claim 22, Brun in view of Colgan in view of Yu teach the semiconductor device of claim 21, further comprising:
a third semiconductor die (128, [0083], see annotated Fig. 7 of Colgan) coupled to the redistribution structure (second wafer 302 of Colgan, [0050]), wherein the third semiconductor die is in electrical contact with the second semiconductor die (128, see annotated Fig. 7 of Colgan) via the first interconnect structure (through lines like 702 in Fig. 7 of Colgan);
a fourth semiconductor die (128, see annotated Fig. 7 of Colgan) coupled to the redistribution structure (302 of Colgan), wherein the fourth semiconductor die is in electrical contact with the second semiconductor die (128) via the second interconnect structure (through lines like 704 in Fig. 7 of Colgan); and
a fifth semiconductor die (128, see annotated Fig. 7 of Colgan) coupled to the redistribution structure (302 of Colgan), wherein the fifth semiconductor die is in electrical contact with the second semiconductor die via the third interconnect structure (through lines like those taught in Fig. 21 of Yu).
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Regarding claim 23, Brun in view of Colgan in view of Yu teach the semiconductor device of claim 21, further comprising:
a through via structure (130, [0083]) in the second semiconductor die (128, [0083]), wherein the through via structure (130) is in electrical contact with at least one of the first interconnect structure, the second interconnect structure, or the third interconnect structure (as the redistribution layer is on top of the second semiconductor die with the interconnect structures in electrical contact with the second die, and the through via structure is through the second die for electrical contact, the through via structure is in electrical contact with at least one of the first interconnect structure, the second interconnect structure, or the third interconnect structure).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SAMMANTHA K SALAZ/Examiner, Art Unit 2892
/ERIC W JONES/Primary Examiner, Art Unit 2892
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