DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/02/2025 has been entered.
Status of the Application
Acknowledgement is made of the amendment received on 10/02/2025. Claims 1-2, 4-20 are pending in this application. Claim 3 is cancelled.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2, 4-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "a plasma atmosphere" in line 12. There is insufficient antecedent basis for this limitation in the claim.
Claim 8 recites the limitation “a plasma atmosphere” in line 17. There is insufficient basis for this limitation in the claim.
In the context of the claim 8 recite the limitation “forming a second conductive polymer layer” is not clear. Forming a first conductive layer inside the preliminary hole, after forming the first conductive polymer layer sequentially performing etching another portion of the insulating structure to form what? and forming a second conductive polymer layer exactly where? One ordinary skill in the relevant art would not know what steps covered by the limitation. For these reasons, the claim is indefinite.
Remarks: To the best of the Examiner’s knowledge and understanding, claim 1 is interpreted and treated as set forth in the Office action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-6, 8, 10-13 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Tokashiki et al (US20190206723A1) in view of Kiehlbauch et al (US US20080057724A1)
Re claim 1 Tokashiki teaches, a method of manufacturing an integrated circuit device (fig 4A-6), the method comprising:
forming an etching target structure (110, fig 4A) [0018] on a substrate (a substrate not shown) [0018];
forming, on the etching target structure (110, fig 4A), an etching mask pattern (120, fig 4A) [0018] having an opening (opening in 120);
first etching a portion (top portion of 110, fig 4A) of the etching target structure through the opening (opening in 120) to form a first hole (D2, fig 4A)[0024] in the etching target structure (110, fig 4A);
forming a conductive polymer layer (115, fig 4A) [to cover the etching target structure inside (120, fig 4A) the first hole (D2) in a plasma atmosphere [0021, 0032-0033]; and
second etching (one more cycle of the etch, fig 4A)[0027] another portion (bottom of D2, fig 4B) of the etching target structure (120) through the first hole (D2, fig 4B) covered by the conductive polymer layer (115) inside the first hole (D2), in a state in which current flows through the conductive polymer layer in a plasma atmosphere to form a second hole (D3, fig 4B) in the etching target structure (120, fig 5A), the second hole (D3) extending from the first hole (D2) toward the substrate (120),
wherein the first etching (fig 4A) [0022,0039], the forming the conductive polymer (115, fig 4A) [0022,0039] and the second etching (fig 4A-4B) [0027, 0039] are performed in-situ in a reaction chamber of a plasma etching apparatus [0023].
Tokashiki does teach forming a first hole, in the etching target structure at a temperature between 20°C and 100°C and second etching another portion of the etching target structure through the first hole at a temperature 20°C and 100°C .
Kiehlbauch does teach forming a first hole (initial etching exposed part of ILD fig 3-6),in the etching target structure (130, fig 3) at a temperature between 20°C and 100°C and second etching another portion (130, fig 5-6 subsequently etching exposed part of the ILD layer, fig 3-6) of the etching target structure (130, fig 5-6) through the first hole (150, fig 4) at a temperature 20°C and 100°C. (about 50°C) [0048] .
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Kiehlbauch into the structure of Tokashiki to include forming a first hole ,in the etching target structure at a temperature between 20°C and 100°C and second etching another portion of the etching target structure through the first hole at a temperature 20°C and 100°C as claimed. It has been held that wherein the general condition of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
The ordinary artisan would have been motivated to modify Tokashiki based on the teaching of Kiehlbauch in the above manner for the purpose of achieving improved profile control of the opening.[0038].
Furthermore, it has been held in that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Re claim 2 Tokashiki in view of Kiehlbauch teach the method of claim 1, wherein the first etching and the second etching each are performed by an etching process using plasma (the HAR openings 105 are formed by an etch process such as by anisotropic etch process e.g. a plasma based etch process) [0023].
Re claim 5 Tokashiki in view of Kiehlbauch teach, the method of claim 1, wherein the forming the conductive polymer layer comprises supplying precursors of a conductive polymer onto the substrate (in 110, on the substrate, fig 4A) in a plasma atmosphere, and the precursors comprise a compound including a C5-C30 (poly(3.4- ethylenedioxytmophene, based on instant apphcation specification} substituted or unsubstituted aromatic ring. [0031], (C4H3S1) [Tokashiki, 0034].
Re claim 6 Tokashiki in view of Kiehlbauch teach, the method of claim 1, wherein the forming the conductive polymer layer comprises supplying precursors of a conductive polymer onto the substrate (in 110, on the substrate, fig 4A) in a plasma atmosphere, the precursors include at least one of thiophene (C4H3S1) [0034]., 3-alkyl thiophene, aniline, phenylvinyl sulfone (to form the sulfur-containing material as the protective material 115, the plasma may be used) [0034], ortho-xylylene, meta-xylylene, para-xylylene, pyrrole, phenylene vinylene, phenylene, or derivatives thereof. [Tokashik1, 0034].
Re claim 8 Tokashiki teaches a method of manufacturing an integrated circuit device(4A-6), the method comprising:
forming an insulating structure (110, fig 4A) [0018] on a substrate (substrate not shown) [0018];
forming, on the insulating structure(110, fig 4A) [0018], an etching mask pattern (120, fig 4A) [0018] having an opening (opening in 120); and
anisotropically etching [0023] the insulating structure (110, fig 4A) [0018] through the opening to form a vertical hole (105, fig 5B) [0027] , the vertical hole (105, fig 5B) [0027] passing through the insulating structure (110, fig 4A) [0018],
wherein the anisotropically etching comprises [0023], etching a portion (top portion of 110, fig 4A) [0018] of the insulating structure through the opening to form a preliminary hole (D2, fig 4B) [0018] in the insulating structure (110, fig 4A).
forming a first conductive polymer layer (115, fig 4B) [0021] to cover the insulating structure (110, fig 4B) inside the preliminary hole (D2, fig 4B) [0021] in a plasma atmosphere [0021, 0023], and
subsequently to the forming the first conductive polymer layer (115, fig 4B) [0018], repeating at least once a cycle comprising sequentially performing etching another portion (bottom of D2, fig 4B-5A) of the insulating structure (110, fig 4B) covered by the first conductive polymer layer inside the preliminary hole (D2, fig 4B), in a state in which current flows through the first conductive polymer layer (115, fig 4B) [0018, 0021] in a plasma atmosphere [0021], and forming a second conductive polymer layer (fig 5B) [0027],
wherein the etching the portion top of 110) of the insulating structure (110, fig 4A) and the forming the first conductive polymer layer (115, fig 4B) are performed in-situ [0023] in a reaction chamber of a plasma etching apparatus.[0039].
Tokashiki do not teach forming a preliminary hole ,in the etching target structure at a temperature between 20°C and 100°C.
Kiehlbauch teaches forming a preliminary hole (initial etching, fig 4), in the etching target structure (130, fig 4) at a temperature between 20°C and 100°C.(about 50 °C) [0049].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Kiehlbauch into the structure of Tokashiki to include as claimed. It has been held that wherein the general condition of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
The ordinary artisan would have been motivated to modify Tokashiki based on the teaching of Kiehlbauch in the above manner for the purpose of achieving improved profile control of the opening.[0038].
Furthermore, it has been held in that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Re claim 10 Tokashiki in view of Kiehlbauch teach the method of claim 8, wherein the insulating structure (110, fig 5B) comprises an oxide film. [Tokashiki, 0019].
Re claim 11 Tokashiki in view of Kiehlbauch teach the method of claim 8, wherein the insulating structure (110, fig 5B) comprises a plurality of silicon oxide films and a plurality of silicon nitride films, which are alternately stacked one by one in a vertical direction.(110 a stack of alternating silicon oxide and silicon nitride materials) [Tokashiki, 0019].
Re claim 12 Tokashiki in view of Kiehlbauch teach the method of claim 8, wherein the etching the portion of the insulating structure (110, fig 4A) is performed using plasma [0023] obtained from an etching gas mixture comprising a fluorinated hydrocarbon compound (the etch gas may be a thiorocarbon-hased (CP, or CHyP,) [Tokashiki, 0023].
Re claim 13 Tokashiki in view of Kiehlbauch teach the method of claim 8, further comprising:after the anisotropically etching [Tokashiki, 0023], forming a channel structure(125, fig 6) [0044] inside the vertical hole (105, fig 5B, and 6) [Tokashiki, 0044].
Re claim 19 Tokashiki teaches, a method of manufacturing an integrated circuit device (4A-5B), the method comprising:
forming an insulating structure (110, fig 4A) [0018] on a substrate(substrate not shown, fig 4A) [0018];
forming, on the insulating structure (110, fig 4A), an etching mask pattern (120, fig 4A) having an opening (opening in 120, fig 4A); and
anisotropically etching [0023] the insulating structure (110, fig 4A) [0018] through the opening (opening in 120) to form a vertical hole (105, fig 5B) [0018], the vertical hole passing through the insulating structure (110, fig 4A),
wherein the anisotropically etching comprises,
etching a portion (top of 110, fig 4A) [0023] of the insulating structure through the opening (opening in the 120, fig 4A) in a first plasma atmosphere [0023] to form a first hole (D2, fig 4B) in the insulating structure (110),
forming a conductive polymer layer (115, fig 4B-5B) [0020] by supplying a conductive polymer or precursors (protective material precursor) [0021, 0023] of the conductive polymer onto the substrate in a second plasma atmosphere [0021] ,
the conductive polymer layer (115, fig 4B-5B) covering sidewalls of the insulating structure (110, fig 4B) inside the first hole (D2, fig 4B) [0021, 0023], and
etching another portion (bottom of D2, fig 5A) of the insulating structure (110, fig 4C) through the first hole (D2), in a state in which current flows through the conductive polymer layer (115, fig 5A-5B) [0027] in a third plasma atmosphere [0021], to form a second hole (D3, fig 5B) in the insulating structure (115, fig 5B), the second hole (D3, fig 5B) extending from the first hole (D2) toward the substrate in a vertical direction (see fig 4A-5B),
wherein the etching (fig 4A) the portion (top of 110, fig 4A) of the insulating structure (110, fig 4A), the forming conductive polymer layer (115, fig 4B) and etching another portion (bottom of D2, fig 4B) [0027, 0039] of the insulating structure (115, fig 5A) are performed in-situ in a reaction chamber of a plasma etching apparatus [0023, 0039].
wherein the first etching (fig 4A) [0022,0039], the forming the conductive polymer (115, fig 4A) [0022,0039] and the second etching (fig 4A-4B) [0027, 0039] are performed in-situ in a reaction chamber of a plasma etching apparatus [0023].
Tokashiki do not teaches, etching a portion of the insulating structure to form a first hole at temperature a temperature between 20°C and 100°C.and etching another portion of the insulating structure at a temperature between 20°C and 100°C.to form a second hole.
Kiehlbauch does teach, etching a portion of the insulating structure to form a first hole (initial etching, fig 4), at temperature a temperature between 20°C and 100°C.and etching another portion of the insulating structure (subsequently etching exposed part of the ILD layer, fig 4-6) at a temperature between 20°C and 100°C.to form a second hole [0049].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Kiehlbauch into the structure of Tokashiki to include etching a portion of the insulating structure to form a first hole at temperature a temperature between 20°C and 100°C.and etching another portion of the insulating structure at a temperature between 20°C and 100°C.to form a second hole as claimed. It has been held that wherein the general condition of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
The ordinary artisan would have been motivated to modify Tokashiki based on the teaching of Kiehlbauch in the above manner for the purpose of achieving improved profile control of the opening.[0038].
Furthermore, it has been held in that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claims 4 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Tokashiki modified by Kiehlbaucas applied to claims 1 and 8 further in view of Von et al (WO 2011104500 A1).
Re claim 4 Tokashiki in view of Kiehlbaucas teach, the method of claim 1, wherein the forming the conductive polymer layer comprises: supplying precursors (C4H3S1) [0034] of a conductive polymer (115, fig 4B) [0029] onto the substrate in a plasma atmosphere (plasma is used during the protective material 115 deposition, fig 4B) [0021, 0034]; and forming the conductive layer [0024].
Tokashiki in view of Kiehlbaucas do not teach forming by plasma-polymerizing the precursors.
Von does teach forming the layer (4, plasma-polymerized polymer, fig 8) [page 3, para 6] by plasma-polymerizing the precursors (one or more precursor compounds) [Page 7, para 6].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Von into the process of Tokashiki and Kiehlbaucas to include forming by plasma-polymerizing the precursors as claimed.
The ordinary artisan would have been motivated to modify Tokashiki and Kiehlbaucas based on the teaching of Von in the above manner for the purpose of cost effective.
Re claim 17 Tokashiki in view of Kiehlbauch teach the method of claim 8, wherein the forming a conductive polymer layer (115, fig 4B) [0018] comprises:
supplying precursors of a conductive polymer onto the substrate (top of substrate in 110, fig 4B) in aplasma atmosphere (115 is formed from a precursor (€4H3S) ofa conductive polymer, the plasma remains present during the formation of 115) [0029]; and wherein the precursors comprise a compound including a C5-C30_ substituted on unsubstituted aromatic ring (poly(thiophene), such as poly(3,4- ethylenedioxythiophene), —poly(pyrrole), or poly(3-thiopheneacetic acid) [0031] and forming the conductive layer (115, fig 4B) [0023].
Tokashiki and Kiehlbauch teach forming the layer by plasma-polymeriz ing the precursors.
Von does teach forming the layer (4, plasma-polymerized polymer, fig 8) [page 3, para 6] by plasma-polymerizing the precursors (one or more precursor compounds) [Page 7, para 7].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Von into the process of Tokashiki and Kiehlbauch to include forming by plasma-polymerizing the precursors as claimed.
The ordinary artisan would have been motivated to modify Tokashiki and Kiehlbauch based on the teaching of Von in the above manner for the purpose of cost effective, easy to deposit and relatively cheap [Page 2 para 5]. Furthermore, since all the claimed elements were known in the prior art, and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, the combination would have yielded nothing more than predictable results to one of ordinary skill in the art. KSR Int’s Co.v.Teleflex Inc., 550 U>S> 538, 416, 82 USPQ2d 1385, 1395 (2007).
Claims 7, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Tokashiki modified by Kiehlbaucas in view of Winter-Jensen et al (US 20070202612A1).
Re claim 7 Tokashiki in view of Kiehlbaucas teach, the method of claim 1,
Tokashiki and Kiehlbaucas do not teach the forming a conductive polymer layer comprises supplying a conductive polymer including a C5-C30 substituted or unsubstituted aromatic ring onto the substrate.
Winter-Jensen teaches, the forming a conductive polymer layer (fig 5) [0154] comprises supplying a conductive polymer (poly-(3,4-ethylenedioxythiophene) [0090] [0154] including a C5-C30 substituted or unsubstituted aromatic ring onto the substrate (Si, wafer) [0155].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Winter-Jensen into the process of Tokashiki and Kiehlbaucas to include the forming a conductive polymer layer comprises supplying a conductive polymer including a C5-C30 substituted or unsubstituted aromatic ring onto the substrate as claimed.
The ordinary artisan would have been motivated to modify Tokashiki and Kiehlbaucas based on the teaching of Winter-Jensen in the above manner for possible simplification of the production procedure, resulting in lower coasts [0100]. Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In the instant case, the material of Winter-Jensen is suitable for conductive polymer layer of Tokashiki and Kiehlbaucas.
Re claim 18 Tokashiki in view of Kiehlbaucas teach, the method of claim 8,
Tokashiki and Kiehlbaucas do not teach the forming the conductive polymer layer comprises supplying a conductive polymer including a C5-C30 substituted or unsubstituted aromatic ring onto the substrate.
Winter-Jensen teaches, the forming the conductive polymer layer (fig 5) [0154] comprise supplying a conductive polymer (poly-(3,4-ethylenedioxythiophene) [0090] [0154] including a C5-C30 substituted or unsubstituted aromatic ring onto the substrate (Si wafer) [0155].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Winter-Jensen into the process of Tokashiki and Kiehlbaucas to include the forming the conductive polymer layer comprises supplying a conductive polymer including a C5-C30 substituted or unsubstituted aromatic ring onto the substrate as claimed.
The ordinary artisan would have been motivated to modify Tokashiki and Kiehlbaucas based on the teaching of Winter-Jensen in the above manner for possible simplification of the production procedure, resulting in lower coasts [0100].
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In the instant case, the material of Winter-Jensen is suitable for conductive polymer layer of Tokashiki and Kiehlbaucas.
Re claim 20 Tokashiki in view of Kiehlbauch teaches the method of claim 19,
Tokashiki and Kiehlbauch do not teach the conductive polymer layer comprises a conductive polymer including a C5-C30 substitute or unsubstituted aromatic ring.
Winter-Jensen teaches, the forming the conductive polymer layer (fig 5) [0154] comprise supplying a conductive polymer (poly-(3,4-ethylenedioxythiophene) [0090] [0154] including a C5-C30 substituted or unsubstituted aromatic ring onto the substrate (Si wafer) [0155].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Winter-Jensen into the process of Tokashiki and Kiehlbauch to include the forming the conductive polymer layer comprises supplying a conductive polymer including a C5-C30 substituted or unsubstituted aromatic ring onto the substrate as claimed.
The ordinary artisan would have been motivated to modify Tokashiki and Kiehlbauch based on the teaching of Winter-Jensen in the above manner for possible simplification of the production procedure, resulting in lower coasts [0100].
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In the instant case, the material of Winter-Jensen is suitable for conductive polymer layer of Tokashiki and Kiehlbauch.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Tokashiki modified by Kiehlbauch as applied to claim 8 further in view of Wang et al (US20060246717A1).
Re claim 9 Tokashiki and Kiehlbauch teach the method of claim 8, wherein the anisotropically etching [0023] further comprises:
Tokashiki and Kiehlbauch do not teach supplying a first purge onto the substrate after the etching the portion of the insulating structure and before the forming a conductive polymer layer gas; and supplying a second purge gas onto the substrate after the forming a conductive polymer layer.
Wang teaches, supplying a first purge (oxygen, Hydrogen and CF4) [0022] onto the substrate (on top of 100, fig 9) after the etching the portion of the insulating structure (124, 126, 106) and before the forming a conductive polymer layer gas (oxygen gas is introduced to remove the residual of 126 and 124 before forming fig 9 and fig 10) [0021]; and supplying a second purge gas onto the substrate after the forming a conductive polymer layer (an in-situ dry cleaning process 134 is performed using oxygen, Hydrogen etc to strip the residual polymers 133, fig10 [0022-0024].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Wang into the process of Tokashiki and Kiehlbaucas to include supplying a first purge onto the substrate after the etching the portion of the insulating structure and before the forming a conductive polymer layer gas; and
supplying a second purge gas onto the substrate after the forming a conductive polymer layer as claimed.
The ordinary artisan would have been motivated to modify Tokashiki and Kiehlbaucas based on the teaching of Wang in the above manner for the purpose to enhance the performance of the device [0027].
Claims 14-15 are rejected under 35 U.S.C.103 as being unpatentable over Tokashiki modified by Kiehlbaucas as applied to claim 8 further in view of Gwak et al (Us 20150093895A1).
Re claim 14 Tokashiki in view of Kiehlbaucas teach the method of claim 8, further comprising:
after the anisotropically etching [Tokashiki 0023], forming a lower electrode of a capacitor inside the vertical hole (fig 5B).
Tokashiki, and Kiehlbaucas do not explicitly teach exposing a surface of the lower electrode by removing the insulating structure, after the forming a lower electrode.
Gwak does teach exposing a surface (top surface of 200b) [0090] of the lower electrode (200b, fig 14C) by removing the insulating structure (145, fig 14B-14C) [0170] , after the forming a lower electrode (200b, fig 14C) [0090].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Gwak into the structure of Tokashiki and Kiehlbaucas to include exposing a surface of the lower electrode by removing the insulating structure, after the forming a lower electrode as claimed.
The ordinary artisan would have been motivated to modify Tokashiki and Kiehlbaucas based on the teaching of Gwak in the above manner for the purpose of improving the capacitance of the device [0085].
Re claim 15 Tokashiki in view of Kiehlbaucas teaches, the method of claim 8, further comprising:
after the anisotropic etching [Tokashiki, 0024], performing a cleaning process to remove residue of the conductive polymer layer [Tokashiki, 0038] from a resultant structure comprising the vertical hole (D1, fig 6) [Tokashiki, 0038],
Tokashiki, and Kiehlbaucas do not teach the cleaning process is performed by wet process using a hydrogen fluoride (HF) solution.
Gwak does teach the cleaning process is performed by wet process using a hydrogen fluoride (HF) solution. (performing wet etching process using an etchant including HF) [0007].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Gwak into the structure of Tokashiki and Kiehlbaucas to include the cleaning process is performed by wet process using a hydrogen fluoride (HF) solution as claimed.
The ordinary artisan would have been motivated to modify Tokashiki and Kiehlbaucas based on the teaching of Gwak in the above manner for the purpose of improving the capacitance of the device [0085].
Claim 16 is rejected under 35 U.S.C.103 as being unpatentable over Tokashiki modified by Kiehlbaucas as applied to claim 8 further in view of Shim et al (US 20070077757A1).
Re claim 16 Tokashiki in view of Kiehlbaucas teach the method of claim 8, further comprising:
after the anisotropically etching [Tokashiki, 0023], performing a cleaning process to remove residue of the conductive polymer layer from a resultant structure (fig. 6) [Tokashiki, 0038] comprising the vertical hole (105, fig 6) [Tokashiki, 0038], (115 removed by low level of oxygen during the subsequent processing acts) [Tokashiki, 0038].
Tokashiki, and Kiehlbaucas do not explicitly teach the cleaning process is performed by a dry process using O2 plasma.
Shim does teach “ a dry cleaning maybe performed to remove the residues. If a dry cleaning 1s performed , oxygen plasma may be used”.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Shim into the process of Tokashiki and Kiehlbaucas to include the cleaning process is performed by a dry process using O2 plasma as claimed.
The ordinary artisan would have been motivated to modify Tokashiki and Kiehlbaucas based on the teaching of Shim in the above manner for doing so it is possible to significantly increase a manufacturing yield. [0089]. Furthermore, since all the claimed elements were known in the prior art, and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, the combination would have yielded nothing more than predictable results to one of ordinary skill in the art. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 538, 416, 82 USPQ2d 1385, 1395 (2007).
Alternative Rejection
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Bera et al (US 20090081876A1) in view of Kiehlbauch et al (US20080057724A1).
Re claim 1 Bera teaches, a method of manufacturing an integrated circuit device (8A-8H), the method comprising:
forming an etching target structure (102, fig 1) [0005] on a substrate (substrate) [0005];
forming, on the etching target structure (102, fig 1) [0005], an etching mask pattern (106, shown in fig 4-6) having an opening (104, fig 1);
first etching a portion (top portion of 102, fig 1) [0023] of the etching target structure (102) to form a first hole (100, fig 1) in the etching target structure (102, fig 1);
forming a conductive polymer layer (130, fig 5) [0024] to cover the etching target structure (120) [0024] inside the first hole (100, fig 5 and fig 8A) in a plasma atmosphere [0024] ; and
second etching another portion (additional section) [0023] of the etching target structure (120) [0024] through the first hole (see fig 5, 8C) covered by the conductive polymer layer (130) inside the first hole (100, fig 8A), in a state in which current flows through the conductive polymer layer (charges in the layer 130 to flow) [0024] in a plasma atmosphere to form a second hole (fig 8C) [0027] in the etching target structure (120), the second hole extending from the first hole toward the substrate (see fig 8A-8C),
wherein the first etching, the forming the conductive polymer (130) [0024] and the second etching are performed in-situ (into the chamber to generate plasma) [0005] in a reaction chamber of a plasma etching apparatus [0005].
Bera does not teach forming a first hole, in the etching target structure at a temperature between 20°C and 100°C and second etching another portion of the etching target structure through the first hole at a temperature 20°C and 100°C .
Kiehlbauch does teach forming a first hole (initial etching exposed part of ILD fig 3-6),in the etching target structure (130, fig 3) at a temperature between 20°C and 100°C and second etching another portion (130, fig 5-6 subsequently etching exposed part of the ILD layer, fig 3-6) of the etching target structure (130, fig 5-6) through the first hole (150, fig 4) at a temperature 20°C and 100°C (about 50°C) [0049] .
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Kiehlbauch into the structure of Bera to include forming a first hole, in the etching target structure at a temperature between 20°C and 100°C and second etching another portion of the etching target structure through the first hole at a temperature 20°C and 100°C as claimed. It has been held that wherein the general condition of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
The ordinary artisan would have been motivated to modify Bera based on the teaching of Kiehlbauch in the above manner for the purpose of achieving improved profile control of the opening.[0038].
Furthermore, it has been held in that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Doan et al (US 20100330805A1) in view of Kiehlbauch et al (US20080057724A1).
Re claim 1 a method of manufacturing an integrated circuit device (4A-4C), the method comprising:
forming an etching target structure (404, fig 4A) [0030] on a substrate [0030];
forming, on the etching target structure (404, fig 4A), an etching mask pattern (406, fig 4A) [0030] having an opening (408, fig 4A) [0030];
first etching [0031] a portion of the etching target structure (404, fig4A) through the opening (408, fig 4A) to form a first hole (410, fig 4A) [0031] in the etching target structure (404, fig 4A);
forming a conductive polymer layer (416, fig 4B) [0032] to cover the etching target structure (404, fig 4B) inside the first hole (410, fig 4A) in a plasma atmosphere ; and
second etching another portion (fig 4C) [0038] of the etching target structure (404) through the first hole (fig 4B) [0032] covered by the conductive polymer layer (416) inside the first hole (fig 4B), in a state in which current flows [0032] through the conductive polymer layer (416) in a plasma atmosphere [0035] in a state in which the etching target structure (404) is covered by the conductive polymer layer (416) in a plasma atmosphere, to form a second hole (fig 4C) in the etching target structure (404), the second hole extending from the first hole toward the substrate (fig 4B-4C) [0032],
wherein the first etching (fig 4A), the forming the conductive polymer (416) and the second etching (fig 4B-4C) are performed in-situ in a reaction chamber of a plasma etching apparatus.[0035].
Doan does not teach forming a first hole, in the etching target structure at a temperature between 20°C and 100°C and second etching another portion of the etching target structure through the first hole at a temperature 20°C and 100°C .
Kiehlbauch does teach forming a first hole (initial etching exposed part of ILD fig 3-6),in the etching target structure (130, fig 3) at a temperature between 20°C and 100°C and second etching another portion (130, fig 5-6 subsequently etching exposed part of the ILD layer, fig 3-6) of the etching target structure (130, fig 5-6) through the first hole (150, fig 4) at a temperature 20°C and 100°C (about 50°C) [0049] .
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Kiehlbauch into the structure of Doan to include forming a first hole, in the etching target structure at a temperature between 20°C and 100°C and second etching another portion of the etching target structure through the first hole at a temperature 20°C and 100°C as claimed. It has been held that wherein the general condition of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
The ordinary artisan would have been motivated to modify Doan based on the teaching of Kiehlbauch in the above manner for the purpose of achieving improved profile control of the opening.[0038].
Furthermore, it has been held in that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/PRATIKSHA JAYANT LOHAKARE/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 10/18/25