DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, per page 7, filed November 12, 2025, with respect to the title have been fully considered and are persuasive. The objection of August 12, 2025 has been withdrawn.
Applicant’s arguments, per page 7, filed November 12, 2025, with respect to claim 2 have been fully considered and are persuasive. The objection of August 12, 2025 has been withdrawn.
Applicant’s arguments, per pages 7-8, filed November 12, 2025, with respect to claims 6-7 have been fully considered and are persuasive. The 112 rejection of August 12, 2025 has been withdrawn.
Applicant's arguments filed November 12, 2025 have been fully considered but they are not persuasive.
Regarding Claim 1, applicant amends the claim to now include the limitation “and wherein the compensation layer is disposed below the stack structure” and asserts that Chang does not disclose this limitation since compensation layer 35a of Chang extends through stack and therefore cannot be considered disposed below the stack. However, this limitation does not prevent the compensation layer from extending through the stack structure and it also does not require that the entire compensation layer is below the stack structure. As such, Chang Fig. 3 still reads on this amendment as a portion of 35a is disposed below stack as explained in the updated rejection below. Similarly, Claim 20 is amended with the same limitations as claim 1 and is not found persuasive for the same reasons.
Status of the Claims
Claims 11-19 are canceled. Claims 1-2, 6-7, and 20 are amended. Claims 1-10, and 20-29 are present for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-5, 8, 10, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang (US 2012/0199897). Claim 1, Chang discloses (Fig. 3) a memory device comprising: a source structure (5/43, semiconductor layer/first impurity implantation regions, Para [0073]); and a stack structure (21a-27a/47, interlayer insulation patterns/conductive patterns, [0074], hereinafter “stack”) over the source structure (stack is over 5/43), the stack structure (stack) including a plug (33/37a/39a, gate insulation layer/ second sub active pattern/inner insulation patterns, Para [0084], [0086], hereinafter “plug”) and a slit (50/54/52a, isolating insulation pattern/metal silicide layer, Para [0076]), wherein the slit includes a source contact (52a) being connected to the source structure (C52a is connected to 43, Para [0076]), wherein a region (region where plug and 5/43 overlap, hereinafter “region”) in which the plug (plug) and the source structure (5/43) overlap with each other includes a compensation layer (35a, first sub active pattern may be doped polysilicon, Para [0082])), the compensation layer (35a) includes a first concentration of an impurity (since 35a is doped would contain a first concentration of the first impurity of the dopant) and the source structure (5/43) includes a second concentration of the impurity (5 is polysilicon which is not doped, Para [0070]) , and the first concentration is greater than the second concentration (since 35a is doped and 5 is undoped, 35a would have greater concentration of dopant than 5), and wherein the compensation layer (35a) is disposed below the stack structure (a lower portion of 35a is disposed below stack). Claim 2, Chang discloses (Fig. 3) the memory device of claim 1, wherein the compensation layer (35a), which is in contact with the plug (35a is in contact with plug), is formed at a portion inside the source structure (35a is formed inside 5/43). Claim 4, Chang discloses (Fig. 3) the memory device of claim 1, wherein the plug (plug) is formed inside a plug hole (hole of plug inside of stack, hereinafter “phole”) penetrating the stack structure (phole penetrates stack) and a landing hole (hole of plug inside of 5/43, hereinafter “lhole”) penetrating a portion of the source structure (lhole penetrates a portion of 5/43). Claim 5, Chang discloses (Fig. 3) the memory device of claim 4, wherein the plug (plug) includes: a core pillar (39a, inner insulation patterns, Para [0074]) formed inside the plug hole and the landing hole (39a is formed inside phole and lhole); a channel layer (37a, second sub active patterns, Para [0086]) surrounding the periphery of the core pillar (37a surrounds periphery of 39a); and a memory layer (33, gate insulation layer comprising charge trapping, Para [0068]) surrounding the periphery of the channel layer (33 surrounds periphery of 37a). Claim 8, Chang discloses (Fig. 3) the memory device of claim 5, wherein the core pillar (39a) and the channel layer (37a) extend from an uppermost end to a lowermost end of the plug (both 39a and 37a extend from an uppermost end to a lowermost end of plug). Claim 10, Chang discloses (Fig. 3) the memory device of claim 1, wherein the stack structure (stack) includes conductive layers (47, conductive patterns, Para [0074]) and interlayer insulating layers (21a-27a, interlayer insulation patterns, Para [0074]), which are alternately stacked (47 and 21a-27a are alternately stacked).
Claim 20, Chang discloses (Fig. 3) a memory device comprising: a first source layer (5/43, semiconductor layer/first impurity implantation regions, Para [0073]); a stack structure (21a-27a/47, interlayer insulation patterns/conductive patterns, [0074], hereinafter “stack”) over the first source layer (stack is over 5/43); a plug (33/37a/39a, gate insulation layer/ second sub active pattern/inner insulation patterns, Para [0084], [0086], hereinafter “plug”) penetrating the stack structure (plug penetrates stack) and extending into the first source layer (plug extends into 5/43); and a first compensation layer (35a, first sub active pattern may be doped polysilicon, Para [0082]) disposed between the first source layer and the plug (35a is disposed between 5/43 and 33 of plug) wherein the first compensation layer includes a first concentration of an impurity (since 35a is doped would contain a first impurity of the dopant) and the first source layer includes a second concentration of the impurity (5 is polysilicon which is not doped, Para [0070]), and the first concentration is greater than the second concentration (since 35a is doped and 5 is undoped, 35a would have greater concentration of dopant than 5), and wherein the compensation layer (35a) is disposed below the stack structure (a lower portion of 35a is disposed below stack).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2012/0199897) as applied to claim 1 above, and further in view of Yang (US 2016/0027796).
Claim 3, Chang discloses the memory device of claim 1. Chang does not explicitly disclose wherein the impurity includes one of phosphorous and boron ion. However, Yang discloses (Fig. 2A) an active region (124, second channel layer, Para [0054]) which may include boron or phosphorous dopant (Para [0054]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing
date of the claimed invention to apply the teachings of Yang, including the specific material of boron or phosphorous dopant to the teachings of Chang.
The motivation to do so is that the combination yields the predictable results of allowing for the
selection of a known material based on its suitability for the intended use as a channel layer. Sinclair
& Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also MPEP 2144.07.
As a result, 35a can be polysilicon doped phosphorous or boron. Claim 9, Chang discloses the memory device of claim 1. Chang does not explicitly disclose wherein the source structure comprises poly-silicon containing the impurity. However, Chang discloses (fig. 3) wherein the source structure (5/43) comprises poly-silicon containing an impurity (43 can be polysilicon layer 5 with n-type impurities, Para [0073]). Furthermore, Yang discloses (Fig. 2A) an active region (124, second channel layer, Para [0054]) which may include a phosphorous dopant for an n-type (Para [0054]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing
date of the claimed invention to apply the teachings of Yang, including the specific material of boron or phosphorous dopant to the teachings of Chang.
The motivation to do so is that the combination yields the predictable results of allowing for the
selection of a known material based on its suitability for the intended use as a channel layer. Sinclair
& Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also MPEP 2144.07.
As a result, 35a can be polysilicon doped with phosphorous with n-type impurity and 43 can also contain phosphorous as it is n-type.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2012/0199897) as applied to claim 1 above, and further in view of Cui (US 2021/0257379). Claim 6, Chang discloses the memory device of claim 5. Chang does not explicitly disclose wherein, in the region in which the source structure and the plug overlap with each other, a first portion of the memory layer is isolated from a second portion of the memory layer in a vertical direction.
However, Cui discloses (Fig. 18) a first portion (topmost portion of 154, hereinafter “p1”) of a memory layer (154, discrete charge storage element, Para [0161]) is isolated from a second portion (p1 is isolated from p2) portion (bottommost portion of 154, hereinafter “p2”) of the memory layer in a vertical direction (p1 is isolated from p2 in a vertical direction). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing
date of the claimed invention to apply the discrete charge storage elements of Cui to charge storage layer of Chang because discrete charge storage elements can result in better programming efficiency and high program slope (Cui, Para [0161]).
Allowable Subject Matter
Claims 7 and 21-29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The following is an examiner’s statement of reasons for allowance: the closest prior art of record,
Regarding Claim 7, the compensation layer is formed between the first portion of the memory layer and the source structure and between the second portion of the memory layer and the source structure.
Regarding Claim 21 (from which claims 22-29 depend), a second source layer disposed between the first source layer and the stack structure; a third source layer disposed between the first source layer and the second source layer; and a second compensation layer disposed between the second source layer and the plug.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Liu (US 2012/0275220) discloses discrete charge storage allows for localized storage which allows for multi-bit storage (Para [0004]).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/G.G.R/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812