DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/02/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claims 1-6 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over CHI et al. (US PGpub: 2015/0287605 A1), herein after CHI, in view of Chang et al. (US PGpub: 2023/0118779 A1), herein after Chang.
Regarding claim 1, CHI teaches a transistor comprising:
a source and a drain (480) on a substrate;
a channel structure to couple the source to the drain (channel is created between source and drain. Semiconductor layer 410c can be considered channel layer);
a gate (440) separated from the channel structure by an insulating region (420a), the insulating region (420a) being a gate dielectric contacting the gate and the channel structure (see below Figure); and
a dielectric region (410b) extending from the channel structure vertically downward into the substrate and disposed between the source and the drain to reduce leakage current paths between the source and the drain.
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CHI does not explicitly teach source and a drain in a substrate and the dielectric region laterally separated from the source and the drain by material of the substrate extending vertically up to the channel structure such that the dielectric region does not contact the source and does not contact the drain.
However, Chang teaches source and a drain (260B) in a substrate (202). Also, the insulating region (420a) being a gate dielectric (gate structure 240 includes a dummy gate stack 245…. gate stacks 245 include a dummy gate dielectric disposed between the dummy gate electrode and fins 218A, 218B, the dummy gate dielectric includes a dielectric material, such as silicon oxide, a high-k dielectric material, other suitable dielectric material, or combinations thereof. Examples of high-k dielectric material include HfO.sub.2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, hafnium dioxide-alumina (HfO.sub.2—Al.sub.2O.sub.3) alloy, other suitable high-k dielectric materials, or combinations thereof. In some embodiments, the dummy gate dielectric includes an interfacial layer (including, for example, silicon oxide) disposed over fins 218A, 218B and a high-k dielectric layer disposed over the interfacial layer. Dummy gate stacks 245 can include numerous other layers, for example, capping layers, interface layers, diffusion layers, barrier layers, hard mask layers, or combinations thereof. For example, dummy gate stacks 245 can further include a hard mask layer disposed over the dummy gate electrode. Paragraph [0042]-[0043]) contacting the gate and the channel structure. Also, the dielectric region (255, part of 255 is separated from 260B) laterally separated from the source and the drain by material of the substrate (255, part of 255 is separated from 260B by 202 as well) extending vertically up to the channel structure such that the dielectric region does not contact the source and does not contact the drain (255 is extended up and side portion of 255 does not contact 260B).
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Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use CHI’s transistor with other teaching from Chang in order to optimize respective device performance, including reduced parasitic capacitance and reduced contact resistance. Particularly, the GAA transistors include S/D features with a bar-like profile or lollipop-like profile for and adjacent airgap to collectively reduce the parasitic capacitance and the contact resistance according to various embodiments.
Regarding claim 2, CHI teaches the transistor of claim 1, wherein the dielectric region includes a crystalline semiconductor region within dielectric material (Paragraph [0044]-[0048]).
Regarding claim 3, CHI teaches the transistor of claim 2, wherein the crystalline semiconductor region includes epitaxial silicon, and the dielectric material includes an electrically insulating oxide (Paragraph [0044]-[0048]).
Regarding claim 4, CHI teaches the transistor of claim 2, wherein material of the channel structure and material of the crystalline semiconductor region have a common composition (Paragraph [0044]-[0048]).
Regarding claim 5, CHI teaches the transistor of claim 1, wherein the dielectric region (410b) is structured without conductive material or semiconductive material within the dielectric region (buried insulating layer).
Regarding claim 6, CHI teaches the transistor of claim 1, wherein the dielectric region extends downward into the substrate to a level lower than a level at which the source extends into the substrate and lower than a level at which the drain extends into the substrate (FIG. 5).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached M-F, 8am-6pm EDT.
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/SHEIKH MARUF/Primary Examiner, Art Unit 2897
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