DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/25/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6, 9 are rejected under 35 U.S.C. 103 as being unpatentable over McKitterick (US 5,789,781) in view of Cassata et al. (US 2015/0003503).
Regarding Claim 1, McKitterick discloses device (Figures 4-5, 6, Figures 4-5 shows a device comprising two symmetric transistors, Figure 6 shows transistor pairs connected to operate as a single symmetric transistor, please see the corresponding elements in Figure 6, for the elements in Figures 4-5 referred below in the rejection), comprising:
a diode circuit on a substrate (comprising diode circuit 26 on substrate 40, Figures 4-5) and coupled between a first input/output (I/O) pin (pin at 32, Figures 4-5) and a second I/O pin of a circuit (pin at 34, Figures 4-5), and configured to be turned off (Column 2, lines 7-9, discussing prior art and motivation for improvements “…In a Pass Gate, which is used to block current when desired, this behavior is definitely undesirable”, Column 4, lines 25-30, “semiconductor device 26 is a symmetric transistor pair…..may be used in any application requiring a pass gate”),
wherein the diode circuit is configured to provide a first discharging path from the first I/O pin to a first bulk terminal of the first transistor of the circuit and a second discharging path for the second I/O pin of the circuit (26 in Figures 4-5 functions as a pass gate, Column 4, lines 20-25, Column 2, lines 7-9, discussing prior art and motivation for improvements “…In a Pass Gate, which is used to block current when desired, this behavior is definitely undesirable”),
wherein the diode circuit comprises:
a first transistor (28, Figures 4-5) that is coupled between a node (comprising 50, Figures 4-5) and the first I/O pin (28 coupled between 50 and the pin at 32, Figures 4-5) and a second transistor (30, Figures 4-5) that is coupled between the node and the second I/O pin (30 coupled between 50 and the pin at 34, Figures 4-5),
wherein the node is configured to receive a first voltage (50 is configured to receive a voltage corresponding to a voltage at 32/34, Figures 4-5, 6), and a control terminal of the first transistor and a control terminal of the second transistor are configured to receive a second voltage (voltage applied at 48 for the device to function as a pass gate, pass current when desired and block current otherwise, Figures 4-5, 6, Column 4, lines 31-35, 66- Column 5, line 9), wherein a voltage difference between the first voltage and the second voltage is configured to turn off the first transistor and the second transistor (Column 4, lines 31-35, 66- Column 5, line 9).
wherein the interconnection structure comprises a first contact (50, Figures 4-5), and a second contact (48, Figures 4-5), the first contact is coupled to the second portion (50 over the second portion), the second contact couples the first gate structure of the first transistor to the second gate structure of the second transistor (48 couples the first gate structure 36 to the second gate structure 38, and 48 is not coupling to 50, Figures 4-5), wherein the first gate structure, the second contact, and the second gate structure form a half H-shape structure in a layout view (half of two legs and the middle cross of an H-shape as shown by 36, 38 and 48 I Figure 1).
McKitterick does not specifically disclose the first voltage being power supply voltage and the structure in the layout view is a full H-shape.
Cassata discloses a diode circuit comprising a first transistor (PD/ND, Figures 8A, 8B) that is coupled between a node and a first I/O pin (PD/ND coupled between node between PD, PS/ND,NS labelled as VP/VN and VCC/GND, Figures 8A, 8B) and a second transistor (PS/NS, Figures 8A, 8B) that is coupled between the node and the second I/O pin (PS/NS coupled between VP/VN and OUTH/OUTL, Figures 8A, 8B),
wherein the node is configured to receive a first voltage, which is power supply voltage (VP/VN is configured to receive V+/V-, Figures 8A, 8B, Paragraph 29, “..The P-type transistors of the high-side leg and the N-type transistors of the low-side leg have a respective current terminal in common, on which an internal positive voltage VP and an internal negative voltage VN, respectively, that are distributed to inner circuits of the transceiver as internal power supply, are made available”), and a control terminal of the first transistor and a control terminal of the second transistor are configured to receive a second voltage (output from OUTPUT DRIVER to the gate terminal of PD/ND and PS/NS, Figures 8A, 8B), wherein a voltage difference between the first voltage and the second voltage is configured to turn off the first transistor and the second transistor (Claim 8, “…configured to be supplied with the voltages on said internal negative and positive supply voltage lines and to turn on/off said two P-type and two N-type transistors to allow transmission on the digital data wire”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to select the first voltage as a power supply voltage such that the first voltage can be applied relative to the second voltage based on the type of transistors in the diode circuit and form an H-shape structure in the layout view by shifting the positioning of the second contact relative to the first and second gate structure based on the space and size requirements of the device.
Regarding Claim 2, combination of McKitterick and Cassata discloses the device of Claim 1, wherein the first discharging path is from the first I/O pin to a bulk terminal of the first transistor for discharging excess charges accumulated on the first I/O pin (forward biased source-body junction of 28 providing a first discharging path from 32 to a bulk of 28, Figures 4-5, 6, Column 4, line 66 Column 5, line 9), and the second discharging path is from the second I/O pin to a bulk terminal of the second transistor for discharging excess charges accumulated on the second I/O pin (forward biased source-body junction of 30 providing a second discharging path from 34 to a bulk of 30, Figures 4-5, 6, Column 4, line 66 Column 5, line 9).
Regarding Claim 3, combination of McKitterick and Cassata discloses the device of Claim 1, wherein the first voltage and second voltage are applied to block/allow current/charge path (Column 4, line 66-Column 5, line 9). Combination of McKitterick and Cassata does not specifically disclose the first voltage higher than the second voltage. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, select the first voltage relative (higher/lower) to the second voltage based on the type of the first transistor and the second transistor.
Regarding Claim 4, combination of McKitterick and Cassata discloses the device of Claim 1, wherein the first I/O pin is coupled to circuit to provide a charge path from the circuit via the first I/O pin (Column 4, line 66-Colukmn 5, line 5). Combination of McKitterick and Cassata does not specifically disclose the first I/O pin being coupled to gates of internal transistors, and an equivalent resistance of the gate coupled to the first I/O pin is higher than an equivalent resistance of the first discharging path. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, the circuit to which the first I/O pin in the device of McKitterick connected to have MOS transistors having gate resistances (as device having MOS transistors (28, 30 in Figures 4-5)) with equivalent resistances higher than that of the discharge path of the device to aid the charge to flow via the device to protect the internal transistors.
Regarding Claim 5, combination of McKitterick and Cassata discloses the device of Claim 1, wherein the first transistor and the second transistor further comprise an active region comprising a first portion (comprising the source 32 of 28), a second portion (comprising node 50 and drains 44, 46 of 28, 30 respectively), and a third portion (comprising source 34 of 30), wherein the second portion of the active region corresponds to the node (second portion of the active region comprising/corresponding to node 50),
wherein first gate structure is over the active region and between the first portion and the second portion of the active region, and configured to operate as the control terminal of the first transistor (comprising gate structure 36),
wherein second gate structure is over the active region and between the second portion and the third portion of the active region, and configured to operate as the control terminal of the second transistor (comprising 38).
Regarding Claim 6, combination of McKitterick and Cassata discloses the device of Claim 5, wherein the second contact is without coupling to the first contact (48 couples the first gate structure 36 to the second gate structure 38, and 48 is not coupling to 50, Figures 4-5).
Regarding Claim 9, combination of McKitterick and Cassata discloses the device of Claim 5, wherein a width of the diode circuit is equal to or less than about three times a distance between the first gate structure and the second gate structure (diode circuit in Figures 4-5 is symmetric and the total width of the diode circuit is less than or equal to three times a distance between 36, 38).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over McKitterick (US 5,789,781) in view of Cassata et al. (US 2015/0003503) and Yen et al. (US 2013/0256801).
Regarding Claim 7, combination of McKitterick and Cassata does not specifically disclose the device of Claim 6, wherein the second contact and the first gate structure are in different layers.
Yen discloses a device (110, Figures 1A-1B, 2A-2C) comprising a first MOS transistor comprising a first gate structure (120 comprising 125, Figures 2A-2C) and a second MOS transistor comprising a second gate structure (130 comprising 135, Figures 2A-2C) and an interconnection structure comprising a first contact (common drain/drain connection 132, 122, Figures 2A-2C) and a second contact (common connection of gates 135, 125 to 105, Figures 2A-2C), wherein the second contact is over the first contact (second contact/common connection of gates 135, 125 over common contact to source/drain 132,122, Figures 2A-2C), and the second contact and the first gate structure are in different layers (Figures 2A-2B shows the second contact/common connection 105, M2/205 in Figure 2C and described in Paragraph 30 and the first gate structure 135 in different layers).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the second contact and the first gate structure in the combination, in different layers by forming multilayer metal layers as taught by Yen to provide isolation between signal lines to reduce noise interference.
Regarding Claim 8, combination of McKitterick and Cassata does not specifically disclose the device of Claim 6, wherein the first gate structure and the second gate structure are between the substrate and the second contact.
Yen discloses a device on a substrate (110 on substrate 101, Figures 1A-1B, 2A-2C) comprising a first MOS transistor comprising a first gate structure (120 comprising 125, Figures 2A-2C) and a second MOS transistor comprising a second gate structure (130 comprising 135, Figures 2A-2C) and an interconnection structure comprising a first contact (common drain/drain connection 132, 122, Figures 2A-2C) and a second contact (common connection of gates 135, 125 to 105, Figures 2A-2C), wherein the second contact is over the first contact (second contact/common connection of gates 135, 125 over common contact to source/drain 132,122, Figures 2A-2C), and the second contact and the first gate structure are in different layers (Figures 2A-2B shows the second contact/common connection 105, M2/205 in Figure 2C and described in Paragraph 30 and the first gate structure 135 in different layers), wherein the first gate structure and the second gate structure are between the substrate and the second contact (first gate structure 125 and second gate structure 135 are between substrate 101 and second contact 105, Figures 2A-2C). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the second contact and the gate structures in the combination, in different layers by forming multilayer metal layers, with the first gate structure and the second gate structure between the substrate and the second contact as taught by Yen to provide isolation between signal lines to reduce noise interference.
Claims 21-25, 28-31 are rejected under 35 U.S.C. 103 as being unpatentable over McKitterick (US 5,789,781).
Regarding Claim 21, McKitterick discloses device (Figures 4-5, 6, Figures 4-5 shows a device comprising two symmetric transistors, Figure 6 shows transistor pairs connected to operate as a single symmetric transistor, please see the corresponding elements in Figure 6, for the elements in Figures 4-5 referred below in the rejection), comprising:
a diode circuit on a substrate (comprising diode circuit 26 on substrate 40, Figures 4-5) and coupled between a first input/output (I/O) pin (pin at 32, Figures 4-5) and a second I/O pin of a circuit (pin at 34, Figures 4-5), and configured to be turned off (Column 2, lines 6-8, discussing prior art and motivation for improvements “…In a Pass Gate, which is used to block current when desired, this behavior is definitely undesirable”, Column 4, lines 25-30, “semiconductor device 26 is a symmetric transistor pair…..may be used in any application requiring a pass gate”),
wherein the diode circuit is configured to provide a first discharging path from the first I/O pin to a first bulk terminal of the first transistor of the circuit and a second discharging path for the second I/O pin of the circuit (26 in Figures 4-5 functions as a pass gate, Column 4, lines 20-25, Column 2, lines 7-9, discussing prior art and motivation for improvements “…In a Pass Gate, which is used to block current when desired, this behavior is definitely undesirable”),
wherein the diode circuit comprises:
a first transistor (28, Figures 4-5) that is coupled between a node (comprising 50, Figures 4-5) and the first I/O pin (28 coupled between 50 and the pin at 32, Figures 4-5) and a second transistor (30, Figures 4-5) that is coupled between the node and the second I/O pin (30 coupled between 50 and the pin at 34, Figures 4-5),
wherein the node is configured to receive a first voltage (50 is configured to receive a voltage corresponding to a voltage at 32/34, Figures 4-5, 6), and a control terminal of the first transistor and a control terminal of the second transistor are configured to receive a second voltage (voltage applied at 48 for the device to function as a pass gate, pass current when desired and block current otherwise, Figures 4-5, 6, Column 4, lines 31-35, 66- Column 5, line 9), wherein the second voltage is different from the first voltage (Column 4, line 66- Column 5, line 9),
wherein the first transistor and the second transistor comprise an interconnection structure (comprising 50, 48, Figures 4-5, Figures 4-5), the interconnection structure comprises a first contact (coupled to 50, Figures 4-5), and a second contact (48, Figures 4-5), the first contact is coupled to the node (first contact coupled to node 50, Figures 4-5), and the second contact couples a first gate structure of the first transistor to a second gate structure of the second transistor (48 couples the first gate structure 36 to the second gate structure 38, Figures 4-5),
wherein a length of the second contact is same as a width of the second gate structure, wherein the length is along a first direction and the width is along a second direction, wherein the second direction is perpendicular to the first direction (length of the second contact 48 a first/x direction is substantially same as the width of the second gate structure 38 in a second/y-direction as shown in the schematics in Figures 4-5).
McKitterick does not specifically disclose the length of the second contact being greater than the width of the second gate structure. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to adjust length of the second contact and width the second gate structure based on design requirements such as the space, size, cost and speed.
Regarding Claim 22, McKitterick discloses the device of Claim 21, wherein the first discharging path is from the first I/O pin to a bulk terminal of the first transistor for discharging excess charges accumulated on the first I/O pin (forward biased source-body junction of 28 providing a first discharging path from 32 to a bulk of 28, Figures 4-5, 6, Column 4, line 66 Column 5, line 9), and the second discharging path is from the second I/O pin to a bulk terminal of the second transistor for discharging excess charges accumulated on the second I/O pin (forward biased source-body junction of 30 providing a second discharging path from 34 to a bulk of 30, Figures 4-5, 6, Column 4, line 66 Column 5, line 9).
Regarding Claim 23, McKitterick discloses the device of Claim 21, wherein the first I/O pin is coupled to circuit to provide a charge path from the circuit via the first I/O pin (Column 4, line 66-Colukmn 5, line 5). McKitterick does not specifically disclose the first I/O pin being coupled to gates of internal transistors, and an equivalent resistance of one of the gates coupled to the first I/O pin is higher than an equivalent resistance of the first discharging path. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, the circuit to which the first I/O pin in the device of McKitterick connected to have MOS transistors having gate resistances (as device having MOS transistors (28, 30 in Figures 4-5)) with equivalent resistances higher than that of the discharge path of the device to aid the charge to flow via the device to protect the internal transistors.
Regarding Claim 24, McKitterick discloses the device of Claim 21, wherein the first transistor and the second transistor comprise an active region comprising a first portion (comprising the source 32 of 28, Figures 4-5), a second portion (comprising node 50 and drains 44, 46 of 28, 30 respectively, Figures 4-5), and a third portion (comprising source 34 of 30), wherein the second portion of the active region corresponds to the node (second portion of the active region comprising/corresponding to node 50, Figures 4-5);
wherein the first gate structure over the active region and between the first portion and the second portion of the active region, and configured to operate as the control terminal of the first transistor (comprising gate structure 36, Figures 4-5);
wherein the second gate structure over the active region and between the second portion and the third portion of the active region, and configured to operate as the control terminal of the second transistor (comprising 38, Figures 4-5).
Regarding Claim 25, McKitterick discloses the device of Claim 24, wherein the second contact is without coupling to the first contact (48 couples the first gate structure 36 to the second gate structure 38, and 48 is not coupling to 50, Figures 4-5).
Regarding Claim 28, McKitterick discloses the device of Claim 24, wherein a width of the diode circuit is equal to or less than about three times a distance between the first gate structure and the second gate structure (diode circuit in Figures 4-5 is symmetric and the total width of the diode circuit is less than or equal to three times a distance between 36, 38).
Regarding Claim 29, McKitterick discloses a method (Figures 4-7), comprising:
coupling two transistors, which are integrally at an active region and adjacent to each other, at a node and between a first input/output (I/O) pin and a second I/O pin of a circuit (Figures 4-5 shows two symmetric transistors 28, 30 adjacent to each other, node 50 and I/O pins coupled to 32, 34, Figure 6 shows transistor pairs connected to operate as a single symmetric transistor); and
turning off the two transistors, in order to provide a first discharging path for the first I/O pin and to provide a second discharging path for the second I/O pin (Column 1, line 60- Column 2, line 8, discussing prior art and Pass gates which are of interest to the disclosed invention, “…In a Pass Gate, which is used to block current when desired, this behavior is definitely undesirable”, Column 4, lines 25-30, “semiconductor device 26 is a symmetric transistor pair…..may be used in any application requiring a pass gate”), wherein the two transistors comprise a first transistor and a second transistor (first transistor 28, second transistor 30, Figures 4-5), and turning off the two transistors comprises:
transmitting a first voltage to a first terminal of the first transistor and a first terminal of the second transistor (transmitting a first voltage to first terminal 44 of 28 and 46 of 30, the first corresponding to a voltage at first/second I/O pins coupled to 32/34, Column 4, line 66-Column 5, line 9); and
transmitting a second voltage to a control terminal of the first transistor and a control terminal of the second transistor, in order to turn off the first transistor and the second transistor by a voltage difference between the first voltage and the second voltage (transmitting a second voltage to 36, 38 by applying a voltage at 48 for the device to function as a pass gate, pass current when desired and block current otherwise, Figures 4-5, 6, Column 4, lines 31-35, 66- Column 5, line 9),
wherein a second terminal of the first transistor is coupled to the first I/O pin, and a second terminal of the second transistor is coupled to the second I/O pin (32 coupled to the first I/O pin and 34 coupled to the second I/O pin, Figures 4-5),
wherein the first voltage is different from the second voltage (Column 4, line 66- Column 5, line 9, “….allowing the tied drains 74 and 76 of the NMOS transistor pair 54 to rise to the higher of the two voltages applied to the sources… other transistor of each transistor pair of 54 and 56 will either block this voltage and prevent current flow or will not block the voltage and allow current flow, depending upon the applied gate voltages),
wherein the first transistor and the second transistor comprise an interconnection structure (comprising 50, 48, Figures 4-5, Figures 4-5), the interconnection structure comprises a first contact (coupled to 50, Figures 4-5), and a second contact (48, Figures 4-5), the first contact is coupled to the node (first contact coupled to node 50, Figures 4-5), and the second contact couples a first gate structure of the first transistor to a second gate structure of the second transistor (48 couples the first gate structure 36 to the second gate structure 38, Figures 4-5),
wherein a length of the second contact is same as a width of the second gate structure, wherein the length is along a first direction and the width is along a second direction, wherein the second direction is perpendicular to the first direction (length of the second contact 48 a first/x direction is substantially same as the width of the second gate structure 38 in a second/y-direction as shown in the schematics in Figures 4-5).
McKitterick does not specifically disclose the first voltage higher than the second voltage, and the length of the second contact being greater than the width of the second gate structure. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, select the first voltage relative (higher/lower) to the second voltage based on the type of the first transistor and the second transistor and adjust length of the second contact and width the second gate structure based on design requirements such as the space, size, cost and speed.
Regarding Claim 30, McKitterick discloses the method of Claim 29, wherein the first transistor and the second transistor further comprise an active region comprising a first portion (comprising the source 32 of 28, Figures 4-5), a second portion (comprising node 50 and drains 44, 46 of 28, 30 respectively, Figures 4-5), and a third portion (comprising source 34 of 30), wherein the second portion of the active region corresponds to the first terminal of the first transistor and the first terminal of the second transistor (second portion of the active region comprising/corresponding to the first terminal 44 of 28 and first terminal 46 of 30 and coupled to node 50, Figures 4-5);
wherein the first gate structure over the active region and between the first portion and the second portion of the active region, and configured to operate as the control terminal of the first transistor (comprising gate structure 36, Figures 4-5);
wherein the second gate structure over the active region and between the second portion and the third portion of the active region, and configured to operate as the control terminal of the second transistor (comprising 38, Figures 4-5).
Regarding Claim 31, McKitterick discloses the method of Claim 30, wherein the second contact is without coupling to the first contact (48 couples the first gate structure 36 to the second gate structure 38, and 48 is not coupling to 50, Figures 4-5).
Claims 26-27 are rejected under 35 U.S.C. 103 as being unpatentable over McKitterick (US 5,789,781) in view of Yen et al. (US 2013/0256801).
Regarding Claim 26, McKitterick does not specifically disclose the device of Claim 25, wherein the second contact and the first gate structure are in different layers.
Yen discloses a device (110, Figures 1A-1B, 2A-2C) comprising a first MOS transistor comprising a first gate structure (120 comprising 125, Figures 2A-2C) and a second MOS transistor comprising a second gate structure (130 comprising 135, Figures 2A-2C) and an interconnection structure comprising a first contact (common drain/drain connection 132, 122, Figures 2A-2C) and a second contact (common connection of gates 135, 125 to 105, Figures 2A-2C), wherein the second contact is over the first contact (second contact/common connection of gates 135, 125 over common contact to source/drain 132,122, Figures 2A-2C), and the second contact and the first gate structure are in different layers (Figures 2A-2B shows the second contact/common connection 105, M2/205 in Figure 2C and described in Paragraph 30 and the first gate structure 135 in different layers).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the second contact and the first gate structure in the device of McKitterick, in different layers by forming multilayer metal layers as taught by Yen to provide isolation between signal lines to reduce noise interference.
Regarding Claim 27, McKitterick does not specifically disclose the device of Claim 25, wherein the first gate structure and the second gate structure are between the substrate and the second contact.
Yen discloses a device on a substrate (110 on substrate 101, Figures 1A-1B, 2A-2C) comprising a first MOS transistor comprising a first gate structure (120 comprising 125, Figures 2A-2C) and a second MOS transistor comprising a second gate structure (130 comprising 135, Figures 2A-2C) and an interconnection structure comprising a first contact (common drain/drain connection 132, 122, Figures 2A-2C) and a second contact (common connection of gates 135, 125 to 105, Figures 2A-2C), wherein the second contact is over the first contact (second contact/common connection of gates 135, 125 over common contact to source/drain 132,122, Figures 2A-2C), and the second contact and the first gate structure are in different layers (Figures 2A-2B shows the second contact/common connection 105, M2/205 in Figure 2C and described in Paragraph 30 and the first gate structure 135 in different layers), wherein the first gate structure and the second gate structure are between the substrate and the second contact (first gate structure 125 and second gate structure 135 are between substrate 101 and second contact 105, Figures 2A-2C). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the second contact and the gate structures in the device of McKitterick, in different layers by forming multilayer metal layers, with the first gate structure and the second gate structure between the substrate and the second contact as taught by Yen to provide isolation between signal lines to reduce noise interference.
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Response to Arguments
Applicant's arguments filed 2/25/2026 have been fully considered but they are not persuasive and/or rendered moot in view of new grounds of rejection in the current office action addressing the new limitations.
Applicant’s arguments, on Pages 8-10 of the Remarks toward the new limitations of Claim 21 and McKitterick reference are rendered moot in view of new grounds of rejection (anticipation rejection of Claim 21 using McKitterick is changed to obviousness rejection over McKitterick).
Applicant’s arguments, on Page 10 of the Remarks toward dependent Claims 22-28 are directed toward the new limitations of Claim 21, therefore please see the response to arguments toward Claim 21 above.
Applicant’s arguments, on Page 10 of the Remarks toward the new limitations of Claim 29 (same new limitation as in Claim 21) and McKitterick reference are rendered moot in view of current rejection addressing the new limitation.
Applicant’s arguments, on Page 10 of the Remarks toward dependent Claims 30-31 are directed toward the new limitations of Claim 29, therefore please see the response to arguments toward Claim 29 above.
The Applicant argues, on Pages 10-12 of the Remarks toward new limitations of Claim 1 and McKitterick reference are rendered moot in view of current rejection addressing the new limitation.
Applicant’s arguments, on Page 12 of the Remarks toward dependent Claims 2-9 are directed toward the new limitations of Claim 11, therefore please see the response to arguments toward Claim 1 above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Maeda et al. (US 6,204,536); Lue et al. (US 2015/0318273)
discloses a device (Figures 1-20), comprising: a diode circuit (for example, comprising 11, 12, Figure 1, also see corresponding elements in other Figures) coupled between a first input/output (I/O) pin (connected to the drain/source node of 10, Figure 1) and a second I/O pin (connected to the drain/source node of 11, Figure 1, it is noted that I/O pins are shown as coupled to the substrate when switched off/during manufacturing, to be coupled to the circuit to be protected) of a circuit (circuit to be protected), and configured to be turned off (Paragraphs, 42, 70-71), wherein the diode circuit is configured to provide a first discharging path for the first I/O pin of the circuit and a second discharging path for the second I/O pin of the circuit (Figures 5-6, during manufacturing provides first and second ESD discharge path, Paragraphs 41, 70-71); Chu et al. (US 9,553,508) discloses MOS transistor circuits (transistors M1, M2 and M3, M4, Figures 1-2) comprising multilayer conductors with vias for gate structure and signal transmission (CL1-CL4 and ML1-ML3 respectively in Figure 2); Lim et al. (US 2015/0293417) discloses a diode circuit (Figures 1-7) formed on a substrate (comprising 101, Figures 5A-C, 6) comprising a first transistor and a second transistor (T12, T22, Figures 2B, 3-4, 5A-C, 6) with common source/drain connection at a node (T12 and T22 with common source/drain connection at a node, Figures 2B, 3-4, 5A-C, 6) and a gate interconnection structure (comprising BL1, CC, contact between drain of T12, T22, not labelled, and the connection C2 between the contacts, Figures 2B, 3-4, 5A-C, 6) that comprises a first contact (comprising contacts between the drain of T12, T22, not labelled, Figures 2B, 3-6) and a second contact (comprising BL1, Figures 2B, 3-4, 5A-C, 6); Mallikarjunaswamy (US 2011/0127602) discloses a MOS transistor structure comprising source, drain and gate terminals and further including two dummy gates that cover two edges of the active region of the MOS transistor (Figure 7, dummy gates 428 cover the two edges of active region comprising source/drain region of the MOS transistor 410); Yamada (US 2012/0243712) discloses a device (Figures 4-5), comprising: a diode circuit formed on a substrate (comprising Mn3,D1/D4, Mn4,D2/D5 formed on a substrate, Figures 4-5, substrate not shown in Figures, recited in Paragraph 79) coupled between a first input/output (I/O) pin (IN/OUT coupled to Mn3, Figures 4-5) and a second I/O pin (IN/OUT coupled to Mn4, Figures 4-5) of a circuit (circuit being coupled to the IN/OUT terminal, Figures 4-5), and configured to be turned off (ON/OFF input to gate of Mn3, Mn4, Figures 4-5), wherein the diode circuit comprises a first transistor that is coupled to the first I/O pin (Mn3 in Figures 4-5 is a transistor) and a second transistor that is coupled to the second I/O pin (Mn4 coupled to the node and the IN/OUT pin), wherein the diode circuit is configured to provide a first discharging path from the first I/O pin to a first bulk terminal of the first transistor of the circuit (the first discharge path from the first I/O pin, IN/OUT in Figure 5 to the node via the body diode of Mn3) and a second discharging path for the second I/O pin of the circuit (Figures 4-5, Paragraph 57, “The serial circuit functions as a switch element for making the source terminals of the third n-channel MOSFET Mn3 and the fourth n-channel MOSFET Mn4 become the ground potential when the third n-channel MOSFET Mn3 and the fourth n-channel MOSFET Mn4 are OFF”); Masuoka et al. (US 2016/0013284) discloses a semiconductor device comprising MOS transistors (Figures 1A-1C), the MOS transistors including a first gate 126 and a second gate 121 and a contact 142 connecting the first gate and second gate, wherein the length of the contact in a first direction is greater than a width of the second gate in a second direction that is perpendicular to the first direction (Figure 1B).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LUCY M THOMAS whose telephone number is (571)272-6002. The examiner can normally be reached Mon-Fri 9:30 am - 5:30 pm.
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/LUCY M THOMAS/Examiner, Art Unit 2838, 4/13/2026
/CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838
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