DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/12/2025 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 3-8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1,3 and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Mathai et al. (hereinafter Mathai) (US 20180175587 A1) in view of Maros et al. (hereinafter Maros) (US 20200052137 A1)
Regarding claim 1, Mathai discloses in Fig. 2,
A semiconductor device [200] (Para. [0020]), comprising:
a substrate [204] (Para. [0020]);
a first reflector [208] (Para. [0022]) on the substrate [204];
a light emission layer [212] (Para. [0022]) on the first reflector [208], wherein the light emission layer [212] comprises active regions [216] (Para. [0023]), and
wherein each of the active regions [216] comprises a primary emission wavelength different from each other [216 in each VCSEL 202a-202d] (Para. [0020]);
second reflectors [214] (Para. [0025]) on corresponding active regions [216]; and
apertures [602 Fig. 6] (Para. [0052,0068]) on corresponding active regions [216].
Mathai fails to disclose,
wherein the light emission layer comprises a Ill-V compound semiconductor material with a nitrogen atom concentration between 0 % and 5 % of the group V materials.
Maros discloses,
A dilute nitride active layer comprising GaInNAsSb with a nitrogen atom concentration between 0% and 5% of the group V materials (Para. [0027])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the active layer material disclosed in Maros as the active layer material of Mathai for the purpose of producing a high-quality active layer lattice matched to a GaAs substrate. (Maros Para. [0027])
Regarding claim 3, Mathai in view of Maros as applied to claim 1 above further discloses in Maros,
wherein the light emission layer comprises a Ill-V compound semiconductor material with an indium atom concentration between 0 % and 20 % of the group Ill materials (Para. [0027]).
Examiner notes that lines 21-26 of the left column on page 3 discloses Ga1-xInxNyAs1-y-zSbz with the composition ranges of 0.08≤x≤0.18, 0.025≤y≤0.04 and 0.001≤z≤0.03.
Regarding claim 5, Mathai in view of Maros as applied to claim 1 above further discloses in Maros,
wherein the light emission layer comprises gallium indium nitride arsenide antimonide (GalnNAsSb) with a nitrogen atom concentration between % and 5 % of the group V materials, an indium atom concentration between 0 % and 20 % of the group Ill materials, and an antimony atom concentration between 0 % and 6 % of the group V materials (Para. [0027]).
Examiner notes that lines 21-26 of the left column on page 3 discloses Ga1-xInxNyAs1-y-zSbz with the composition ranges of 0.08≤x≤0.18, 0.025≤y≤0.04 and 0.001≤z≤0.03.
Regarding claim 6, Mathai in view of Maros as applied to claim 1 above further discloses in Fig. 2 of Mathai
wherein each of the second reflectors [214] comprises a stack of dielectric layers (Para [0025]); and wherein the stack of dielectric layers comprises a metal oxide, a metal sulfide, a metal halide, an oxynitride, or a combination thereof (Para. [0025]).
Examiner notes the term “or” used in line 4 of claim 6. For the purposes of examination in the instant application, the limitation “wherein the stack of dielectric layers comprises a metal oxide, a metal sulfide, a metal halide, oxynitrides, or a combination thereof” will be understood to read, “wherein the stack of dielectric layers comprises a metal oxide.”
Regarding claim 7, Mathai in view of Maros as applied to claim 1 above further discloses in Fig. 6 of Mathai
wherein each of the apertures [602] (Para. [0068]) comprises a Ill-V compound semiconductor material with an aluminum atom concentration between 80 % and 100 % of the group Ill materials (Para. [0069]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Mathai in in view of Maros as applied to claim 1 above and further in view of Naone et al. (hereinafter Naone) (US 20020150135 A1).
Regarding claim 4, Mathai in view of Maros discloses the device outlined in the rejection of claim 1 and further discloses in Maros,
A light emission layer comprising a semiconductor material with a nitrogen atom concentration between 0% and 5% of the group V materials (Para. [0027])
Examiner notes that lines 21-26 of the left column on page 3 discloses Ga1-xInxNyAs1-y-zSbz with the composition ranges of 0.08≤x≤0.18, 0.025≤y≤0.04 and 0.001≤z≤0.03.
Mathai in view of Maros fails to disclose,
wherein the light emission layer comprises a gallium arsenide-based dilute nitride semiconductor material with a nitrogen atom concentration between 0% and 5% of the group V materials, an indium phosphide-based dilute nitride semiconductor material with a nitrogen atom concentration between 0% and 5% of the group V materials, or a gallium phosphide-based dilute nitride semiconductor material with a nitrogen atom concentration between 0% and 5% of the group V materials; and
wherein the gallium arsenide-based dilute nitride semiconductor material comprises gallium arsenide nitride (GaAsN), indium gallium arsenide nitride (InGaAsN), or aluminum gallium antimonide phosphide nitride (AIGaSbPN).
Naone discloses in Fig. 2,
wherein the light emission layer [108] (Para. [0054]) comprises a gallium arsenide-based dilute nitride semiconductor material [110] (Para. [0054]), an indium phosphide-based dilute nitride semiconductor material, or a gallium phosphide-based dilute nitride semiconductor material; and
wherein the gallium arsenide-based dilute nitride semiconductor material [110] comprises gallium arsenide nitride (GaAsN), indium gallium arsenide nitride (InGaAsN) (Para. [0056]), or aluminum gallium antimonide phosphide nitride (AIGaSbPN).
Examiner notes the term “or” used in lines 3 and 6 of claim 4. For the purpose of examination in the instant application, the interpretation used for claim 4 will be “wherein the light emission layer comprises a gallium arsenide-based dilute nitride semiconductor material; and
Wherein the gallium arsenide-based dilute nitride semiconductor material comprises indium gallium arsenide nitride (InGaAsN)”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the quantum well structure of Naone in place of the active layer of the modified device of Mathai for the purpose of providing substantially defect free, high optical quality material. (Naone Para. [0056])
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Mathai in view of Maros as applied to claim 1 above and further in view of Kwak (US 20040120376 A1).
Regarding claim 8, Mathai in view of Maros discloses the device outlined in the rejection of claim 1 above but fails to disclose,
further comprising insulating structures on corresponding second reflectors, wherein the insulating structures are substantially aligned with corresponding apertures.
Kwak discloses in Fig. 4,
an insulating structure [160] on a second reflector [140] (Para. [0039]), wherein the insulating structures [160] are substantially aligned with corresponding apertures [150] (Para. [0038,0042]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the insulation film as shown in Kwak into the modified device of Mathai for the purpose of providing protection to the reflector layer while allowing a window for light emission. (Kwak Para. [0038])
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Examiner particularly notes US 20210111539 A1 which discloses the use of dilute nitride based lasers comprising InGaAsNSb. See PTO-892 form.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNTER J NELSON whose telephone number is (571)270-5318. The examiner can normally be reached Mon-Fri. 8:30am-5:00 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MinSun Harvey can be reached at (571) 272-1835. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/H.J.N./Examiner, Art Unit 2828 /MINSUN O HARVEY/Supervisory Patent Examiner, Art Unit 2828