DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/24/2025 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7, 11 and 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the limitation “the second comprising” renders the claim indefinite because it is unclear as to what structure “the second” refers to. Appropriate correction should be made to clarify the language.
For examination purposes, the examiner interprets the limitation “the second comprising” to be “the second die comprising”. This interpretation is supported by the Applicant’s drawings and written description.
Furthermore, the limitation “an interconnect positioned between a cavity surface of the PCB” renders the claim indefinite. As the limitation only recites a single surface (“a cavity surface of the PCB”) it is unclear what structures the interconnect is between. Appropriate correction should be made to clarify the language.
For examination purposes, the limitation will be interpreted as the interconnect being positioned between the second die and the cavity surface.
Claims 2-7, 11, and 13 are also rejected under 35 USC 112(B) since they inherit the deficiencies of base claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (US20160113115A1) in view of Drab et al. (US20180337160A1).
Regarding claim 1, Fig.6B of Kwon teaches a module comprising:
a printed circuit board (PCB) 110d (para.0059) including a plurality of metal layers (para.0032, conductive pads); wherein a first metal layer (para.0032, conductive pads) of the plurality of metal layers (para.0032, conductive pads) is disposed on a top insulating layer of the PCB 110d;
a first die 143 (para.0041) electrically coupled to the PCB 110d by a first flip-chip mounting 132 (para.0041);
a second die 120a (para.0028) electrically coupled to the PCB 110d by a second flip-chip mounting PD1 (para.0032); wherein at least a portion of the second die 120a is disposed between the first die 143 and the PCB 110d such that the first die 143 is stacked over the second die 120a; wherein the first die 143 is separated from the second die 120a by a gap; wherein a height of the first flip-chip mounting 132 is taller than a height of the second flip-chip mounting PD1; wherein at least two opposing ends of the first die 143 extend beyond the second die 120a; wherein the first flip-chip mounting 132 mechanically supports the at least two opposing ends of the first die 143;
a component 182 (para.0059) electrically coupled to the first metal layer (para.0032, conductive pads); and
a molding compound 200A (para.0064) formed over the component 182, the second die 120a, and the top insulating layer of the PCB 110d;
Kwon does not teach wherein the PCB defines a cavity recessed from a top surface of the PCB, and the second die is at least partially received in the cavity, the cavity comprising a vertical sidewall, the second comprising a first contact coupled to a ball grid array through a via and a second contact coupled to an interconnect positioned between a cavity surface of the PCB.
Drab teaches, in Fig.3D, wherein the PCB 208 (para.0037) defines a cavity 204 (para.0037) recessed from a top surface of the PCB 208, and the second die 202 (para.0037) is at least partially received in the cavity 204, the cavity 204 comprising a vertical sidewall, the second comprising a first contact 142 (Fig.2H, para.0033) coupled to a ball grid array 226 (para.0037) through a via 130 (Fig.2H, para.0033) and a second contact 134 (Fig.2G, para.0032) coupled to an interconnect 158 (Fig.2G, para.0032) positioned between a cavity surface of the PCB 208.
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to include the cavity and the electrical connections 226 of Drab in the teachings of Kwon in order for the cavity to enable the device die 202 to be encapsulated and for the electrical connections to enable connection of external devices. (Drab, [para.0037]).
Regarding claim 2, Drab further teaches the module of claim 1, wherein a second metal layer 134 (Fig.2G, para.0032) of the plurality of metal layers 134 is disposed on a bottom surface of the cavity 204 (para.0037); wherein the second flip-chip mounting 158 (Fig.2G, para.0032) is between the second die 202 (para.0037) and the second metal layer 134.
Regarding claim 3, Kwon further teaches the module of claim 2, wherein the first flip-chip mounting 132 (para.0041) is between the first die 143 (para.0041) and the first metal layer (para.0032, conductive pads).
Regarding claim 4, Kwon further teaches the module of claim 2, wherein the first flip-chip mounting 132 (para.0041) is between the first die 143 (para.0041) and the second metal layer (para.0032, conductive pads).
Regarding claim 5, Kwon further teaches the module of claim 2, wherein at least a third metal layer of the plurality of metal layers is disposed between the first metal layer (para.0032, conductive pads on first side 112) and the second metal layer (para.0039, conductive pads on second side 114).
Regarding claim 6, Combination of Kwon and Drab further teaches the module of claim 2, wherein the first flip-chip mounting 132 (Kwon, para.0041) comprises a first plurality of interconnects on the top insulating layer (Kwon, para.0030, PCB 110a may include one or more dielectric material layers) of the PCB 110d (para.0059); wherein the second flip-chip mounting PD1 (Kwon, para.0032) comprises a second plurality of interconnects in the cavity 204 (Drab, para.0037); wherein a height of the first plurality of interconnects 132 is greater than a height of the second plurality of interconnects PD1, wherein the first plurality of interconnects 132 includes pillars.
Regarding claim 7, Kwon further teaches the module of claim 1, wherein the first flip-chip mounting 132 (para.0041) is between the first die 143 (para.0041) and the first metal layer (para.0032, conductive pads); wherein the second flip-chip mounting PD1 (para.0032) is between the second die 120a (para.0028) and the first metal layer (para.0032, conductive pads).
Regarding claim 11, Kwon further teaches the module of claim 1, wherein the molding compound 200A (para.0064) is formed over the first die 143 (para.0041).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (US20160113115A1) in view of SPARTIOTIS et al. (US20150279890A1).
Regarding claim 13, Kwon fails to disclose wherein the first flip-chip mounting comprises a plurality of copper pillars; wherein the second flip-chip mounting comprises a plurality of nickel bumps; wherein the plurality of copper pillars are taller than the plurality of nickel bumps.
Spartiotis teaches, in Fig.5, a method of bonding two device 101 and 102, wherein a flip-chip mounting structure (6-8) is used, and wherein the flip-chip mounting structure comprise copper pillar 8 [0024] and nickel bump 7 [0024]; and wherein the copper pillar is taller than the nickel bump (Fig. 5).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to incorporate the flip-chip mounting structure of Spartiotis into the method of Kwon to include the first flip-chip mounting comprises a plurality of copper pillars; wherein the second flip-chip mounting comprises a plurality of nickel bumps; wherein the plurality of copper pillars are taller than the plurality of nickel bumps for the purpose of avoiding the risk of short-circuiting (Spartiotis, [0022]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891