DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Applicant’s remarks, filed 03/25/2026, with respect to the rejection(s) of claim 1 under 35 U.S.C. § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of layer 200 of Drab’s invention being the PCB. The argument that the reference does not teach the depth of 30 micron is not persuasive because Drab discloses, in para.0036, wherein different device dies have distinct thickness such as 100-700 micrometers (this range is at least 30 micrometers) and wherein a cavity depth is greater than the thickest interconnection die in order to accommodate dissimilar dies 108. Applicant’s argument that the reference does not teach wherein the bottom surface of the second die being positioned above a top surface of the PCB and the cavity is not persuasive because as shown by the annotated Fig.3D, it is illustrated how the bottom surface of the second die 202 is above the top surface of the PCB 200. In view of Drab’s teachings, therefore, it is clear that Drab teaches the argued limitations. A detailed rejection of the claims as a whole is provided hereinafter.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (US20160113115A1) in view of Drab et al. (US20180337160A1).
Regarding claim 1, Fig.6B of Kwon teaches a module comprising:
a printed circuit board (PCB) 110d (para.0059) including a plurality of metal layers (para.0032, conductive pads); wherein a first
metal layer (para.0032, conductive pads) of the plurality of metal layers (para.0032, conductive pads) is disposed on a top insulating layer of the PCB 110d;
a first die 143 (para.0041) electrically coupled to the PCB 110d by a first flip-chip mounting 132 (para.0041);
a second die 120a (para.0028) electrically coupled to the PCB 110d by a second flip-chip mounting PD1 (para.0032); wherein at least a portion of the second die 120a is disposed between the first die 143 and the PCB 110d such that the first die 143 is stacked over the second die 120a; wherein the first die 143 is separated from the second die 120a by a gap; wherein a height of the first flip-chip mounting 132 is taller than a height of the second flip-chip mounting PD1; wherein at least two opposing ends of the first die 143 extend beyond the second die 120a; wherein the first flip-chip mounting 132 mechanically supports the at least two opposing ends of the first die 143;
a component 182 (para.0059) electrically coupled to the first metal layer (para.0032, conductive pads); and
a molding compound 200A (para.0064) formed over the component 182, the second die 120a, and the top insulating layer of the PCB 110d;
Kwon does not teach wherein the PCB defines a cavity recessed from a top surface of the PCB, and the second die is at least partially received in the cavity, the cavity comprising a vertical sidewall, the second die comprising a first contact coupled to a ball grid array through a via and a second contact coupled to an interconnect positioned between a cavity surfaces of the PCB, the vertical sidewall being integral to and a part of the PCB.
Fig.3D of Drab teaches a device die 202 is received in a cavity 204 etched into an oxide bonded semiconductor wafer stack (abstract); wherein the PCB 200 (para.0037) defines a cavity 204 (para.0037) recessed from a top surface of the PCB 200, and the second die 202 (para.0037) is at least partially received in the cavity 204, the cavity 204 comprising a vertical sidewall, the second die 202 comprising a first contact 142 (para.0033) coupled to a ball grid array 226 (para.0037) through a via 130 (para.0033) and a second contact 134 (Fig.2G, para.0032) coupled to an interconnect positioned between a cavity surfaces of the PCB 200, the vertical sidewall being integral to and a part of the PCB 200.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to the cavity and the electrical contacts of Drab in the teachings of Kwon in order for the cavity to enable the device die to be encapsulated and for the electrical connections to enable connection of external devices (Drab, [para.0037]).
Regarding claim 2, Drab further teaches the module of claim 1, wherein a second metal layer 134 (Fig.2G, para.0032) of the plurality of metal layers 134 is disposed on a bottom surface of the cavity 204 (para.0037); wherein the second flip-chip mounting 158 (Fig.2G, para.0032) is between the second die 202 (para.0037) and the second metal layer 134.
Regarding claim 3, Kwon further teaches the module of claim 2, wherein the first flip-chip mounting 132 (para.0041) is between the first die 143 (para.0041) and the first metal layer (para.0032, conductive pads).
Regarding claim 4, Kwon further teaches the module of claim 2, wherein the first flip-chip mounting 132 (para.0041) is between the first die 143 (para.0041) and the second metal layer (para.0032, conductive pads).
Regarding claim 5, Kwon further teaches the module of claim 2, wherein at least a third metal layer of the plurality of metal layers is disposed between the first metal layer (para.0032, conductive pads on first side 112) and the second metal layer (para.0032, conductive pads on second side 114).
Regarding claim 6, the combination of Kwon and Drab teaches the module of claim 2, wherein the first flip-chip mounting 132 (Kwon, para.0041) comprises a first plurality of interconnects on the top insulating layer (Kwon, para.0032, PCB 110a may include one or more dielectric material layers) of the PCB 110d (para.0059); wherein the second flip-chip mounting PD1 (Kwon, para.0032) comprises a second plurality of interconnects in the cavity 204 (Drab, para.0037); wherein a height of the first plurality of interconnects 132 is greater than a height of the second plurality of interconnects PD1, wherein the first plurality of interconnects 132 includes pillars.
Regarding claim 7, Kwon further teaches the module of claim 1, wherein the first flip-chip mounting 132 (para.0041) is between the first die 143 (para.0041) and the first metal layer; wherein the second flip-chip mounting 132 (para.0041) is between the second die 120a (para.0028) and the first metal layer (para.0032, conductive pads).
Regarding claim 21, Fig.6B of Kwon teaches a module comprising:
a printed circuit board (PCB) 110d (para.0059) including a plurality of metal layers (para.0032, conductive pads); wherein a first metal layer (para.0032, conductive pads) of the plurality of metal layers (para.0032, conductive pads) is disposed on a top insulating layer of the PCB 110d;
a first die 143 (para.0041) electrically coupled to the PCB 110d by a first flip-chip mounting 132 (para.0041);
a second die 120a (para.0028) electrically coupled to the PCB 110d by a second flip-chip mounting PD1 (para.0032); wherein at least a portion of the second die 120a is disposed between the first die 143 and the PCB 110d such that the first die 143 is stacked over the second die 120a; wherein the first die 143 is separated from the second die 120a by a gap; wherein a height of the first flip-chip mounting 132 is taller than a height of the second flip-chip mounting PD1; wherein at least two opposing ends of the first die 143 extend beyond the second die 120a; wherein the first flip-chip mounting 132 mechanically supports the at least two opposing ends of the first die 143;
a component 182 (para.0059) electrically coupled to the first metal layer (para.0032, conductive pads); and
a molding compound 200A (para.0064) formed over the component 182, the second die 120a, and the top insulating layer of the PCB 110d;
Kwon does not teach wherein the PCB defines a cavity recessed from a top surface of the PCB, and the second die is at least partially received in the cavity, the cavity comprising a vertical sidewall, the second die comprising a first contact coupled to a ball grid array through a via and a second contact coupled to an interconnect positioned between a cavity surface of the PCB, the vertical sidewall being integral to and a part of the PCB, the cavity being at least 30 micrometers and induced by etching during a PCB cavity formation process.
Fig.3D of Drab teaches a device die 202 that is received in a cavity etched into an oxide bonded semiconductor wafer stack (abstract); wherein the PCB 200 (para.0037) defines a cavity 204 (para.0037) recessed from a top surface of the PCB 200, and the second die 202 (para.0037) is at least partially received in the cavity 204, the cavity 204 comprising a vertical sidewall, the second die 202 comprising a first contact 142 (para.0033) coupled to a ball grid array 226 (para.0037) through a via 130 (para.0033) and a second contact 134 (Fig.2G, para.0032) coupled to an interconnect positioned between a cavity surfaces of the PCB 200, the vertical sidewall being integral to and a part of the PCB 200. Drab also discloses, in para.0036, wherein different device dies have distinct thickness such as 100-700 micrometers (which is at least 30 micrometers) and wherein a cavity depth is greater than the thickest interconnection die in order to accommodate dissimilar dies 108.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to the cavity and the electrical contacts of Drab in the teachings of Kwon in order for the cavity to enable the device die to be encapsulated and for the electrical connections to enable connection of external devices (Drab, [para.0037]).
Regarding claim 22, Fig.6B of Kwon teaches a module comprising:
a printed circuit board (PCB) 110d (para.0059) including a plurality of metal layers (para.0032, conductive pads); wherein a first metal layer (para.0032, conductive pads) of the plurality of metal layers (para.0032, conductive pads) is disposed on a top insulating layer of the PCB 110d;
a first die 143 (para.0041) electrically coupled to the PCB 110d by a first flip-chip mounting 132 (para.0041);
a second die 120a (para.0028) electrically coupled to the PCB 110d by a second flip-chip mounting PD1 (para.0032); wherein at least a portion of the second die 120a is disposed between the first die 143 and the PCB 110d such that the first die 143 is stacked over the second die 120a; wherein the first die 143 is separated from the second die 120a by a gap; wherein a height of the first flip-chip mounting 132 is taller than a height of the second flip-chip mounting PD1; wherein at least two opposing ends of the first die 143 extend beyond the second die 120a; wherein the first flip-chip mounting 132 mechanically supports the at least two opposing ends of the first die 143;
a component 182 (para.0059) electrically coupled to the first metal layer (para.0032, conductive pads); and
a molding compound 200A (para.0064) formed over the component 182, the second die 120a, and the top insulating layer of the PCB 110d;
Kwon does not teach wherein the PCB defines a cavity recessed from a top surface of the PCB, and the second die is at least partially received in the cavity, the cavity comprising a vertical sidewall, the second die comprising a first contact coupled to a ball grid array through a via and a second contact coupled to an interconnect positioned between a cavity surface of the PCB, the vertical sidewall being integral to and a part of the PCB, a bottom surface of the second die being positioned above a top surface of the PCB and the cavity.
Fig.3D of Drab teaches a device die 202 that is received in a cavity 204 etched into an oxide bonded semiconductor wafer stack (abstract); wherein the PCB 200 (para.0037) defines a cavity 204 (para.0037) recessed from a top surface of the PCB 200, and the second die 202 (para.0037) is at least partially received in the cavity 204, the cavity 204 comprising a vertical sidewall, the second die 202 comprising a first contact 142 (para.0033) coupled to a ball grid array 226 (para.0037) through a via 130 (para.0033) and a second contact 134 (Fig.2G, para.0032) coupled to an interconnect positioned between a cavity surfaces of the PCB 200, the vertical sidewall being integral to and a part of the PCB 200, a bottom surface (see annotated Fig.3D) of the second die being positioned above a top surface (see annotated Fig.3D) of the PCB 200and the cavity 204.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to the cavity and the electrical contacts of Drab in the teachings of Kwon in order for the cavity to enable the device die to be encapsulated and for the electrical connections to enable connection of external devices (Drab, [para.0037]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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