DETAILED ACTION
This office action is in response to applicant’s RCE filed on 12/30/2025.
Currently claims 1-20 are pending in the application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/30/2025 was filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement was considered by the examiner.
Claim Objections
Claims 1 and 3 are objected to because of the following informalities:
Regarding claim 1, in the limitation of the claim, “…one first electrode of the plurality of first electrodes and one second electrode of the plurality of second electrodes are connected to the first channel layer and another first electrode of the plurality of first electrodes and another second electrode of the plurality of second electrodes are connected to the second channel layer, …”, the underlined word should be added.
Regarding claim 3, in the limitation of the claim, “…a second memory transistor is formed with the second channel layer and the corresponding first and second electrodes electrically connected to the first channel layer, …”, the underlined word ‘first’ should be replaced by ‘second’.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3 and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over WO 2022/178083 A1 (Samachisa) and further in view of US 2021/0399052 A1 (Wu).
Regarding claim 1, Samachisa discloses, a semiconductor device, comprising: a substrate (1302);
a stack (as annotated on Fig. 13a) including a plurality of electrodes (204a/204b and 204d/204e) and a channel separation pattern (203), each electrode of the plurality of electrodes being stacked on the substrate and spaced apart from each other, and the channel separation pattern (203) being between adjacent electrodes of the plurality of electrodes (Fig. 13a; page 9); and
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a vertical structure (at the middle, as annotated on Fig. 13a) penetrating the stack,
wherein: the vertical structure includes a conductive pillar (as annotated on Fig. 13a), a channel structure (as annotated on Fig. 13a), and an interposing layer (as annotated on Fig. 13a) between the conductive pillar and the channel structure, wherein the channel structure, the interposing layer surrounds the conductive pillar from a top down view (Fig. 13a; page 9),
the channel structure (as annotated on Fig. 13a) includes a first channel layer (250, below 203) and a second channel layer (250, above 203), which are discreet from each other and vertically spaced apart from each other by the channel separation pattern (203) (Fig. 13a; page 9),
the plurality of electrodes (204a/204b and 204d/204e) include a plurality of first electrodes (204a/204b) and a plurality of second electrodes (204d/204e), in which one first electrode (204a/204b) of the plurality of first electrodes and one second electrode (204d/204e) of the plurality of second electrodes are connected to the first channel layer (250, below 203) and another first electrode (204a/204b) of the plurality of first electrodes and another second electrode (204d/204e) of the plurality of second electrodes are connected to the second channel layer (250, above 203), and
the channel separation pattern (203) is between the first channel layer (250, below 203) and the second channel layer (250, above 203),
But Samachisa fails to teach explicitly, the conductive pillar includes a plurality of conductive pillars spaced apart from each other in both a first horizontal direction and a second horizontal direction, with the channel structure interposed between adjacent conductive pillars in both the first horizontal direction and the second horizontal direction,
However, in analogous art, Wu discloses, the conductive pillar (114; conductive layer; Fig. 8A; [0037]) includes a plurality of conductive pillars (Figs. 8A and 8B) spaced apart from each other in both a first horizontal direction (D1-direction; Fig. 8B) and a second horizontal direction (D2-direction; Fig. 8B), with the channel structure (110; channel layer; Fig. 8A; [0037]) interposed between adjacent conductive pillars in both the first horizontal direction (D1-direction; Fig. 8B) and the second horizontal direction (D2-direction; Fig. 8B),
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Samachisa and Wu before him/her, to modify the teachings of a semiconductor memory device as taught by Samachisa and to include the teachings of array of vertical memory structures as taught by Wu since having memory structures in a two-dimensional array would provide a very high density memory device. Absent this important teaching in Samachisa, a person with ordinary skill in the art would be motivated to reach out to Wu while forming a semiconductor memory device of Samachisa.
Regarding claim 2, Samachisa discloses, the semiconductor device as claimed in claim 1,
wherein the interposing layer (as annotated on Fig. 13a) includes:
a ferroelectric layer (part of 271; ferroelectric material; Fig. 13a and 13b; page 9) on an outer side surface of the conductive pillar (252/272; local word line); and
a gate insulating layer (part of 271; interface dielectric layer; Fig. 13a and 13b; page 9) between the ferroelectric layer and the channel structure (250/270).
Note: Although Samachisa failed to teach whether gate insulating layer between the ferroelectric layer and the channel structure, since in MPEP 2143 (I) (E), it is stated that it is "Obvious to try" – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success. The ferroelectric layer and the interface dielectric layer can be formed in two ways only, one on the left and the other on the right. Furthermore, the applicant has not presented persuasive evidence in Spec. para. [0043] that the claimed arrangements are for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed arrangements). Also, the applicant has not shown that the claimed arrangements produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art.
Regarding claim 3, Samachisa discloses, the semiconductor device as claimed in claim 1,
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wherein: a first memory transistor is formed with the first channel layer (250, below 203) and the corresponding first and second electrodes electrically connected to the first channel layer, a first current path extending between the corresponding first and second electrodes and vertically through the first channel layer (Fig. 13a; page 9), and
a second memory transistor is formed with the second channel layer (250, above 203) and the corresponding first and second electrodes electrically connected to the first channel layer, a second current path extending between the corresponding first and second electrodes and vertically through the second channel layer (Fig. 13a; page 9).
Regarding claim 5, the combination of Samachisa and Wu discloses, the semiconductor device as claimed in claim 1, wherein the first channel layer and the second channel layer are each formed of an amorphous oxide semiconductor material; or a two-dimensional material (Wu teaches in para. [0035] that the channel layer 110 (Fig. 8A) includes a metal oxide, an oxide semiconductor, or a combination thereof. The material of the channel layer 110 may be or include amorphous indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium oxide, other applicable materials, or combinations thereof).
Regarding claim 6, Samachisa teaches, the semiconductor device as claimed in claim 1, wherein the first channel layer (top) is above the second channel layer (below the top),
But the combination of Samachisa and Wu fails to teach explicitly, wherein a distance between the first channel layer and the second channel layer is larger than a distance between the lowermost one of the first and second electrodes connected to the first channel layer and the uppermost one of the first and second electrodes connected to the second channel layer.
However, having the channel length slightly shorter in size in both sides would satisfy the limitation. It would not change the device characteristics significantly. In MPEP 2144.04 (IV) (A), it is stated that the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. Furthermore, the applicant has not presented persuasive evidence in Spec. para. [0036] that the claimed arrangements are for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed arrangements). Also, the applicant has not shown that the claimed arrangements produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Samachisa, Wu and MPEP 2144.04 (IV) (A) before him/her, to make the distance between the first channel layer and the second channel layer larger than a distance between the lowermost one of the first and second electrodes connected to the first channel layer and the uppermost one of the first and second electrodes connected to the second channel layer.
Regarding claim 7, the combination of Samachisa and Wu fails to teach explicitly, the semiconductor device as claimed in claim 1, wherein a vertical cross section of the channel separation pattern has a "T"-shape with an upper portion of the T extending vertically and being interposed between the first and second channel layers.
However, having the channel length slightly shorter in size in both sides would make vertical cross section of the channel separation pattern has a "T"-shape with an upper portion of the T extending vertically and being interposed between the first and second channel layers. It would not change the device characteristics significantly. In MPEP 2144.04 (IV) (A), it is stated that the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. Furthermore, the applicant has not presented persuasive evidence in Spec. para. [0036] that the claimed arrangements are for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed arrangements). Also, the applicant has not shown that the claimed arrangements produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Samachisa, Wu and MPEP 2144.04 (IV) (A) before him/her, to make the vertical cross section of the channel separation pattern has a "T"-shape with an upper portion of the T extending vertically and being interposed between the first and second channel layers.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Samachisa and Wu as applied to claim 1 and further in view of US 9,875,784 B1 (Li).
Regarding claim 8, the combination of Samachisa and Wu fails to teach explicitly, the semiconductor device as claimed in claim 1, further comprising a lower insulating layer between the stack and the substrate, wherein a bottom surface of the channel structure is at a level between top and bottom surfaces of the lower insulating layer.
However, in analogous art, Li discloses, the semiconductor device as claimed in claim 1, further comprising a lower insulating layer (376 and 328; insulating layer and bottom dielectric layer; Fig. 3C; col. 9, lines 3-23; col. 10, lines 48-57) between the stack (as annotated on Fig. 3C) and the substrate (330; substrate; Fig. 3C; col. 11, lines 12-15);
a bottom surface (as annotated on Fig. 3C) of the channel structure (362; through-layer silicon bar; Fig. 3C; col. 10, lines 5-20) is at a level between a top surface and a bottom surface (as annotated on Fig. 3C) of the lower insulating layer (376 and 328).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Samachisa, Wu and Li before him/her, to modify the teachings of a semiconductor memory device as taught by Samachisa and to include the teachings of a lower insulating layer on the substrate as taught by Li since the lower insulating layer helps isolate any substrate noise from the memory device and maintains its reliability as a memory device. Absent this important teaching in Samachisa, a person with ordinary skill in the art would be motivated to reach out to Li while forming a semiconductor memory device of Samachisa.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Samachisa and Wu as applied to claim 1 and further in view of US 2021/0242239 A1 (Lin).
Regarding claim 10, the combination of Samachisa and Wu fails to teach explicitly, the semiconductor device as claimed in claim 1, further comprising a peripheral circuit layer between the stack and the substrate or on the stack.
However, in analogous art, Lin discloses, the semiconductor device as claimed in claim 1, further comprising a peripheral circuit layer (214; peripheral circuit; Fig. 9; [0052]) between the stack (200b; memory; Fig. 9; [0052]) and the substrate (substrate) (Fig. 9; [0052]) or on the stack.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Samachisa, Wu and Lin before him/her, to modify the teachings of a semiconductor memory device as taught by Samachisa and to include the teachings of a peripheral circuit between memory device and substrate as taught by Lin since a control circuit in the periphery is required to control the operation of the memory device. Absent this important teaching in Samachisa, a person with ordinary skill in the art would be motivated to reach out to Lin while forming a semiconductor memory device of Samachisa.
Claims 11-12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over WO 2022/178083 A1 (Samachisa) and further in view of US 9,875,784 B1 (Li) and US 2021/0399052 A1 (Wu).
Regarding claim 11, Samachisa discloses, a semiconductor device, comprising:
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a substrate (1302; Fig. 13a; page 8);
a stack (as annotated on Fig. 13a) including electrodes (204a/204b and 204d/204e; conductor/polysilicon; Fig. 13a; page 9) and spaced apart from each other; and
a vertical structure (as annotated on Fig. 13a) penetrating the stack, wherein:
the vertical structure (as annotated on Fig. 13a) includes a conductive pillar (252), a channel structure (as annotated on Fig. 13a), and an interposing layer (as annotated on Fig. 13a) between the conductive pillar (252) and the channel structure (as annotated on Fig. 13a),
the channel structure is an outermost part of the vertical structure and is connected to the electrodes, and
But Samachisa fails to teach explicitly, a lower insulating layer on the substrate; a bottom surface of the channel structure is at a level between a top surface and a bottom surface of the lower insulating layer.
However, in analogous art, Li discloses, a lower insulating layer (376 and 328; insulating layer and bottom dielectric layer; Fig. 3C; col. 9, lines 3-23; col. 10, lines 48-57) on the substrate (330; substrate; Fig. 3C; col. 11, lines 12-15);
a bottom surface (as annotated on Fig. 3C) of the channel structure (362; through-layer silicon bar; Fig. 3C; col. 10, lines 5-20) is at a level between a top surface and a bottom surface (as annotated on Fig. 3C) of the lower insulating layer (376 and 328).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Samachisa and Li before him/her, to modify the teachings of a semiconductor memory device as taught by Samachisa and to include the teachings of a lower insulating layer on the substrate as taught by Li since the lower insulating layer helps isolate any substrate noise from the memory device and maintains its reliability as a memory device. Absent this important teaching in Samachisa, a person with ordinary skill in the art would be motivated to reach out to Li while forming a semiconductor memory device of Samachisa.
But the combination of Samachisa and Li fails to teach explicitly, the conductive pillar includes a plurality of conductive pillars spaced apart from each other in both a first horizontal direction and a second horizontal direction, with the channel structure interposed between adjacent conductive pillars in both the first horizontal direction and the second horizontal direction,
However, in analogous art, Wu discloses, the conductive pillar (114; conductive layer; Fig. 8A; [0037]) includes a plurality of conductive pillars (Figs. 8A and 8B) spaced apart from each other in both a first horizontal direction (D1-direction; Fig. 8B) and a second horizontal direction (D2-direction; Fig. 8B), with the channel structure (110; channel layer; Fig. 8A; [0037]) interposed between adjacent conductive pillars in both the first horizontal direction (D1-direction; Fig. 8B) and the second horizontal direction (D2-direction; Fig. 8B),
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Samachisa, Li and Wu before him/her, to modify the teachings of a semiconductor memory device as taught by Samachisa and to include the teachings of array of vertical memory structures as taught by Wu since having memory structures in a two-dimensional array would provide a very high density memory device. Absent this important teaching in Samachisa, a person with ordinary skill in the art would be motivated to reach out to Wu while forming a semiconductor memory device of Samachisa.
Regarding claim 12, the combination of Samachisa, Li and Wu discloses, the semiconductor device as claimed in claim 11, wherein the bottom surface of the channel structure (362; silicon bar) is at a level lower than a bottom surface of the conductive pillar (382; source electrode) (Fig. 3C; col. 11, lines 36-56; Li Reference).
Regarding claim 14, the combination of Samachisa, Li and Wu discloses, the semiconductor device as claimed in claim 11, wherein the conductive pillar is a circular pillar (Lee Fig. 8B) and has a diameter (as annotated on Fig. 13a; Samachisa) larger than a thickness of each of the electrodes (as annotated on Fig. 13a). In MPEP 2125, it is stated that Drawings and pictures can anticipate claims if they clearly show the structure which is claimed. In re Mraz, 455 F.2d 1069, 173 USPQ 25 (CCPA 1972).
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Claims 16-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over WO 2022/178083 A1 (Samachisa) and further in view of US 2021/0399052 A1 (Wu).
Regarding claim 1, Samachisa discloses, a semiconductor device, comprising:
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a substrate (1302; Fig. 13a; page 8);
stacks (as annotated on Fig. 13a; since it is a memory structure, there will be a lot of stacks) on the substrate (1302),
the stacks being spaced apart from each other in a first direction (x-direction, horizontal); and
a vertical structure (as annotated on Fig. 13a) penetrating each of the stacks, wherein:
each of the stacks includes a first electrode (204a/204b) and a second electrode (204d/204e), which is stacked on the first electrode (204a/204b),
the first electrode (204a/204b) and the second electrode (204d/204e) each extend parallel to each other in a second direction (y-direction, inside the 2D-plane of the viewable area), and
the vertical structure includes:
a conductive pillar (252) extending in a third direction (z-direction, vertical) perpendicular to the first direction (x-direction) and the second direction (y-direction);
a channel layer (250, part of channel structure, as annotated on Fig. 13a) connecting the first electrode (204a/204b) and the second electrode (204d/204e) to each other; and
a ferroelectric layer (part of 271; ferroelectric material; Fig. 13a and 13b; page 9) between the conductive pillar (252) and the channel layer (250), with respect to a top down view, the ferroelectric layer (part of 271) surrounds the conductive pillar (252), and the channel layer (250) surrounds the ferroelectric layer (part of 271),
But Samachisa fails to teach explicitly, the conductive pillar includes a plurality of conductive pillars spaced apart from each other in both a first horizontal direction and a second horizontal direction, with the channel structure interposed between adjacent conductive pillars in both the first horizontal direction and the second horizontal direction,
However, in analogous art, Wu discloses, the conductive pillar (114; conductive layer; Fig. 8A; [0037]) includes a plurality of conductive pillars (Figs. 8A and 8B) spaced apart from each other in both a first horizontal direction (D1-direction; Fig. 8B) and a second horizontal direction (D2-direction; Fig. 8B), with the channel structure (110; channel layer; Fig. 8A; [0037]) interposed between adjacent conductive pillars in both the first horizontal direction (D1-direction; Fig. 8B) and the second horizontal direction (D2-direction; Fig. 8B),
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Samachisa and Wu before him/her, to modify the teachings of a semiconductor memory device as taught by Samachisa and to include the teachings of array of vertical memory structures as taught by Wu since having memory structures in a two-dimensional array would provide a very high density memory device. Absent this important teaching in Samachisa, a person with ordinary skill in the art would be motivated to reach out to Wu while forming a semiconductor memory device of Samachisa.
Regarding claim 17, Samachisa discloses, the semiconductor device as claimed in claim 16, wherein: one of the first electrode (204a/204b) and the second electrode (204d/204e) is a bit line (common drain region), another one of the first electrode and the second electrode is a source line (common source region), and the conductive pillar (252) is connected to a word line (local word line) (Fig. 13a; page 9).
Regarding claim 18, Samachisa discloses, the semiconductor device as claimed in claim 16, wherein the vertical structure (as annotated on Fig. 13a) further includes a gate insulating layer (part of 271; interface dielectric layer; Fig. 13a and 13b; page 9) between the ferroelectric layer (part of 271; ferroelectric material; Fig. 13a and 13b; page 9) and the channel layer (250/270).
Note: Although Samachisa failed to teach whether gate insulating layer between the ferroelectric layer and the channel structure, but in MPEP 2143 (I) (E), it is stated that it is "Obvious to try" – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success. The ferroelectric layer and the interface dielectric layer can be formed in two ways only, one on the left and the other on the right. Furthermore, the applicant has not presented persuasive evidence in Spec. para. [0043] that the claimed arrangements are for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed arrangements). Also, the applicant has not shown that the claimed arrangements produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art.
Regarding claim 20, the combination of Samachisa and Wu discloses, the semiconductor device as claimed in claim 16, wherein the channel layer is formed of an amorphous oxide semiconductor material; or a two-dimensional material (Wu teaches in para. [0035] that the channel layer 110 (Fig. 8A) includes a metal oxide, an oxide semiconductor, or a combination thereof. The material of the channel layer 110 may be or include amorphous indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium oxide, other applicable materials, or combinations thereof).
Allowable Subject Matter
Claims 4, 9, 13, 15 and 19 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent forms including all of the limitations of the base claims and any intervening claims.
Regarding claim 4, the closest prior art, WO 2022/178083 A1 (Samachisa), in combination with US 2021/0399052 A1 (Wu), US 2021/0242239 A1 (Lin) and US 9,875,784 B1 (Li), fails to disclose, “the semiconductor device as claimed in claim 1, wherein: each of the electrodes includes: a semiconductor pattern connected to the channel structure, the semiconductor pattern having opposite first and second vertical side surfaces; and first and second conductive patterns which are respectively on the first and second vertical side surfaces of the semiconductor pattern”, in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 9, the closest prior art, WO 2022/178083 A1 (Samachisa), in combination with US 2021/0399052 A1 (Wu), US 2021/0242239 A1 (Lin) and US 9,875,784 B1 (Li), fails to disclose, “the semiconductor device as claimed in claim 1, wherein: the electrodes further include third electrodes connected to one of the first channel layer and the second channel layer, the first electrodes and the third electrodes are bit lines, respectively, and the second electrodes are between the first electrodes and the third electrodes and are common source lines”, in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 13, the closest prior art, WO 2022/178083 A1 (Samachisa), in combination with US 2021/0399052 A1 (Wu), US 2021/0242239 A1 (Lin) and US 9,875,784 B1 (Li), fails to disclose, “the semiconductor device as claimed in claim 11, wherein: the lower insulating layer includes a first lower insulating layer, a second lower insulating layer, and a third lower insulating layer, which are sequentially stacked, the second lower insulating layer has an etch selectivity with respect to the first lower insulating layer and the third lower insulating layer, and the bottom surface of the channel structure is at a level between a top surface and a bottom surface of the second lower insulating layer”, in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 15, the closest prior art, WO 2022/178083 A1 (Samachisa), in combination with US 2021/0399052 A1 (Wu), US 2021/0242239 A1 (Lin) and US 9,875,784 B1 (Li), fails to disclose, “the semiconductor device as claimed in claim 1, wherein: each of the electrodes includes: a semiconductor pattern connected to the channel structure, the semiconductor pattern having opposite first and second vertical side surfaces; and first and second conductive patterns which are respectively on the first and second vertical side surfaces of the semiconductor pattern”, in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 19, the closest prior art, WO 2022/178083 A1 (Samachisa), in combination with US 2021/0399052 A1 (Wu), US 2021/0242239 A1 (Lin) and US 9,875,784 B1 (Li), fails to disclose, “the semiconductor device as claimed in claim 16, wherein: each of the stacks further includes a third electrode, which is stacked on the second electrode and is connected to the channel layer, the first electrode and the third electrode are bit lines, respectively, and the second electrode is between the first electrode and the third electrode and is a common source line”, in combination with the additionally claimed features, as are claimed by the Applicant.
Examiner’s Note
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2022/0384459 A1 (Lu) - A ferroelectric memory device is disclosed having a multi-layer stack disposed over a substrate and including a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A plurality of ferroelectric portions are discretely disposed between the channel layer and the plurality of conductive layers. The plurality of ferroelectric portions are vertically separated from one another by one or more non-zero distances.
US 2022/0231026 A1 (Wu) - A memory array is disclosed including hybrid memory cells, wherein each hybrid memory cell includes a transistor-type memory including a memory film extending on a gate electrode; a channel layer extending on the memory film; a first source/drain electrode extending on the channel layer; and a second source/drain electrode extending along the channel layer; and a resistive-type memory including a resistive memory layer, wherein the resistive memory layer extends between the second source/drain electrode and the channel layer.
US 2022/0028882 A1 (Lee) - A memory device and method of forming the same are provided. The memory device includes a word line, a bit line, a source line, a channel pillar, and a charge storage structure. The bit line and the source line are disposed on opposite sides of the word line in a vertical direction. The channel pillar penetrates through and is connected to the word line, the bit line and the source line. The charge storage structure surrounds a top surface and a bottom surface of the word line and is laterally sandwiched between the channel pillar and the word line. The channel pillar completely penetrates through and is laterally surrounded by the bit line.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
01/22/2026