DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/20/2025 has been entered.
Response to Amendment
The Amendment filed on 10/20/2025 has been entered. Claims 1-3, 5-7, 9-12 and newly added claims 13-15, remain pending in the application. Claims 4 and 8 have been cancelled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 3, 5, 6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yuji Imoto et al. (Japanese Patent Application Publication Number, JP 2015-162649A), hereinafter referenced as Imoto, in view of Masanori Onodera et al., (United States Patent Number US 6,373,140 B1) hereinafter referenced as Onodera, and in view of Kyouhei Watanabe, (United States Patent Application Publication Number US 2011/0300662 A1), hereinafter referenced as Watanabe, and in view of Hidekazu Kawanishi et al., (United States Patent Application Publication Number US 2020/0313400 A1), hereinafter referenced as Kawanishi.
Regarding claim 1, Imoto teaches a semiconductor apparatus, comprising: a semiconductor element having a top electrode (Fig.12, semiconductor element #4, paragraph [0012], row 6 is connected to the lead terminal, element #6, on the top side of the semiconductor); a control terminal (Fig.10, elements #8 and #6, paragraph [0012], rows 6-9) including a pad (Fig.12, element #6, paragraph [0012], rows 6-7) electrically connected to the top electrode of the semiconductor element through a wiring member (Fig.12, element #13, paragraph [0002], rows 4-5, and paragraph [0024], rows 5-6); and a case member (Fig.12, element #5, paragraph [0012], rows 5-6) in which at least a portion of the control terminal is embedded (Fig.10, paragraph [0012], rows 7-9) and which defines a space for housing the semiconductor element (Fig.2, there is a space between the left and right walls made of element #5), and an encapsulating resin filling the space (Fig.1, element #9, paragraph [0012], row 9), wherein the case member includes a wiring member positioning part raised on the case member (Fig.10, protrusions, elements #14 are raised from the surface of the case member).
Imoto does not teach wherein the positioning part is used as a reference point for a positioning of the wiring member before a connection is made of the wiring member to the pad. Onodera teaches a wiring member positioning part raised from the surface (Fig.20, element #46 (30B) column 11, rows 60-63) that is used as a reference point for a positioning of the wiring member before a connection is made of the wiring member to the pad (column 5, rows 25-29, detection mark position is stored in a memory unit and, based on that, the wire bonding is performed). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Onodera and disclose a positioning part raised from the surface and used as a reference point before a connection is made of the wiring member to the pad. As Onodera disclosed, the raised positioning part may comprise of highly reflective materials that can be detected easily (column 10, rows 11-12 and 17-18) and thus provides a highly accurate reference point, which increases reliability of the wire bonding. Furthermore, the positioning part may be built simultaneously with other layers or parts of the device (column 10, rows 45-46) thus saving processing time and steps.
The combination of Imoto and Onodera does not teach the semiconductor apparatus further comprises a coating film interposed between the positioning part and the encapsulating resin. Watanabe teaches a coating film (Fig.5, element #106, paragraph [0022], rows 7-8) interposed between the positioning part (Fig.5, element #107) and the encapsulating resin (Fig.5, element #504, paragraph [0044], rows 1-2). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Watanabe and disclose a coating film interposed between the positioning part and the encapsulating resin. The film can act as a protective layer against potential corrosion, and comprises materials with different reflectivity as compared to the case material, which will make the positioning part easier to locate on the case wall.
Imoto further teaches wherein the pad is provided in plurality as a pad group (Fig.10, element #6) and the plurality of pads in the pad group is arranged in a predetermined direction (Fig.6, direction parallel to the top surface of element #5b and the inside surface of element #5a), the positioning part is provided in plurality (Fig.10, element #14).
The combination of Imoto, Onodera and Watanabe does not teach two positioning parts among the plurality of positioning parts sandwich therebetween the pad group in the predetermined direction, one of the two positioning parts is disposed beside an outmost one of the plurality of pads at one of opposite ends of the pad group in the predetermined direction, and the other of the two positioning parts is disposed beside another outmost one of the plurality of pads at the other of the opposite ends of the pad group. Kawanishi teaches wherein the pad is provided in plurality as a pad group (Fig.2, pads, element #42 form pad groups consisting of 4 pads each),and the plurality of pads in the pad group is arranged in a predetermined direction (Fig.2, are arranged along x direction), the positioning part is provided in plurality (Fig.2, cross marks), two positioning parts among the plurality of positioning parts sandwich therebetween the pad group in the predetermined direction (Fig.2, cross marks adjacent to the second pad group from the top), one of the two positioning parts is disposed beside an outmost one of the plurality of pads at one of opposite ends of the pad group in the predetermined direction, and the other of the two positioning parts is disposed beside another outmost one of the plurality of pads at the other of the opposite ends of the pad group (Fig.2, the cross marks are beside outmost pads along x direction, on opposite ends of the pad group). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Kawanishi and disclose two positioning parts among the plurality of positioning parts sandwich therebetween the pad group in the predetermined direction, one of the two positioning parts is disposed beside an outmost one of the plurality of pads at one of opposite ends of the pad group in the predetermined direction, and the other of the two positioning parts is disposed beside another outmost one of the plurality of pads at the other of the opposite ends of the pad group. The presence of the two positioning parts which sandwich the pad group in the predetermined direction, and are located at opposite ends of the pad group, provide two sets of reference data for positioning the wiring members, which results in a more accurate determination of the pads location as compared to using a single positioning part.
Regarding claim 2, the combination of Imoto, Onodera, Watanabe and Kawanishi teaches the semiconductor apparatus of claim 1 as set forth in the obviousness rejection. Imoto further teaches wherein the case member (Fig.5, element #5) has a rectangular frame shape (Fig.2, shows a top view of the case member, element #5) with the space in a center of the case member in a plan view of the semiconductor apparatus (Fig.2, space delimited by part of element #1 visible in the figure, is in a center of the case, element #5), the case member including a wall (Fig.1, element #5 forms a wall), the control terminal is disposed in the wall (Fig.10, element #8 and #6, paragraph [0012], rows 7-9), the wall includes a step part that is a step down from a top face of the wall (Fig.10, top surface of the wall is the top surface of element #5b, which has a step part where element #6 is inserted), the control terminal has a top face (Fig.10, top surface of element #6) and is embedded in the step part (Fig.6, element #6 is embedded in the step part) such that a portion of the top face of the control terminal is flush with the step part (Fig.10, top face of element #6 and the upper side of the step part are flush), and the positioning part is disposed at the top face of the wall, beside the pad (Fig.10, protrusions element #14 are located on top face and beside the pad).
Regarding claim 3, the combination of Imoto, Onodera, Watanabe and Kawanishi teaches the semiconductor apparatus of claims 1 and 2 as set forth in the obviousness rejection. Imoto further teaches wherein the control terminal (Fig.10, elements #8 and #6, paragraph [0012], rows 6-9) includes an outer terminal part for external connection (Fig.10, element #8) and an inner terminal part (Fig.10, element #6) connected to the top electrode of the semiconductor element through the wiring member (Fig.12, element #6, connected to top side of semiconductor element #4 through wiring member, element #13), the top face of the control terminal that is flush with the step part (Fig.10, top face of element #6 and the upper side of the step part are flush), is a top face of the inner terminal part (Fig.10, the top face of element #6 is both) the wall has a pillar projecting upward from the top face of the wall (Fig.10, part of element #5a is a pillar projecting upward from top face of element #5b), and the outer terminal part includes an intermediate part that is embedded in the pillar (Fig.10, part represented by the doted lines between elements #6 and #8) and a leading end that projects out from a top face of the pillar (Fig.8, element #8 projects up from a top face of the pillar).
Regarding claim 5, the combination of Imoto, Onodera, Watanabe and Kawanishi teaches the semiconductor apparatus of claims 1 and 2 as set forth in the obviousness rejection. Imoto further teaches the semiconductor apparatus, further comprising: an encapsulating resin filling the space (Fig.1, element #9, paragraph [0012], row 9), wherein the wall includes an anchor part on an inner face of the wall (Fig.11, element #10 acts as an anchor for the resin, element #9, paragraph [0014], rows 3-4), the anchor part having an uneven shape (elements #10 can be made uneven as shown in Fig.9).
Regarding claim 6, the combination of Imoto, Onodera, Watanabe and Kawanishi teaches the semiconductor apparatus of claim 1 as set forth in the obviousness rejection. Imoto further teaches wherein the positioning part has a cylindrical shape (Fig.10, element #14 has a cylindrical shape).
Regarding claim 13, the combination of Imoto, Onodera, Watanabe and Kawanishi teaches the semiconductor apparatus of claim 1 as set forth in the obviousness rejection. Kawanishi further teaches the semiconductor apparatus according to claim 1, wherein the two positioning parts are respectively disposed on left and right sides of three or more pads of the plurality of pads arranged in a row (Fig.2, the positioning parts are disposed on the left and right side of 4 pads, along the x direction). The presence of the two positioning parts disposed on left and right sides of three or more pads of the plurality of pads arranged in a row, provide two sets of reference data for positioning the wiring members, which results in a more accurate determination of the pads location as compared to using a single positioning part.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Imoto, in view of Onodera, Watanabe, Kawanishi and in view of Norio Yamanishi, (United States Patent Number, US 9,406,620 B2) hereinafter referenced as Yamanishi.
Regarding claim 7, the combination of Imoto, Onodera, Watanabe and Kawanishi teaches the semiconductor apparatus of claim 1 as set forth in the obviousness rejection. The combination of Imoto, Onodera, Watanabe and Kawanishi does not teach wherein the positioning part has a recess at an upper end thereof. Yamanishi teaches wherein the positioning part has a recess at an upper end thereof (Fig.2, positioning part, formed by elements #22A and #23 has a recess at the upper end, column 3 rows 20-25). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Yamanishi and disclose a recess at an upper end of the positioning part. As disclosed by Yamanishi, this results in an image contrast between the recessed region and the upper part of the positioning part and makes the positioning part easy to distinguish from the surroundings, thus allowing it to be located with high accuracy (column 8, rows 15-21).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Imoto, in view of Onodera, Watanabe, in view of Toshio Hanada, (United States Patent Number US 9,960,103 B2) hereinafter referenced as Hanada, and in view of Keita Fukutani et al. (United States Patent Number US 8,497,572 B2) hereinafter referenced as Fukutani.
Regarding claim 9, the combination of Imoto, Onodera, Watanabe and Kawanishi teaches the semiconductor apparatus of claim 1 as set forth in the obviousness rejection. Imoto further teaches the semiconductor apparatus according to claim 1, further comprising: an insulating substrate including a circuit layer (Fig.1, element #2, paragraph [0012], rows 3-4). The combination of Imoto, Onodera, Watanabe and Kawanishi doesn’t teach the circuit layer is electrically connected to the semiconductor element. Hanada teaches the circuit layer (Fig.17, element #10a, column 9, rows 31-33) is electrically connected to the semiconductor element (Fig.17, element #10a is connected through electrically conductive material, solder, element #3b, column 13, row 6, to semiconductor, element #Q, column 13, row 17). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Hanada and disclose a circuit layer electrically connected to the semiconductor element. The circuit layer provides integration of the semiconductor device into a complex electronic system where the device can be connected to other components of the circuit.
Imoto further teaches a metal wiring plate (Fig.1, elements #8 and #6 on the left side of the figure), one end of which forms a main terminal connectible to an external conductor (Fig.1, element #8 on the left side of the image) and another end of which is bonded to the insulating plate (Fig.1, right end of the left element #6). The combination of Imoto, Onodera, Watanabe and Kawanishi does not teach, the metal wiring plate bonded through a bonding material, to the circuit layer of the insulating substrate. Hanada discloses the metal wiring plate (Fig.19, element #SS) bonded through a bonding material (Fig.19, element #3c column 12, row 35), to the circuit layer (Fig.19, electrode pattern, element SSP, column 12, row 34-36, part of layer copper plate layer, element #10a, column 12, row 48) of the insulating substrate (element #10, column 11, row 42). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Hanada and disclose the metal wiring plate bonded, through a bonding material, to the circuit layer of the insulating substrate. The electrical connection allows the wiring plate to power the circuit layer or output signals from the circuit. Furthermore, the use of a bonding material for the connection provides a reliable electrical connection and minimizes stress as compared to other bonding techniques, such as welding or soldering, that require high heat or strong mechanical forces that can damage the circuit.
Imoto further teaches wherein the case member has a rectangular frame shape (Fig.2, element #5 has a rectangular shape) with the space in a center of the case member in a plan view of the semiconductor apparatus (Fig.2, space delimited by the part of element #1 visible in the figure, is in a center of the case, element #5), and has first and second walls facing each other in a predetermined direction (Fig.1, first wall is the right side of the figure and second wall is on the left side of the figure made), and the control terminal (Fig.2 element #8) are disposed on the second wall (Fig.2, left side wall).
The combination of Imoto, Onodera, Watanabe, Kawanishi and Hanada doesn’t teach the metal wiring plate includes an intermediate terminal, a positive electrode terminal, and a negative electrode terminal, the positive electrode terminal and the negative electrode terminal are disposed on the first wall, the intermediate terminal is disposed on the second wall. Fukutani teaches the metal wiring plate (Fig.26, element #30, column 15, row 11) includes an intermediate terminal (Fig.26, element #13, column 31, row 59-60) a positive electrode terminal (Fig.26, element #12, column 32, row 61), and a negative electrode terminal (Fig.26, element #14, column 32, row 58), the positive electrode terminal and the negative electrode terminal are disposed on the first wall (Fig.26, top dashed line of the resin mold part, element #J20), the intermediate terminal is disposed on the second wall (Fig.26, bottom dashed line of the resin mold, element #J20, on same side with the control terminal element #15 and #15a,column 31, rows 30-35). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Fukutani and disclose the metal wiring plate includes an intermediate terminal, a positive electrode terminal, and a negative electrode terminal, the positive electrode terminal and the negative electrode terminal are disposed on the first wall, the intermediate terminal and control terminal is disposed on the second wall. As disclosed by Fukutani, disposing the negative and positive terminal adjacent to each other reduces the inductance (column 33, row 4-9). Also, disposing the intermediate terminal and the control terminal on a wall opposite to the one where the positive and negative terminals are located allows an easier integration of multiple devices in parallel, while maintaining a small footprint of the device and optimum size of the terminals.
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Imoto, in view of Onodera, Watanabe, Kawanishi and in view of disclosed prior art, Tomohiro Hieda et al. (Japanese Patent Application Publication Number JP 2002-134552 A) hereinafter referenced as Hieda.
Regarding claim 10, the combination of Imoto, Onodera, Watanabe and Kawanishi teaches the semiconductor apparatus of claim 1 as set forth in the obviousness rejection. Imoto does not teach before the connection is made between the wiring member and the pad of the control terminal, producing a planar image of the area around the pad. Onodera teaches before the connection is made between the wiring member (Fig.4B, element #31A, column 5, row 29) and the pad of the control terminal (Fig.7, element #28, column 7, row 24), producing a planar image (column 5, rows 17-19 and 24-29). Onodera does not teach the image is of the area around the pad. Thus, the combination of Imoto, Onodera, Watanabe and Kawanishi does not teach before the connection is made between the wiring member and the pad of the control terminal, producing a planar image of the area around the pad. Hieda teaches before the connection is made between the wiring member and the pad of the control terminal (Fig.4a, paragraph [0017], rows 1-4), producing a planar image of the area around the pad (paragraph [0019], rows 1-6). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Hieda and disclose producing a planar image of the area around the pad before the connection is made between the wiring member and the pad of the control terminal. The image allows an accurate measurement of the positioning parts location which is used by the bonding machine to precisely place the bonding wires and form reliable bonds.
The combination of Imoto, Onodera, Watanabe and Kawanishi does not teach connecting the wiring member to the pad on a basis of relative coordinates between the positioning part and the pad in the planar image. Hieda teaches connecting the wiring member to the pad on a basis of relative coordinates between the positioning part and the pad in the planar image (paragraph [0019], rows 1-6). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Hieda and disclose connecting the wiring member to the pad on a basis of relative coordinates between the positioning part and the pad in the planar image. This method only requires the precise location of the positioning parts, since the relative distance between the positioning parts and the electrode terminals and the bonding pads is known from design. Therefore, the method requires less amount of data to be stored and used by the bonding machine as compared to recording the absolute position of each terminal and bonding pads.
Regarding claim 11, Imoto teaches a method of manufacturing a semiconductor apparatus, comprising: preparing a semiconductor product that includes a semiconductor element with a top electrode(Fig.12, semiconductor element #4, paragraph [0012], row 6 is connected to the lead terminal, element #6, on the top side of the semiconductor), a control terminal (Fig.10, elements #8 and #6, paragraph [0012], rows 6-9), including a pad (Fig.12, element #6, paragraph [0012], rows 6-7) that is to be electrically connected to the top electrode of the semiconductor element through a wiring member (Fig.12, element #13, paragraph [0002], rows 4-5, and paragraph [0024], rows 5-6), and a case member (Fig.12, element #5, paragraph [0012], rows 5-6) in which at least a portion of the control terminal is embedded (Fig.10, paragraph [0012], rows 7-9) and which defines a space for housing the semiconductor element (Fig.2, there is a space between the left and right side of the walls made of element #5), the case member including a wiring member positioning part raised on the case member (Fig.10, protrusions, element s#14 are raised from the surface of the case member).
Imoto does not teach the positioning part is a reference point for positioning of the wiring member to be connected to the pad. Onodera teaches a wiring member positioning part raised from the surface (Fig.20, element #46 (30B) column 11, rows 60-63) is a reference point for a positioning of the wiring member before a connection is made of the wiring member to the pad (detection pf the positioning part location is stored in a memory unit and based on that, the wire bonding is performed column 5, rows 25-29). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Onodera and disclose a positioning part raised from the surface and used as a reference point before a connection is made of the wiring member to the pad. As Onodera disclosed, the raised positioning part may comprise of highly reflective materials that can be easily detected (column 10, rows 11-12 and 17-18) and thus provides a highly accurate reference point, which increases reliability of the wire bonding. Furthermore, the positioning part may be built simultaneously with other layers or parts of the device (column 10, rows 45-46) thus saving processing time and steps.
Imoto further teaches an encapsulating resin filling the space (Fig.1, element #9, paragraph [0012], row 9). The combination of Imoto and Onodera does not teach a coating film interposed between the positioning part and the encapsulating resin. Watanabe teaches a coating film (Fig.5, element #106, paragraph [0022], rows 7-8) interposed between the positioning part (Fig.5, element #107) and the encapsulating resin (Fig.5, element #504, paragraph [0044], rows 1-2). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Watanabe and disclose a coating film interposed between the positioning part and the encapsulating resin. The film can act as a protective layer against potential corrosion and comprises material with different reflectivity as compared to the case material, which will make the positioning part easier to locate on the case wall.
Imoto further teaches wherein the pad is provided in plurality as a pad group (Fig.10, element #6) and the plurality of pads in the pad group is arranged in a predetermined direction (Fig.6, direction parallel to the top surface of element #5b and the inside surface of element #5a), the positioning part is provided in plurality (Fig.10, element #14).
The combination of Imoto, Onodera and Watanabe does not teach two positioning parts among the plurality of positioning parts sandwich therebetween the pad group in the predetermined direction, one of the two positioning parts is disposed beside an outmost one of the plurality of pads at one of opposite ends of the pad group in the predetermined direction, and the other of the two positioning parts is disposed beside another outmost one of the plurality of pads at the other of the opposite ends of the pad group. Kawanishi teaches wherein the pad is provided in plurality as a pad group (Fig.2, pads, element #42 form pad groups consisting of 4 pads each),and the plurality of pads in the pad group is arranged in a predetermined direction (Fig.2, are arranged along x direction), the positioning part is provided in plurality (Fig.2, cross marks), two positioning parts among the plurality of positioning parts sandwich therebetween the pad group in the predetermined direction (Fig.2, cross marks adjacent to the second pad group from the top), one of the two positioning parts is disposed beside an outmost one of the plurality of pads at one of opposite ends of the pad group in the predetermined direction, and the other of the two positioning parts is disposed beside another outmost one of the plurality of pads at the other of the opposite ends of the pad group (Fig.2, the cross marks are beside outmost pads along x direction, on opposite ends of the pad group). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Kawanishi and disclose two positioning parts among the plurality of positioning parts sandwich therebetween the pad group in the predetermined direction, one of the two positioning parts is disposed beside an outmost one of the plurality of pads at one of opposite ends of the pad group in the predetermined direction, and the other of the two positioning parts is disposed beside another outmost one of the plurality of pads at the other of the opposite ends of the pad group. The presence of the two positioning parts which sandwich the pad group in the predetermined direction, and are located at opposite ends of the pad group, provide two sets of reference data for positioning the wiring members, which results in a more accurate determination of the pads location as compared to using a single positioning part.
The combination of Imoto and Watanabe does not teach producing a planar image of the area around the pad. Onodera teaches producing a planar image (column 5, rows 17-19 and 24-29) but does not teach the image is of the area around the pad. Hieda teaches producing a planar image of the area around the pad (paragraph [0019], rows 1-6). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Hieda and disclose producing a planar image of the area around the pad before the connection is made between the wiring member and the pad of the control terminal. The image allows an accurate measurement of the positioning parts locations which is used by the bonding machines to precisely place the boding wires and form reliable bonds.
The combination of Imoto, Onodera, Watanabe and Kawanishi does not teach connecting the wiring member to one of the plurality of pads on a basis of relative coordinates between one of the plurality of positioning parts and the one of the plurality of pads in the planar image. Hieda teaches connecting the wiring member to one of the plurality of pads on a basis of relative coordinates between one of the plurality of positioning parts and the pad in the planar image (paragraph [0019], rows 1-6). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Hieda and disclose connecting the wiring member to one of the plurality of pads on a basis of relative coordinates between one of the plurality of positioning parts and the one of the plurality of pads in the planar image. This method only requires the precise location of the positioning parts, since the relative distance between the positioning parts and the electrode terminals and the bonding pads is known from design. Therefore, the method requires less amount of data to be stored and used by the bonding machine as compared to recording the absolute position of each terminal and bonding pads.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Imoto, in view of Onodera, Watanabe, Kawanishi and in view of Norihiro Katayama, (United States Patent Application Publication Number US 2005/0155432 A1) hereinafter referenced as Katayama.
Regarding claim 12, the combination of Imoto, Onodera, Watanabe and Kawanishi teaches the semiconductor apparatus of claims 1 and 2 as set forth in the obviousness rejection. The combination of Imoto, Onodera, Watanabe and Kawanishi doesn’t teach wherein the coating film covers the step part of the case member. Katayama teaches wherein the coating film covers the step part of the case member (Fig.1, coating film, element #50, covers terminal element #30 which is embedded in a step formed between element #12 and the rest of the case, element #10). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Katayama and disclose wherein the coating film covers the step part of the case member. As disclosed by Katayama, the coating can be made of a material which is highly resistive to chemical substances and therefore acts as a protective layer for the terminals (paragraph [0028], rows 12-14).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Imoto, in view of Onodera, Watanabe, Kawanishi and in view of Shimazu, (Japanese Patent Publication Number, JP 2007242703A), hereinafter referenced as Shimazu.
Regarding claim 14, the combination of Imoto, Onodera, Watanabe and Kawanishi teaches the semiconductor apparatus of claim 1 as set forth in the obviousness rejection. Imoto teaches wherein each positioning part has a rectangular projecting shape. The combination of Imoto, Onodera, Watanabe and Kawanishi does not teach the semiconductor apparatus according to claim 1, wherein each positioning part has an upwardly projecting pin shape. Shimazu teaches wherein each positioning part has an upwardly projecting pin shape (Fig.4, element 26). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Shimazu and disclose each positioning part has an upwardly projecting pin. As disclosed by Shimazu, positioning pins can provide physical constrains and robustness that ensure superior precision and repeatability of the device assembly process, as compared to relying solely on optical positioning marks.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Imoto, in view of Onodera, Watanabe, Kawanishi and in view of Kotaro Kodani et al., (United States Patent Application Publication Number, US 2008/0245549 A1) hereinafter referenced as Kodani.
Regarding claim 15, the combination of Imoto, Onodera, Watanabe and Kawanishi teaches the semiconductor apparatus of claim 1 as set forth in the obviousness rejection. The combination of Imoto, Onodera, Watanabe and Kawanishi does not each the semiconductor apparatus according to claim 1, wherein a surface roughness of each of a surface of each positioning part and a surface of an area of the case member in which said each positioning part is disposed is in a range from 0.1 um to 5.0 um. Kodani teaches wherein a surface roughness of each of a surface of each positioning part and a surface of an area of the member in which said each positioning part is disposed is in a range from 0.1 um to 5.0 um (Fig.2, roughness of the top surface, element #11A, of the positioning part, element #13, is 0.1um or less, and roughness of the top surface, element #11B, of the member in which the positioning part is disposed, element #12, is between 0.2um and 0.6um (paragraph [0045], rows 1-8). It would have been obvious to one ordinary skilled in the art, before the effective filling date of the claimed invention, to optimize a surface roughness of the positioning part and a surface of an area of the case member in which said each positioning part is disposed through routine experimentation. The surface roughness is a result effective variable because, as disclosed by Kodani, when the surface roughness of the positioning part becomes large it is difficult to recognize the positioning part from its surroundings (paragraph [0042], rows 1-4). Furthermore, the surface roughness of the area of the member in which the positioning part is displaced has to be large enough to secure the adhesion of a resin layer to it (paragraph [0043], rows 4-8).
Response to Arguments
Applicant’s arguments filed on 10/20/2025 have been fully considered but they
are not persuasive. Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899