DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/6/2026 has been entered.
Claim Objections
In view of Applicant’s amendments, the prior objections are withdrawn.
Drawings
In view of Applicant’s amendments, the prior drawing objection is withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-5, 7, 9, 15-18, and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1 and 15 recite “wherein the frontside is entirely flat, including an area of the frontside that extends from the first integrated sensor circuit to the second integrated sensor circuit”. Nowhere is a frontside shown or described as now claimed. Though the specification describes e.g., skipping every other die for cutting (Instant: ¶38), this only shows that there may not be a groove or other synonymous feature between dies, not that the frontside is entirely flat, including an area of the frontside that extends from the first integrated sensor circuit to the second integrated sensor circuit.
Therefore, the quoted limitation above introduces new matter.
Claims 2-5, 7, 9, 16-18, and 20 inherit this rejection for new matter.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-5, 7, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Astegher et al. (US 2016/0025529), Rasbornig et al. (US 2013/0200909), and Kolb et al. (US 2006/0202291), all of record.
(Re Claim 1) Astegher teaches a sensor chip, comprising: a semiconductor substrate (the semiconductor chip as described in ¶¶31-32 that is part of the common semiconductor chip); a first integrated sensor circuit (110; e.g., XMR sensor Fig. 1, ¶¶25, 32) monolithically integrated (¶¶31-32) on the semiconductor substrate; and a second integrated sensor circuit (120; e.g., XMR sensor, Fig. 1, ¶¶25, 32) monolithically integrated (¶¶31-32) on the semiconductor substrate.
Astegher does not explicitly teach a sensor chip wherein the semiconductor substrate has a frontside and backside opposite to the frontside; the first and the second integrated sensor circuits are monolithically integrated into the semiconductor substrate at the frontside and embodied identically,
wherein the frontside is entirely flat, including an area of the frontside that extends from the first integrated sensor circuit to the second integrated sensor circuit.
Kolb teaches monolithically integrating an integrated sensor circuit (104+other elements above 102; Fig. 1) into a semiconductor substrate (102; Fig. 1).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the first and second integrated sensor circuits of Astegher monolithically integrated into the semiconductor substrate of the common semiconductor chip, as taught by Kolb, as conventional processing may be used to each complete integrated sensor circuit (Kolb: ¶73) and cost and performance may be improved (Kolb: ¶78). See also Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Astegher teaches forming a first integrated sensor circuit (210; Fig. 2B) and a second integrated sensor circuit (220; Fig. 2B), adjacent to each other, and on separate semiconductor substrates (left and right 202; Fig. 2B) that have a frontside (top side as seen in Fig. 2B) and backside (bottom as seen in Fig. 2B) opposite to the frontside, where the integrated sensor circuits monolithically integrated into the semiconductor substrate at the respective frontside of the semiconductor substrates, wherein the frontside is entirely flat (Fig. 2B).
A PHOSITA would find it obvious to form first and second integrated circuits 110 and 120 of modified Astegher such that they are at a frontside of the semiconductor substrate, as shown in Fig. 2B, to allow for access to interconnects for signal output.
After forming the first and second integrated sensor circuits of modified Astegher in the common semiconductor substrate, the resulting structure is demonstrated in the markup based on Fig. 2B below (including a frontside, and a backside opposite the frontside respectively corresponding to the top and bottom sides of the semiconductor substrate).
Therefore, modified Astegher also teaches the frontside is entirely flat, including an area of the frontside that extends from the first integrated sensor circuit to the second integrated sensor circuit (the area around each integrated sensor circuit in Fig. 2B is shown to be entirely flat).
Rasbornig teaches that it is conventional to use two identical redundant sensors (¶5).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the sensor chip of Astegher such that the first and second integrated sensor circuit are embodied indentically, as taught by Rasbornig, as this is a conventional way to achieve a redundant circuit configuration (Astegher: ¶58). See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
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(Re Claim 2) Modified Astegher teaches the sensor chip as claimed in claim 1, wherein the first and the second integrated sensor circuits are arranged laterally adjacently on the semiconductor substrate (Fig. 1).
(Re Claim 3) Modified Astegher teaches the sensor chip as claimed in claim 1, wherein the semiconductor substrate, the first integrated sensor circuit, and the second integrated sensor circuit are embodied integrally (¶¶31-32).
(Re Claim 4) Modified Astegher teaches the sensor chip as claimed in claim 1, wherein the first and the second integrated sensor circuits are redundant sensors (Rasbornig: ¶5).
(Re Claim 5) Modified Astegher teaches the sensor chip as claimed in claim 1, further comprising a common chip package (130; Fig. 1) that encapsulates (¶20) the first and the second integrated sensor circuits integrated jointly on the semiconductor substrate.
(Re Claim 7) Modified Astegher teaches the sensor chip as claimed in claim 1, wherein each of the first and the second integrated sensor circuits comprise sensor circuits from a set of magnetic sensor circuits (XMR sensors; Astegher: ¶58; Rasbornig: ¶23), radar sensor circuits, and MEMS sensor circuits for providing sensor signals.
(Re Claim 9) Modified Astegher teaches the sensor chip as claimed in claim 1, wherein a plurality of identical integrated sensor circuits (110 and 120 of modified Astegher) including the first integrated sensor circuit and the second integrated sensor circuit, are arranged in a two-dimensional matrix arrangement (Fig. 1) that is integrated into the semiconductor substrate of the sensor chip (Fig. 1).
Claims 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Astegher et al. (US 2016/0025529), Rasbornig et al. (US 2013/0200909), Kolb et al. (US 2006/0202291), and Keser et al. (US 2017/0343608), Doogue et al. (US 2013/0015843), and Raberg (US 2013/0278250), all of record.
(Re Claim 15) Astegher teaches a sensor chip, comprising: a semiconductor substrate (semiconductor substrate described in ¶¶31-32 that is part of the common semiconductor chip); a first integrated sensor circuit (110; e.g., XMR sensor Fig. 1, ¶¶25, 32) monolithically integrated (¶¶31-32) on the semiconductor substrate; and a second integrated sensor circuit (120; e.g., XMR sensor, Fig. 1, ¶¶25, 32) monolithically integrated (¶¶31-32) on the semiconductor substrate.
Astegher does not explicitly teach a sensor chip comprising a semiconductor substrate having a frontside and backside opposite to the frontside, a first and second integrated sensor circuit monolithically integrated into the semiconductor substrate at the frontside, wherein the first and the second integrated sensor circuits are embodied identically, wherein the frontside is entirely flat, including an area of the frontside that extends from the first integrated sensor circuit to the second integrated sensor circuit, wherein the first integrated sensor circuit comprises: a first plurality of sensor elements configured to provide a first differential measurement; a first differential amplifier configured to amplify the first differential measurement to generate a first amplified differential measurement; and a first operational amplifier configured to generate a first analog output signal based on the first amplified differential measurement received at an input of the first operational amplifier, wherein the second integrated sensor circuit comprises: a second plurality of sensor elements configured to provide a second differential measurement; a second differential amplifier configure to amplify the second differential measurement to generate a second amplified differential measurement; and a second operational amplifier configured to generate a second analog output signal based on the second amplified differential measurement received at an input of the second operational amplifier, wherein the first plurality of sensor elements and the second plurality of sensor elements are embodied identically, wherein the first differential amplifier and the second differential amplifier are embodied identically, and wherein the first operational amplifier and the second operational amplifier are embodied identically.
Kolb teaches monolithically integrating an integrated sensor circuit (104+other elements above 102; Fig. 1) into a semiconductor substrate (102; Fig. 1).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the first and second integrated sensor circuits of Astegher monolithically integrated into the semiconductor substrate of the common semiconductor chip, as taught by Kolb, as conventional processing may be used to each complete integrated sensor circuit (Kolb: ¶73) and cost and performance may be improved (Kolb: ¶78). See also Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Astegher teaches forming a first integrated sensor circuit (210; Fig. 2B) and a second integrated sensor circuit (220; Fig. 2B), adjacent to each other, and on separate semiconductor substrates (left and right 202; Fig. 2B) that have a frontside (top side as seen in Fig. 2B) and backside (bottom as seen in Fig. 2B) opposite to the frontside, where the integrated sensor circuits monolithically integrated into the semiconductor substrate at the respective frontside of the semiconductor substrates, wherein the frontside is entirely flat (Fig. 2B).
A PHOSITA would find it obvious to form first and second integrated circuits 110 and 120 of modified Astegher such that they are at a frontside of the semiconductor substrate, as shown in Fig. 2B, to allow for access to interconnects for signal output.
After forming the first and second integrated sensor circuits of modified Astegher in the common semiconductor substrate, the resulting structure is demonstrated in the markup based on Fig. 2B below (including a frontside, and a backside opposite the frontside respectively corresponding to the top and bottom sides of the semiconductor substrate).
Rasbornig teaches that it is conventional to use two identical redundant sensors (¶5).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the sensor chip of Astegher such that the first and second integrated sensor circuit are embodied identically, as taught by Rasbornig, as this is a conventional way to achieve a redundant circuit configuration (Astegher: ¶58). See Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Doogue teaches an integrated sensor circuit (53; Fig. 3, ¶35), wherein the integrated sensor circuit comprises: a first plurality of sensor elements (54; 54 may be multiple MR elements connected in a bridge circuit; ¶35) configured to provide a first measurement (“stage 60 can be implemented…to amplify and condition the sensing element’s magnetic field signal output”; ¶31);
a first differential amplifier (110; Fig. 4B) configured to amplify the first measurement (amplified measurement 88; ¶33); and
a first operational amplifier (96; Fig. 3) configured to generate a first analog output signal (analog output voltage Vout 58; Fig. 3, ¶36), based on the first amplified measurement received at an input of the first operational amplifier (Fig. 3, ¶34).
Doogue also teaches that the sensor elements (54; Fig. 3) may alternatively be hall effect or magnetoresistance elements (¶35).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to use the integrated sensor circuit 53 of Doogue for the first and second integrated sensor circuits of modified Astegher, as the integrated sensor circuit of Doogue allows for self-calibration of sensor output signals (Doogue: ¶26), and is suitable for sensor elements that are either hall effect or magnetoresistance based sensors (Astegher: ¶25; Doogue: ¶35).
As Astegher in view of Rasbornig has the first and second integrated sensor circuits embodied identically, modified Astegher in view of Doogue teaches the sensor chip, wherein the first integrated sensor circuit comprises:
a first plurality of sensor elements (Doogue: 54; 54 may be multiple MR elements connected in a bridge circuit; ¶35) configured to provide a first measurement;
a first differential amplifier (Doogue: 110; Fig. 4B) configured to amplify the first differential measurement to generate a first amplified measurement (Doogue: Fig.3, ¶34); and a first operational amplifier (Doogue: 96; Fig. 3) configured to generate a first analog output signal (Doogue: analog output voltage Vout; Fig. 3, ¶36) based on the first amplified measurement received at an input of the first operational amplifier (Doogue: Fig. 3, ¶34), and
wherein the second integrated sensor circuit comprises: a second plurality of sensor elements (Doogue: 54; 54 may be multiple MR elements connected in a bridge circuit; ¶35) configured to provide a second measurement (Doogue: “stage 60 can be implemented…to amplify and condition the sensing element’s magnetic field signal output”; ¶31);
a second differential amplifier (Doogue: 110; Fig. 4B) configured to amplify the second measurement to generate a second amplified measurement (Doogue: amplified measurement 88; ¶33); and a second operational amplifier (Doogue: 96; Fig. 3) configured to generate a second analog output signal (Doogue: analog output voltage Vout; Fig. 3, ¶36) based on the second amplified measurement received at an input of the second operational amplifier Doogue: Fig. 3, ¶34), wherein the first plurality of sensor elements and the second plurality of sensor elements are embodied identically, wherein the first differential amplifier and the second differential amplifier are embodied identically, and wherein the first operational amplifier and the second operational amplifier are embodied identically (these elements are embodied identically in view of Rasbornig teaching identical redundant sensors; Rasbornig: ¶5).
Modified Astegher has not been shown to explicitly teach that the first and second measurements, and the first and second amplified measurements, are respectively differential measurements and amplified differential measurements.
Keser teaches forming a plurality of sensor elements (517+518+519+520; Fig. 5) that form a magnetoresistive sensor (515; ¶56) in a wheatstone bridge configuration (¶56), configured to provide a first differential measurement (the amplifier 521 has tapping nodes between 517 and 519, and between 518 and 520; Fig. 5, ¶56).
A PHOSITA would find it obvious to use the bridge configuration of 517, 518, 519, and 520 within the sensor 515 of Keser for the bridge configuration of element 54 taught by Doogue and used for the first and second integrated sensor circuits of modified Astegher, as wheatstone bridge configurations avoid issues with thermal drift (Raberg: Fig.1, ¶45). This results in the element 54 of Doogue being the bridge configuration comprising elements 517, 518, 519, 520 of Keser.
Furthermore, a PHOSITA would find it obvious to utilize only the amplifier 521 of Keser that is configured to produce a differential measurement from the bridge configuration of Keser for the components of the sensing interface stage 60 of Doogue, as “components to be included in the stage 60 can vary with the type of sensing technology that is chosen” (Doogue: ¶35; note also the presence of an amplifier 68 in Fig. 3), and Keser shows that a single amplifier component 521 is sufficient to produce a differential measurement that may undergo further processing when utilizing the MR-based sensor element bridge configuration of Keser (Doogue: ¶35; Keser: ¶56). Reducing the number or types of components also reduces manufacturing defects that would occur due to additional processing steps or a larger utilized area. See also Ruiz v. A.B. Chance Co., 357 F.3d 1270, 69 USPQ2d 1686 (Fed. Cir. 2004).
Doing so results in the first and second differential amplifiers being the combination of Doogue’s 110 and Keser’s 521, where Keser’s 521 is the sole component of Doogue’s stage 60.
This results in modified Astegher teaching the first and second measurements are first and second differential measurements, and the first and second amplified measurements are first and second amplified differential measurements, as the output from the first and second plurality of sensor elements is now from a differential amplifier (Keser: 521).
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(Re Claim 20) Modfied Astegher teaches the sensor chip as claimed in claim 15, wherein the first plurality of sensor elements are arranged in a first Wheatstone bridge circuit (Keser: Fig. 5, ¶56), and wherein the second plurality of sensor elements are arranged in a second Wheatstone bridge circuit (Keser: Fig. 5, ¶56) identical to the first Wheatstone bridge circuit (Rasbornig: ¶5; see also the corresponding discussion in the rejection of claim 15).
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Astegher et al. (US 2016/0025529), Rasbornig et al. (US 2013/0200909), Kolb et al. (US 2006/0202291), and Keser et al. (US 2017/0343608), Doogue et al. (US 2013/0015843) and Raberg (US 2013/0278250), all of record, as applied to claim 15 above, and further in view of Chen (US 6,338,032) of record.
(Re Claim 16) Modified Astegher teaches the sensor chip as claimed in claim 15, but does not explicitly teach the sensor chip wherein the first integrated sensor circuit comprises a first digital-to-analog converter configured to calibrate the first differential amplifier for offset or temperature, wherein the second integrated sensor circuit comprises a second digital-to-analog converter configured to calibrate the second differential amplifier for offset or temperature, and wherein the first digital-to-analog converter and the second digital-to-analog converter are embodied identically.
Chen teaches using a digital-to-analog converter (e.g., DAC above leader for 14; Fig. 1) configured to calibrate (col. 4 ln. 39-44) a differential amplifier (CKT 1; Fig. 1) for offset (col. 4 ln. 39-44).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to calibrate both the first and second differential amplifier (Either Keser’s 521 or Doogue’s 110) using a respective first and second digital-to-analog converter for offset, as taught by Chen, to cause differential amplifier’s to have performance consistent with required specifications (Chen: col. 1 ln. 10-16).
As the integrated sensor circuits are embodied identically (see the rejection of claim 15 above), the first digital-to-analog converter and the second digital-to-analog converter are embodied identically.
(Re Claim 17) Modified Astegher teaches the sensor chip as claimed in claim 16, but does not explicitly teach the sensor chip wherein the first digital-to-analog converter is configured to calibrate the first differential amplifier based on first laser fuses provided in the first integrated sensor circuit, wherein the second digital-to-analog converter is configured to calibrate the second differential amplifier based on second laser fuses provided in the second integrated sensor circuit, and wherein the first laser fuses and the second laser fuses are embodied identically.
Chen teaches the digital-to-analog converter (e.g., DAC above leader for 14; Fig. 1) is configured to calibrate the differential amplifier (CKT 1; Fig. 1) based on laser fuses (44; col. 5 ln. 24-39) provided in an integrated circuit (10; Fig. 1).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to have both the first and second digital-to-analog converters of modified Astegher configured to respectively calibrate the first and second differential amplifiers based on respective first and second laser fuses provided in the respective first and second integrated sensor circuits, as taught by Chen, as this allows for permanent calibration (col. 5 ln. 24-26).
As the integrated sensor circuits are embodied identically (see the rejection of claim 15 above), the first laser fuses and the second laser fuses are embodied identically
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Astegher et al. (US 2016/0025529), Rasbornig et al. (US 2013/0200909), Kolb et al. (US 2006/0202291), and Keser et al. (US 2017/0343608), Doogue et al. (US 2013/0015843) and Raberg (US 2013/0278250), all of record as applied to claim 15 above, and further in view of Cummings et al. (US 2009/0212771) of record.
(Re Claim 18) Modified Astegher teaches the sensor chip as claimed in claim 15, but has not been shown to explicitly teach the sensor chip wherein the first integrated sensor circuit comprises a first power management unit configured to supply electrical supply energy to the first plurality of sensor elements, the first differential amplifier, and the first operational amplifier, the second integrated sensor circuit comprises a second power management unit configured to supply electrical supply energy to the second plurality of sensor elements, the second differential amplifier, and the second operational amplifier, and wherein the first power management unit and the second power management unit are embodied identically.
Cummings et al. (US 2009/0212771) teaches using a power management unit (36; Fig. 5) configured to supply electrical energy to all subcircuits (Fig. 5).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form first and second integrated sensor circuit with a respectively first and second power management unit 36 as taught by Cummings, and configured to supply electrical supply energy to the respective first and second sensor elements, differential amplifiers, and operational amplifiers, as this allows for each of these subcircuits of modified Astegher to receive a substantially constant voltage (Cummings: ¶23), reducing errors or damage due to voltage excursions.
As the integrated sensor circuits are embodied identically (see the rejection of claim 15 above), the first power management unit and the second power management unit are embodied identically.
Response to Arguments
Applicant's arguments filed 4/6/2026 have been fully considered but they are moot in view of the new rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee (US 2014/0124956) teaches that an entire frontside of a die may be flat (Fig. 1A; "Top surfaces and bottom surfaces of the first unit semiconductor chip, the second unit semiconductor chip, and the corresponding boundary region may be horizontally flat. The first unit semiconductor chip, the second unit semiconductor chip, and the corresponding boundary region may be horizontally physically continuous for each of the first to fourth semiconductor devices” (¶12)).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher A Schodde whose telephone number is (571)270-1974. The examiner can normally be reached M-F 1000-1800 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571)272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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