DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Applicant's remarks , filed on 02/04/2026, with respect to the rejection(s) of claim 1 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of U.S. Patent Application Publication No. US 20170092743 A1 (“OKUMURA”).
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/04/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3,5, 7-9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over OKUMURA et al. (US20170092743A1) in view of Cheng et al. (US20130134512A1).
Regarding claim 1, Annotated Fig.23 of OKUMURA teaches a semiconductor device comprising:
a semiconductor substrate 8 (para.0121) including a surface 9 (para.0121) and a convex portion (see annotated Fig.23) protruding upward from the surface 9;
a gate electrode 20 (para.0130) arranged on the surface of the semiconductor substrate 8; a source region 15 (para.0125) of a first conductivity type (n.sup.+-type ) and a drain region 15 (para.0125) of the first conductivity type (n.sup.+-type ), the source region 15 and the drain region 15 being arranged at the surface of the semiconductor substrate 8;
a first region 97 (para.0238) of the first conductivity type arranged in the semiconductor substrate 8 so as to be positioned between the gate electrode 20 and the drain region 15 in plan view, the first region 97 having an impurity concentration lower than an impurity concentration of the drain region 15; a second region 98 (para.0238) of a second conductivity type (para.0243, a p.sup.−-type ) arranged in the convex portion (see annotated Fig.23) such that the second region 98 is located higher than the source region 15 and the drain region 15 in a thickness direction of the semiconductor substrate 8, the second region 98 forming a pn junction with the first region 97; a body region 12 (para.0124) of the second conductivity type (a p.sup.−-type) arranged in the semiconductor substrate 8, the body region 12 forming a pn junction with the source region 15.
Annotated Fig.23
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OKUMURA does not disclose an interlayer insulating layer arranged on the surface of the semiconductor substrate so as to cover the gate electrode;
a contact hole provided in the interlayer insulating layer; and
a contact conductive layer embedded in the contact hole and connected to an upper surface of the convex portion,
wherein the second region is electrically connected to any one of the gate electrode and a ground potential via the contact conductive layer.
Fig.7 of Cheng teaches a power MOSFET that includes a semiconductor region (para.0025) extending from a top surface of a semiconductor substrate 20 (para.0007) into the semiconductor substrate 20, wherein the semiconductor region (para.0025) is of a first conductivity type and an interlayer insulating layer 66 (para.0020) arranged on the surface of the semiconductor substrate 20 so as to cover the gate electrode 34 (para.0018);
a contact hole (contact plugs 64 pass through holes in the interlayer dielectric layer 66) provided in the interlayer insulating layer 66; and
a contact conductive layer 64 (para.0020) embedded in the contact hole and connected to an upper surface of the convex portion,
wherein the second region 38 (para.0010) is electrically connected to any one of the gate electrode and a ground potential via the contact conductive layer 64.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the contacts and the interlayer dielectric layer of Cheng in the teachings of OKUMURA in order for the contact plugs to provide electrical access to the gate electrode and for the interlayer dielectric layer to provide insulation between components.
Regarding claim 2, OKUMURA further teaches the semiconductor device according to claim 1, wherein the first region 97 (para.0238) includes:
a first semiconductor region 97 (para.0238) arranged below the convex portion (see annotated Fig.23); and
a second semiconductor region 98 (para.0238) arranged in the convex portion (see annotated Fig.23) so as to form a pn junction with the second region 98.
Regarding claim 3, OKUMURA further teaches the semiconductor device according to claim 2, wherein an impurity concentration of the first conductivity type in the second semiconductor region 98 (para.0238) is equal to an impurity concentration of the first conductivity type in the first semiconductor region 97 (para.0238, wherein as the interbody region 97 has a protrusion 98 projecting from a surface 9 of the epitaxial layer 8 to be raised with respect to the surface 9 of the epitaxial layer 8, the conductivity type (n.sup.−-type) of the epitaxial layer 8 is maintained).
Regarding claim 5, OKUMURA further teaches the semiconductor device according to claim 1, wherein an impurity concentration of the second conductivity type (a p.sup.−-type) in the second region 98 (para.0238) is equal to or larger than the impurity concentration of the first conductivity type in the first region 97 (para.0238).
Regarding claim 7, OKUMURA further teaches the semiconductor device according to claim 1, wherein the gate electrode 20 (para.0130) is formed on the convex portion (see annotated Fig.23).
Regarding claim 8, OKUMURA further teaches the semiconductor device according to claim 1, wherein the convex portion (see annotated Fig.23) is arranged so as to individually surround a periphery of each of the drain region 15 (para.0129) and the source region 15 (para.0129) in plan view.
Regarding claim 9, the combination of OKUMURA and Cheng teaches the semiconductor device according to claim 8, comprising a contact conductive layer 64 (Cheng, para.0020) connected to the second region 98 (OKUMURA, para.0238),
wherein the contact conductive layer 64 is arranged in a second direction perpendicular to a first direction toward the drain region 15 (OKUMURA, para.0129) with respect to the source region 15 (OKUMURA, para.0129) in plan view.
Regarding claim 11, OKUMURA further teaches the semiconductor device according to claim 1, wherein the drain region 15 (para.0129) is arranged at a distance from the second region 98 (para.0238) in plan view.
Claims 6 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over OKUMURA et al. (US20170092743A1) in view of Cheng et al. (US20130134512A1) and in further view of Snyder et al. (US9171916B1).
Regarding claim 6, the combination of OKUMURA and Cheng does not teach wherein a side surface of the convex portion is configured by an inclined surface of {111} plane.
Fig.5 of Snyder teaches wherein device 300 has a convex portion that includes:
both side surfaces to be inclined surfaces in a cross section; and
an upper surface which is a flat surface connected to an upper end of each of the both side surfaces.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include device 300, having two inclined surfaces with a flat upper surface, of Snyder in the teachings of OKUMURA, as modified by Cheng, because inclined surfaces create a more gradual transition and allow new material to deposit in a more uniform and continuous film.
Regarding claim 10, the combination of OKUMURA and Cheng further teaches wherein the contact conductive layer 64 (Cheng, para.0020) is connected to the upper surface of the convex portion (see annotated 23).
However, the combination of OKUMURA and Cheng does not disclose wherein the convex portion includes:
both side surfaces to be inclined surfaces in a cross section; and
an upper surface which is a flat surface connected to an upper end of each of the both side surfaces.
Fig.5 of Snyder teaches wherein device 300 has a convex portion that includes:
both side surfaces to be inclined surfaces in a cross section; and
an upper surface which is a flat surface connected to an upper end of each of the both side surfaces.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include device 300, having two inclined surfaces with a flat upper surface, of Snyder in the teachings of OKUMURA, as modified by Cheng, because inclined surfaces create a more gradual transition and allow new material to deposit in a more uniform and continuous film.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over OKUMURA et al. (US20170092743A1) in view of Cheng et al. (US20130134512A1) and in further view of Rhee et al. (US20090170254A1).
Regarding claim 13, the combination of OKUMURA and Cheng further teaches the semiconductor device according to claim 1, comprising
a first transistor and a second transistor different from the first transistor, the first transistor including the source region 15 (OKUMURA, para.0125), the drain region 15 (OKUMURA, para.0125) and the gate electrode 20 (OKUMURA, para.0130),
However, OKUMURA, as modified by Cheng, does not teach wherein a source region of the second transistor and a drain region of the second transistor are arranged at a height position different from a height position of the source region of the first transistor and a height position of the drain region of the first transistor.
Fig.17 of Rhee teaches a semiconductor device with first transistor and second transistor; wherein a source region 224 (para.0097) of the second transistor 222 (para.0096) and a drain region 224 (para.0097) of the second transistor 222 are arranged at a height position different from a height position of the source region 232 (para.0098) of the first transistor 234 (para.0096) and a height position of the drain region 232 (para.0098) of the first transistor 234.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Rhee’s second transistor in the teachings of OKUMURA, as modified by Cheng, in order to provide a different conductivity type.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891