DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Continued Examination Under 37 CFR 1.114
5. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9/25/2025 has been entered.
Response to Arguments
6. Applicant’s arguments, see Claim Rejections under 35 U.S.C. §§ 102 & 103, filed 6/26/2025, with respect to the rejection of claim 1 under 35 U.S.C. § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Loo, Kum-Weng et al. (Pub No. US 20110018125 A1) (hereinafter, Loo) in view of Saeidi, Seyed Mahdi et al. (Pub No. US 20140061893 A1) (hereinafter, Saeidi).
7. Applicant’s arguments, see Claim Rejections under 35 U.S.C. §§ 102 & 103, filed 6/26/2025, with respect to the rejection of claim 14 under 35 U.S.C. § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Saeidi, Seyed Mahdi et al. (Pub No. US 20140061893 A1) (hereinafter, Saeidi) in view of Im, Yun-Hyeok (Pub No. US 20030085475 A1) (hereinafter, Im).
8. Applicant’s arguments, see Claim Rejections under 35 U.S.C. §§ 102 & 103, filed 6/26/2025, with respect to the rejection of claim 20 under 35 U.S.C. § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Saeidi, Seyed Mahdi et al. (Pub No. US 20140061893 A1) (hereinafter, Saeidi) in view of Lin, Tsung-Shu et al. (Pub No. US 20210366889 A1) (hereinafter, Lin) in view of Yamazaki, Kozo et al. (Pub No. JP 2004311598 A) (hereinafter, Yamazaki).
Claim Rejections - 35 USC § 103
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claims 1-2 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Loo, Kum-Weng et al. (Pub No. US 20110018125 A1) (hereinafter, Loo), and further in view of Saeidi, Seyed Mahdi et al. (Pub No. US 20140061893 A1) (hereinafter, Saeidi).
Figure 6 - Semiconductor Package (Loo)
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Re Claim 1, (Currently Amended) Loo teaches a semiconductor package comprising:
a substrate (Printed wire board; 10; Fig 6; ¶[0004]) comprising, at an upper surface (Upper surface; Fig 6) thereof, an inner area (Area surrounding die 12; Fig 6; See Fig 6 above labelled IA), and an edge area (Area from edge of die 12 to edge of printed wire board 10; Fig 6; See Fig 6 above labelled EA) surrounding the inner area;
a chip set (Die; 12; Fig 6; ¶[0023]) on the inner area of the substrate;
a stiffener set (Stiffening ring/passive component/heat spreader; 60/40/44; Fig 6; ¶¶[0023,0024]) on the edge area of the substrate, the stiffener set comprising a first stiffener and a second stiffener (Pairs of stiffening ring/passive components; 60/40; Fig 6; ¶¶[0023,0024]) spaced apart from one another; and
wherein the first stiffener comprises a pillar region (Pillar portion of 60; Fig 6) and a roof region (Portion of 60 which hangs over passive component 40; Fig 6), the roof region protruding from an upper surface (Horizontal plane located at corner of 60; Fig 6) of the pillar region and being above the second stiffener,
the roof region does not overlap (Roof of 60 doesn’t overlap IA) the inner area in a plan view (Vertical view (not shown); Note: Fig. 6 in the vertical view would not have 60 overlap any portion of the inner area where chip set 12 is located, as it forms a ring structure per ¶[0024]),
an inner side surface (Surface facing inner area IA; Fig 6) of the roof region facing the inner area is horizontally spaced apart from a side surface (Side surface of die 12; Fig 6) of the chip set on the inner area.
However, Loo does not teach an adhesive member attaching the first stiffener and the second stiffener to the substrate,
the second stiffener has a pillar-shaped cross-section that has a height greater than a width, is horizontally spaced apart from the pillar region, and is closer to the inner area than the pillar region,
a bottom surface of the roof region is at a higher position than the chip set.
In the same field of endeavor, Saeidi teaches an adhesive member (Second TIM/Adhesive; 1304/314; Fig 13; Per ¶[0070] Second TIM provides adhesion) attaching the first stiffener (Heat spreader lid; 302; Fig 13; ¶[0067]) and the second stiffener (Pair of Stiffeners; 1302; Fig 13; ¶[0067]) to the substrate (308; Fig 13; Per ¶[0031]).
the second stiffener is horizontally spaced apart from the pillar region (Peripheral pillars supports of 302; Fig 13), and is closer to the inner area (IA; Fig 6) than the pillar region,
the roof region (Roof of 302 which hangs over chip 304; Fig 13) extends horizontally toward the inner area such that the roof region overlaps the second stiffener in a plan view (Per ¶[0035] Heat spreader lid 302 encloses die 304 from the top side and lateral sides (surfaces that are perpendicular to surface 310 of substrate 308)), and
a bottom surface (Bottom surface of 302) of the roof region is at a higher position (Bottom surface of 302 is higher than 304) than the chip set (Die; 304; Fig 13; ¶[0035]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used an adhesive member attaching the plurality of stiffeners to the substrate, the second stiffener has a pillar-shaped cross-section that has a height greater than a width, is horizontally spaced apart from the pillar region, and is closer to the inner area than the pillar region and the roof region extends horizontally toward the inner area such that the roof region overlaps the second stiffener in a plan view, and a bottom surface of the roof region is at a higher position than the chip set, as taught by Saeidi. One would have been motivated to do this with a reasonable expectation of success because the adhesive and second TIM provides greater stiffness/rigidity and adhesion, reducing warp of package (Saeidi, ¶[0070]). Further, it would be rendered obvious to place the roof region at a higher position than the chip set (die), such that the roof of the heat spreader lid or its equivalent may provide environmental protection and EMI shielding for the chip set, given its ring shape which surrounds the chip set, as suggested by Saeidi (¶[0036]).
Re Claim 2, (Previously Presented) Loo teaches the semiconductor package according to The semiconductor package according to claim 1, wherein:
the first stiffener (Stiffening ring; 60; Fig 6; ¶[0024]) surrounds the second stiffener (Passive component; 40; Fig 6; ¶[0023]).
Re Claim 12, (Original) Loo teaches the semiconductor package according to claim 1, wherein an outer side surface of the stiffener set (Stiffening ring/passive component/heat spreader; 60/40/44; Fig 6; ¶¶[0023,0024]) is vertically aligned with an outer side surface of the substrate (Printed wire board; 10; Fig 6; ¶[0004]) .
Re Claim 13, (Original) Loo teaches the semiconductor package according to claim 1, wherein the stiffener set (Stiffening ring/passive component/heat spreader; 60/40/44; Fig 6; ¶¶[0023,0024]) does not contact the chip set (Die; 12; Fig 6; ¶[0023]; Note: The heat spreader contacts the thermally conductive material 20 and does not the die 12).
11. Claims 3-5 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Loo, Kum-Weng et al. (Pub No. US 20110018125 A1) (hereinafter, Loo) in view of Saeidi, Seyed Mahdi et al. (Pub No. US 20140061893 A1) (hereinafter, Saeidi) as applied to claim 2, and further in view of Yamazaki, Kozo et al. (Pub No. JP 2004311598 A) (hereinafter, Yamazaki).
Re Claim 3, (Original) Loo does not teach the semiconductor package according to claim 2, wherein a coefficient of thermal expansion (CTE) of the first stiffener, a CTE of the second stiffener, and a CTE of the chip set, and a CTE of the substrate are different.
In the same field of endeavor, Saeidi teaches the semiconductor package according to claim 2, wherein a coefficient of thermal expansion (CTE) of the first stiffener (Heat spreader lid; 302; Fig 13; Per ¶[0036] used for warp reduction acting as a stiffener; CTE may be of Stainless Steel; 10-17.3 ppm/C), a CTE of the second stiffener (Stiffener; 1302; Fig 13; Per ¶[0073] may be Ceramic such as Silicon Nitride; CTE of less than 7.5 ppm/C), and a CTE of the substrate (308; Fig 13; Per ¶[0031] may be electrically insulating layers such as ceramic, plastic, tape etc. or organic material such as BT (bismaleimide triazine) laminate/resin, a flexible tape material such as polyimide, a flame retardant fiberglass composite substrate board material) are different.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used made the CTE of the first and second stiffener and CTE of the substrate different, as taught by Saeidi. One would have been motivated to do this with a reasonable expectation of success because the substrate is preferably composed of conductive layers in between insulating layers, and the insulating layers reduce warpage towards adhesives or the die, due to lessening thermal expansion (Saeidi, ¶[0006]).
However, Loo in view of Saeidi does not teach the CTE of the chip set.
In the same field of endeavor, Yamazaki teaches the CTE of the chip set (Semiconductor element; 21; Fig 1; Per ¶[Abstract, 0008] semiconductor element has CTE of 5 ppm/C and dielectric constant of 4 ppm/C and is therefore an insulating material).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a chip set with a CTE different from the stiffeners and substrate, as taught by Yamazaki. One would have been motivated to do this with a reasonable expectation of success because the resin substrate can sufficiently withstand thermal stress caused by a difference in thermal expansion coefficient from the chip, and the entire semiconductor package is less likely to warp toward the chip mounting surface, thus preventing the chip from warping (Yamazaki, ¶[0050]).
Re Claim 4, (Original) Loo does not teach the semiconductor package according to claim 3, wherein each of the CTE of the first stiffener and the CTE of the second stiffener is greater than both the CTE of the chip set and the CTE of the substrate.
In the same field of endeavor, Saeidi teaches the semiconductor package according to claim 3, wherein each of the CTE of the first stiffener (Heat spreader lid; 302; Fig 13; Per ¶[0036] CTE of Stainless Steel 10-17.3 ppm/C) and the CTE of the second stiffener (Stiffener; 1302; Fig 13; Per ¶[0073] may be Ceramic such as Silicon Nitride; CTE of less than 7.5 ppm/C) is greater than the CTE of the substrate (308; Fig 13; Per ¶[0031] may be electrically insulating layers such as ceramic, plastic, tape etc. or organic material such as BT (bismaleimide triazine) laminate/resin, a flexible tape material such as polyimide, a flame retardant fiberglass composite substrate board material).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used the first and second stiffeners with a CTE greater than that of the substrate, as taught by Saeidi. One would have been motivated to do this with a reasonable expectation of success because the first and second stiffeners are thermally conductive in order to dissipate heat, whereas the CTE of the substrate requires a CTE is designed to reduce package warping (Saeidi, ¶[0006]).
However, Loo in view of Saeidi does not teach the CTE of the chip set.
In the same field of endeavor, Yamazaki teaches wherein each of the CTE of the stiffeners (Stiffeners; 31; Fig 1; Per ¶[0041] plate-shaped member made of Invar (Fe-Ni alloy)) is greater that the CTE of the chip set (Semiconductor element; 21; Fig 1; Per ¶[Abstract, 0008] semiconductor element has CTE of 5 ppm/C).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used the first and second stiffeners with a CTE greater than that of the chip set, as taught by Yamazaki. One would have been motivated to do this with a reasonable expectation of success because using the LSI chip 21 having a low dielectric constant, it is possible to realize the semiconductor package 11 with high yield and high reliability, whereas the stiffener is designed to absorb a large amount of thermal stress concentrated on the interface with the substrate (Yamazaki, ¶[0050]).
Re Claim 5, (Original) Loo in view of Saeidi does not teach the semiconductor package according to claim 4, wherein the CTE of the substrate is greater than the CTE of the chip set.
In the same field of endeavor, Yamazaki teaches the semiconductor package according to claim 4, wherein the CTE of the substrate (Resin substrate; 41; Fig 1; Per ¶[0039] CTE is 13 - 16 ppm/C therebetween) is greater than the CTE of the chip set (Semiconductor element; 21; Fig 1; Per ¶[Abstract, 0008] semiconductor element has CTE of 5 ppm/C).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used CTE of the substrate to be greater than the CTE of the chip set, as taught by Yamazaki. One would have been motivated to do this with a reasonable expectation of success because the resin substrate can sufficiently withstand thermal stress caused by a difference in thermal expansion coefficient from the semiconductor element, and the entire wiring substrate is less likely to warp to the semiconductor element (chip) mounting surface side. (Yamazaki, ¶[0010]).
Re Claim 9, (Previously Presented) Loo and Seidi do not teach the semiconductor package according to claim 1, wherein the adhesive member is a single member, and contacts the first stiffener and the second stiffener.
Yamazaki teaches the semiconductor package according to claim 1, wherein the adhesive member (Adhesive; 34; Fig 1; ¶[0043]) is a single member, and the first stiffener and the second stiffener (Stiffeners; 31; Fig 1; Per ¶[0043]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a single member adhesive to contact all of the stiffeners, as taught by Yamazaki. One would have been motivated to do this with a reasonable expectation of success because making all of the stiffeners attached to an adhesive causes the bending stress to be applied elsewhere to a large area, such as the semiconductor element itself or a connection portion between the semiconductor element and the resin substrate (Yamazaki, ¶[0032]).
12. Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Loo, Kum-Weng et al. (Pub No. US 20110018125 A1) (hereinafter, Loo) in view of Saeidi, Seyed Mahdi et al. (Pub No. US 20140061893 A1) (hereinafter, Saeidi) as applied to claim 1, and further in view of Iyengar, Madhusudan K. et al. (Pub No. US 20210378106 A1) (hereinafter, Iyengar).
Re Claim 10, (Previously Presented) Loo in view of Saeidi does not teach the semiconductor package according to claim 1, wherein each of the first stiffener and the second stiffener comprises a core metal and a plated region at an outside of the core metal.
In the same field of endeavor, Iyengar teaches the semiconductor package according to claim 1, wherein each of the stiffeners (Stiffener; 130; Figs 1/3A; ¶[0137]) comprises a core metal (Metal with which it is formed; ¶[0137]) and a plated region (Plated (not shown); ¶[0137]) at an outside (Plated region promotes adhesion per ¶[0137] and therefore is on outside) of the core metal.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have made the stiffeners comprise a core metal and a plated region at an outside of the core metal, as taught by Iyengar. One would have been motivated to do this with a reasonable expectation of success in order use the core metal to have a higher conductivity than other components in the semiconductor package and use the plated region to promote adhesion. (Iyengar, ¶[0137]).
Re Claim 11, (Original) Loo in view of Saeidi does not teach the semiconductor package according to the semiconductor package according to wherein:
the core metal comprises Cu; and
the plated region comprises Ni.
Iyengar teaches the semiconductor package according to the semiconductor package according to wherein:
the core metal (Metal with which it is formed; ¶[0137]) comprises Cu (Copper; ¶[0137]); and the plated region (Plated (not shown); ¶[0137]) comprises Ni (Nickel; ¶[0137]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used copper as the core metal and nickel as material of the plated region, as taught by Iyengar. One would have been motivated to do this with a reasonable expectation of success in order use the copper as the core metal to promote thermal heat transfer and nickel as the plating for increased durability.
13. Claims 14, 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Saeidi, Seyed Mahdi et al. (Pub No. US 20140061893 A1) (hereinafter, Saeidi), and further in view of Im, Yun-Hyeok (Pub No. US 20030085475 A1) (hereinafter, Im).
Figure 13 – Semiconductor Package, Saeidi
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Re Claim 14, (Currently Amended) Saeidi teaches a semiconductor package comprising:
a substrate (308; Fig 13; Per ¶[0031]) comprising, at an upper surface (Upper surface; Fig 13) thereof, an inner area (Area surrounding die 304; Fig 13; See Fig 13 above labelled IA) and an edge area (Area from edge of die 304 to edge of heat spreader lid 302; Fig 13; See Fig 13 above labelled EA) surrounding the inner area;
a chip set (Die; 304; Fig 13; ¶[0030]) on the inner area of the substrate;
a stiffener set (Heat spreader lid/Stiffener; 302/1302; Fig 13; ¶[0067]) on the edge area of the substrate, the stiffener set comprising a first stiffener (Heat spreader lid; 302; Fig 13; ¶[0067]) and a second stiffener (Pair of Stiffeners; 1302; Fig 13; ¶[0067]) having different coefficients of thermal expansion (CTEs) (Per ¶¶0036,0073] CTE of Heat spreader lid 302 may be of Stainless Steel (10-17.3 ppm/C) and CTE of Stiffener 1302 may be Silicon Nitride (Less than 7.5 ppm/C)), respectively; and
an adhesive member (Second TIM/Adhesive; 1304/314; Fig 13; Per ¶[0070] Second TIM provides adhesion) attaching the first stiffener and the second stiffener to the substrate,
wherein the first stiffener comprises a pillar region (Peripheral pillars supports of 302; Fig 13) and a roof region (Roof of 302 which hangs over chip 304; Fig 13), the roof region protruding from an upper surface (Horizontal plane on location of corners of 302; Fig 13) of the pillar region and being above the second stiffener,
the second stiffener is horizontally spaced apart from the pillar region, and is closer to the inner area than the pillar region,
the roof region extends horizontally toward the inner area such that the roof region overlaps the second stiffener in a plan view (Per ¶[0035] Heat spreader lid 302 encloses die 304 from the top side and lateral sides (surfaces that are perpendicular to surface 310 of substrate 308)), and
an inner side surface of the roof region facing the inner area is horizontally spaced apart from a side surface (Sider surfaces of 304; Fig 13) of the chip set on the inner area.
a bottom surface (Bottom surface of 302) of the roof region is at a higher position (Bottom surface of 302 is higher than 304) than the chip set.
However, Saedi does not teach the second stiffener has a pillar-shaped cross-section that has a height greater than a width,
the roof region does not overlap the inner area in a plan view.
In the same field of endeavor, Im teaches the second stiffener (Supporter; 114; Fig 9; ¶ has a pillar-shaped cross-section (Pillar-shape of 114; Fig 9) that has a height greater than a width (Per Fig 9, the height is greater than the width).
the roof region (Lid; 108F; Fig 9; ¶[0053]) does not overlap the inner area (Between outer injection holes 116; Fig 9) in a plan view (Vertical view; Fig 12; Note: Due to the ring structure, lid 108F would not overlap the inner area where chip set 102 is located)
Im, Fig 9: Semiconductor package with stiffener set
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Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a second stiffener with a height greater than the width and the roof region does not overlap the inner area in a plan view as taught by Im for the semiconductor package as taught by Saeidi. One would have been motivated to do this with a reasonable expectation of success because a second stiffener with a greater height and a roof region not overlapping the chip set may be able to allow for more room for the thermal interface material (TIM) above the central chip, which in turn will allow for more surface area in which heat may be transferred away from the chip while powered, preventing the TIM from flowing down or melting onto the materials below, as suggested by Im (¶[0006]).
Re Claim 17, (Previously Presented) Saeidi teaches the semiconductor package according to claim 14, wherein the first stiffener and the second stiffener (Heat spreader lid/Stiffener; 302/1302; Fig 13; ¶[0067]) have different heights (Heat spreader lid 302 covers Stiffener 1302; Fig 13), respectively.
Re Claim 19, (Previously Presented) Saeidi teaches the semiconductor package according to claim 14, wherein the stiffener set (Heat spreader lid/Stiffener; 302/1302; Fig 13; ¶[0067]) and the chip set (Die; 304; Fig 13; ¶[0030]) are spaced apart (Spaced apart by second TIM 322; Fig 13) from one another.
14. Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Saeidi, Seyed Mahdi et al. (Pub No. US 20140061893 A1) (hereinafter, Saeidi) as applied to claim 14, and further in view of Yamazaki, Kozo et al. (Pub No. JP 2004311598 A) (hereinafter, Yamazaki).
Re Claim 15, (Previously Presented) Saeidi teaches the semiconductor package according to The semiconductor package according to claim 14, wherein a coefficient of thermal expansion (CTE) of each the first stiffener and the second stiffener (Heat spreader lid/Stiffener; 302/1302; Fig 13; Per ¶¶0036,0073] CTE of Heat spreader lid 302 may be of Stainless Steel (10-17.3 ppm/C) and CTE of Stiffener 1302 may be Silicon Nitride (Less than 7.5 ppm/C), and a CTE of the substrate (308; Fig 13; Per ¶[0031] may be electrically insulating layers such as ceramic, plastic, tape etc. or organic material such as BT (bismaleimide triazine) laminate/resin, a flexible tape material such as polyimide, a flame retardant fiberglass composite substrate board material) are different.
However, Saeidi does not teach the CTE of the chip set.
In the same field of endeavor, Yamazaki teaches CTE of the chip set (Semiconductor element; 21; Fig 1; Per ¶[Abstract, 0008] semiconductor element has CTE of 5 ppm/C and dielectric constant of 4 ppm/C and is therefore an insulating material).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a chip set with a CTE different from the stiffeners and substrate, as taught by Yamazaki. One would have been motivated to do this with a reasonable expectation of success because the resin substrate can sufficiently withstand thermal stress caused by a difference in thermal expansion coefficient from the chip, and the entire semiconductor package is less likely to warp toward the chip mounting surface, thus preventing the chip from warping (Yamazaki, ¶[0050]).
Re Claim 16, (Previously Presented) Saeidi teaches the semiconductor package according to the semiconductor package according to wherein:
wherein each of the CTE of the first stiffener and the second stiffener (Heat spreader lid/Stiffener; 302/1302; Fig 13; Per ¶¶0036,0073] CTE of Heat spreader lid 302 may be of Stainless Steel (10-17.3 ppm/C) and CTE of Stiffener 1302 may be Silicon Nitride (Less than 7.5 ppm/C) is greater than the CTE of the substrate (308; Fig 13; Per ¶[0031] may be electrically insulating layers such as ceramic, plastic, tape etc. or organic material such as BT (bismaleimide triazine) laminate/resin, a flexible tape material such as polyimide, a flame retardant fiberglass composite substrate board material); and
However, Saeidi does not teach wherein the CTE of each of the stiffeners is greater than both the CTE of the chip set.
In the same field of endeavor, Yamazaki wherein each of the CTE of the stiffeners (Stiffeners; 31; Fig 1; Per ¶[0041] plate-shaped member made of Invar (Fe-Ni alloy)) is greater that the CTE of the chip set (Semiconductor element; 21; Fig 1; Per ¶[Abstract, 0008] semiconductor element has CTE of 5 ppm/C).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used the first and second stiffeners with a CTE greater than that of the chip set, as taught by Yamazaki. One would have been motivated to do this with a reasonable expectation of success because using the LSI chip 21 having a low dielectric constant, it is possible to realize the semiconductor package 11 with high yield and high reliability, whereas the stiffener is designed to absorb a large amount of thermal stress concentrated on the interface with the substrate (Yamazaki, ¶[0050]).
15. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Saeidi, Seyed Mahdi et al. (Pub No. US 20140061893 A1) (hereinafter, Saeidi) in view of Lin, Tsung-Shu et al. (Pub No. US 20210366889 A1) (hereinafter, Lin), and further in view of Yamazaki, Kozo et al. (Pub No. JP 2004311598 A) (hereinafter, Yamazaki).
Re Claim 20, (Currently Amended) Saeidi teaches a semiconductor package comprising:
a substrate (308; Fig 13; Per ¶[0031]) comprising, at an upper surface (Upper surface; Fig 13) thereof, an inner area (Area surrounding die 304; Fig 13; See Fig 13 above labelled IA) and an edge area (Area from edge of die 304 to edge of heat spreader lid 302; Fig 13; See Fig 13 above labelled EA) surrounding the inner area;
a chip set (Die; 304; Fig 13; ¶[0030]) on the inner area of the substrate;
a stiffener set (Heat spreader lid/Stiffener; 302/1302; Fig 13; ¶[0067]) on the edge area of the substrate, the stiffener set comprising a first stiffener and a second stiffener (Heat spreader lid/Pair of Stiffeners; 302/1302; Fig 13; ¶[0067]) spaced apart from one another and having different coefficients of thermal expansion (CTEs) (Per ¶¶0036,0073] CTE of Heat spreader lid 302 may be CTE of Stainless Steel (10-17.3 ppm/C) and CTE of Stiffener 1302 may be Silicon Nitride (Less than 7.5 ppm/C)), respectively; and
an adhesive member (Second TIM/Adhesive; 1304/314; Fig 13; Per ¶[0070] Second TIM provides adhesion) attaching the first stiffener and the second stiffener to the substrate,
wherein a coefficient of thermal expansion (CTE) of each of the first stiffener and the second stiffener (Heat spreader lid/Stiffener; 302/1302; Fig 13; Per ¶¶0036,0073] CTE of Heat spreader lid 302 may be of Stainless Steel (10-17.3 ppm/C) and CTE of Stiffener 1302 may be Silicon Nitride (Less than 7.5 ppm/C)), and a CTE of the substrate (308; Fig 13; Per ¶[0031] may be electrically insulating layers such as ceramic, plastic, tape etc. or organic material such as BT (bismaleimide triazine) laminate/resin, a flexible tape material such as polyimide, a flame retardant fiberglass composite substrate board material) is different,
wherein the first stiffener comprises a pillar region (Peripheral pillars supports of 302; Fig 13) and a roof region (Roof of 302 which hangs over chip 304; Fig 13), the roof region protruding from an upper surface (Horizontal plane on location of corners of 302; Fig 13) of the pillar region and being above the second stiffener,
the second stiffener is horizontally spaced apart from the pillar region, and is closer to the inner area than the pillar region,
the roof region extends horizontally toward the inner area such that the roof region overlaps the second stiffener in a plan view (Per ¶[0035] Heat spreader lid 302 encloses die 304 from the top side and lateral sides (surfaces that are perpendicular to surface 310 of substrate 308)), and
and a lower surface (Lower surface of roof of 60; Fig 6) of the roof region is spaced apart (Vertically spaced apart by adhesive 1304; Fig 6) from an upper surface (Upper surface of 302; Fig 6) of the second stiffener such that a gap is defined between the lower surface of the roof region and the upper surface of the second stiffener.
a bottom surface (Bottom surface of 302) of the roof region is at a higher position (Bottom surface of 302 is higher than 304) than the chip set.
However, Saeidi does not teach the chip set comprising an interposer on the substrate and a logic chip and a memory stack on the interposer, and
the second stiffener has a pillar-shaped cross-section that has a height greater than a width.
and the CTE of the chip set.
the roof region does not overlap the inner area in a plan view.
Lin, Fig 12: Embodiment of package structure
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In the same field of endeavor, Lin teaches the second stiffener (Singulated structure; SS; Fig 12; ¶[0055]) has a pillar-shaped cross-section that has a height greater than a width (SS has a vertical height greater than horizontal width; Fig 12),
the chip set (Semiconductor dies; 120a/b; Fig 12; ¶[0013]) comprising an interposer (INT; Fig 12; ¶[0013]) on the substrate (Wiring substrate; 150; Fig 12; ¶[0021]) and a logic chip (Logic die; 120a; Fig 12; ¶[0013]) and a memory stack (High bandwidth memory cubes with stacked memory dies; 120b; Fig 12; ¶[0013]) on the interposer.
the roof region (Roof of SS above underfill UF2; Fig 12) does not overlap the inner area (Area where 120b/120a are located; Fig 12) in a plan view (Vertical view; Figs 16A/16B).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a chip set comprising an interposer on a substrate, a logic chip and memory stack, and the roof region does not overlap the inner area in a plan view, as taught by Lin. One would have been motivated to do this with a reasonable expectation of success to meet the demand for miniaturization, higher speed, greater bandwidth and lower power consumption. Furthermore, logic dies are often used together in order to have a high-speed processing capability that can only store and retrieve data (Lin, ¶¶[0001, 0013]).
Additionally, the roof region not overlapping the inner area would allow for more room for the thermal interface material (TIM) above the central chip, which in turn will allow for more surface area in which heat may be transferred away from the chip while powered, preventing the TIM from flowing down or melting onto the materials below, as suggested by Im (¶[0006]).
Lastly, the second stiffener with a greater height may be able to allow for more room for the thermal interface material (TIM) above the central chip, which in turn will allow for more surface area in which heat may be transferred away from the chip while powered, preventing the TIM from flowing down or melting onto the materials below.
However, Saeidi in view of Lin does not teach the CTE of the chip set.
In the same field of endeavor, Yamazaki teaches the CTE of the chip set (Semiconductor element; 21; Fig 1; Per ¶[Abstract, 0008] semiconductor element has CTE of 5 ppm/C and dielectric constant of 4 ppm/C and is therefore an insulating material).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a chip set with a CTE different from the stiffeners and substrate, as taught by Yamazaki. One would have been motivated to do this with a reasonable expectation of success because the resin substrate can sufficiently withstand thermal stress caused by a difference in thermal expansion coefficient from the chip, and the entire semiconductor package is less likely to warp toward the chip mounting surface, thus preventing the chip from warping (Yamazaki, ¶[0050]).
Conclusion
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/T.E.D./
Examiner
Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817