Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
A request for continued examination (RCE) under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action mailed on 10/03/2025 ("10-03-25 Final OA") has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/05/2026 ("01-05-26 Submission") has been entered when the RCE was filed on 01/05/2026.
In the 01-05-26 Submission, the Applicant substantively amended 1, 7, 9 and 10.
Currently, amended claims 1-20 are pending and are examined below.
Information Disclosure Statement
The information disclosure statement submitted on 02/02/2026 ("02-02-26 IDS") is in compliance with the provisions of 37 CFR 1.97. Accordingly, the 02-02-26 IDS is being considered by the examiner.
Response to Arguments
Applicant’s amendments to claim 9 have overcome the 35 U.S.C. 112(b) rejection of claims 9, 16 and 17 as being indefinite set forth starting on page 3 under line item number 1 of the 10-03-25 Final OA.
Despite the substantive amendments to the independent claims 1, 7 and 10, previously-cited Kobayashi reads on the independent claims 1, 7 and 10, infra. Thus, the 35 U.S.C. 102(a)(1) rejection of claims 1, 3, 5, 7, 9-11, 13-15 and 20 as being anticipated by Kobayashi set forth starting on page 4 under line item number 2 of the 10-03-25 Final OA has been maintained.
Despite the substantive amendments to the independent claims 1, 7 and 10, previously-cited Lin reads on the independent claims 1, 7 and 10, infra. Thus, the 35 U.S.C. 102(a)(2) rejection of claims 1, 2, 7, 8, 10-14, 18 and 20 as being anticipated by Lin set forth starting on page 9 under line item number 3 of the 10-03-25 Final OA has been maintained.
Despite the substantive amendments to the independent claims 1 and 10, previously-cited Kawabata reads on the independent claims 1 and 10, infra. Thus, the 35 U.S.C. 102(a)(1) rejection of claims 1, 4, 10 and 19 as being anticipated by Kawabata set forth starting on page 13 under line item number 4 of the 10-03-25 Final OA has been maintained.
At least the substantively-amended independent claims 1, 7 and 10 required further consideration and search. New grounds of rejection are provided below.
A. Prior-art rejections based on Kobayashi
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3, 5, 7, 9-11, 13-15 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kobayashi (previously-cited Pub. No. US 2017/0365545 A1 to Kobayashi et al.).
Fig. 3C and 4B of Kobayashi have annotated to support the rejection below:
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Regarding independent claim 1, Kobayashi teaches a substrate 20 (see Fig. 3C for example. See also Fig. 4B) comprising:
one or more interconnects 16 (para [0057] - "Therefore, a multilayered wiring structure 17, in which a wiring layer 16 having the lands and the wiring is buried in an insulating layer 15 includes a first insulating layer, a second insulating layer, and the third insulator layer, is formed."); and
an elastomer layer 14 (para [0040] - "The resin layer 14 is made of a sealing resin...") comprising at least one conductor 11 (para [0040] - "through electrodes 11"), wherein the at least one conductor 11 is configured to couple at least one of the one or more interconnects 16 of the substrate 20 to a circuit board 21 (para [0071] - "...the circuit board 20 in mounted on a printed circuit board 21."), the at least one conductor 11 being formed by filling one or more holes H that pass through an elastomer body 14 from one of the interconnects 16 to a surface S of the elastomer layer 14 (A limitation of “formed by filling” does not structurally distinguish the claimed substrate over the substrate taught by Kobayashi, because it is directed to a process of how a substrate is made.” Kobayashi teaches the through electrodes 11 that is embedded in the resin layer 14 and taking up space or hole 11 in the resin layer 14.), the elastomer layer 14 comprising a compliant elastomer body 14 molded to surround the at least one conductor 11.
A limitation of “the compliant elastomer body comprising a predictable shape to provide predictable signal integrity performance at the substrate to an interface of the circuit board” does not structurally distinguish the claimed substrate over the substrate taught by Kobayashi, because it is directed to an intended use of the compliant elastomer body 14.
Regarding claim 3, Kobayashi teaches the elastomer layer 14 that further comprises a non-conductive elastomer body 14 (The resin layer 14 is inherently electrically insulating because it harbors electrically conductive through electrodes 11.), and wherein the at least one conductor 11 of the elastomer layer 14 is contained within the non-conductive elastomer body 14.
Regarding claim 5, Kobayashi teaches the elastomer layer 14 that is at least one pin comprising the at least one conductor 11.
Regarding independent claim 7, Kobayashi teaches a semiconductor package (see Fig. 4B; see also Fig. 3C) comprising:
a first die 25 (para [0075] - "semiconductor chips 25");
a substrate 20 coupled to the first die 25, the substrate comprising one or more interconnects 16 (para [0057] - "Therefore, a multilayered wiring structure 17, in which a wiring layer 16 having the lands and the wiring is buried in an insulating layer 15 includes a first insulating layer, a second insulating layer, and the third insulator layer, is formed.") and an elastomer layer 14 (para [0040] - "The resin layer 14 is made of a sealing resin...") comprising at least one conductor 11 (para [0040] - "through electrodes 11"), wherein the at least one conductor 11 is configured to couple at least one of the one or more interconnects 16 of the substrate 20 to a circuit board 21 (para [0071] - "...the circuit board 20 in mounted on a printed circuit board 21."), the at least one conductor 11 being formed by filling one or more holes H that pass through an elastomer body 14 from one of the interconnects 16 to a surface S of the elastomer layer 14 (A limitation of “formed by filling” does not structurally distinguish the claimed substrate over the substrate taught by Kobayashi, because it is directed to a process of how a substrate is made.” Kobayashi teaches the through electrodes 11 that is embedded in the resin layer 14 and taking up space or hole 11 in the resin layer 14.), the elastomer layer 14 comprising a compliant elastomer body 14 molded to surround the at least one conductor 11.
A limitation of “the compliant elastomer body comprising a predictable shape to provide predictable signal integrity performance at the substrate to an interface of the circuit board” does not structurally distinguish the claimed substrate over the substrate taught by Kobayashi, because it is directed to an intended use of the compliant elastomer body 14.
Regarding claim 9, Kobayashi teaches the elastomer layer 14 that comprises at least one pin comprising the at least one conductor 11.
Regarding independent claim 10, Kobayashi teaches a method comprising:
forming a substrate 20 comprising (i) one or more interconnects 16 (para [0057] - "Therefore, a multilayered wiring structure 17, in which a wiring layer 16 having the lands and the wiring is buried in an insulating layer 15 includes a first insulating layer, a second insulating layer, and the third insulator layer, is formed.") and (ii) an elastomer layer 14 (para [0040] - "The resin layer 14 is made of a sealing resin..."), the elastomer layer comprising at least one conductor 11 (para [0040] - "through electrodes 11"), wherein the elastomer layer 14 is formed to couple at least one of the one or more interconnects 16 of the substrate 20 to a circuit board 21 (para [0071] - "...the circuit board 20 in mounted on a printed circuit board 21.") via the at least one conductor 11, the at least one conductor 11 being formed by filling one or more holes H that pass through an elastomer body 14 from one of the interconnects 16 to a surface S of the elastomer layer 14 (A limitation of “formed by filling” does not structurally distinguish the claimed substrate over the substrate taught by Kobayashi, because it is directed to a process of how a substrate is made.” Kobayashi teaches the through electrodes 11 that is embedded in the resin layer 14 and taking up space or hole 11 in the resin layer 14.), the elastomer layer 14 comprising a compliant elastomer body 14 molded to surround the at least one conductor 11, the elastomer layer 14 comprising a compliant elastomer body 14 molded to surround the at least one conductor 11.
A limitation of “the compliant elastomer body comprising a predictable shape to provide predictable signal integrity performance at the substrate to an interface of the circuit board” does not structurally distinguish the claimed substrate over the substrate taught by Kobayashi, because it is directed to an intended use of the compliant elastomer body 14.
Regarding claim 11, Kobayashi teaches the circuit board 21 that comprises one or more solid pad connections 22 (para [0072] - "bumps 22").
Regarding claim 13, Kobayashi teaches the elastomer layer 14 that further comprises a non-conductive elastomer body 14 (The resin layer 14 is inherently electrically insulating because it harbors electrically conductive through electrodes 11.), and wherein the at least one conductor 11 of the elastomer layer 14 is contained within the non-conductive elastomer body 14.
Regarding claim 14, Kobayashi teaches the at least one conductor 11 of the elastomer layer 14 at least partially extends from the non-conductive elastomer body 14 to couple to the circuit board.
Regarding claim 15, Kobayashi teaches the elastomer layer 14 that is the at least one conductor 11.
Regarding claim 20, Kobayashi teaches the elastomer layer 14 that is formed on a surface of one or more first layers 15 (para [0057] - "an insulating layer 15 that includes a first insulating layer, a second insulating layer, and the third insulating layer, is formed.") of the substrate 20 as a body extending along an axis parallel to a plane defined by the surface of the one or more first layers 15 of the substrate 20.
B. Prior-art rejections based on Lin
Claim Rejections - 35 USC § 102
Claims 1, 2, 7, 8, 10-14, 18 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lin (previously-cited Pub. No. US 2023/0067349 A1 to Lin et al.).
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Regarding independent claim 1, Lin teaches a substrate (see Fig. 12) comprising:
one or more interconnects 125 (para [0018] - "TIVs 125"); and
an elastomer layer 124 (para [0011] - "a redistribution layer (RDL) structure 110 (not fully illustrated in FIG. 1 but fully illustrated below with respect to FIG. 4) may be formed on the carrier 102…one or more dielectric layers 124"; para [0012] - "In some embodiments, the dielectric layer 104 is formed of a photo-sensitive material...polyimide (PI)...") comprising at least one conductor 126 (para [0011] - "one or more metallization patterns 126"), wherein the at least one conductor 126 is configured to couple at least one of the one or more interconnects 125 of the substrate to a circuit board 190 (para [0054] - "The package substrate 190"), the at least one conductor 126 being formed by filling one or more holes (volume occupied by one or more metallization patterns 126 in the one or more dielectric layers 124) that pass through an elastomer body 124 from one of the interconnects 125 to a surface of the elastomer layer 124 (A limitation of “formed by filling” does not structurally distinguish the claimed substrate over the substrate taught by Lin, because it is directed to a process of how a substrate is made.” Lin teaches the one or more metallization patterns 126 that is embedded in the resin layer 124 and taking up space or hole in the resin layer 124.), the elastomer layer 124 comprising a compliant elastomer body 124 molded to surround the at least one conductor 126.
A limitation of “the compliant elastomer body comprising a predictable shape to provide predictable signal integrity performance at the substrate to an interface of the circuit board” does not structurally distinguish the claimed substrate over the substrate taught by Lin, because it is directed to an intended use of the compliant elastomer body 124.
Regarding claim 2, Lin teaches the one or more interconnects 126 at least partially extend into the elastomer layer 124 to form or to couple to the at least one conductor 126 of the elastomer layer 124.
Regarding independent claim 7, Lin teaches a semiconductor package (see Fig. 12) comprising:
a first die 210 (para [0032] - "dies 210"); and
a substrate T1, T2 (para [0056]) coupled to the first die 210, the substrate comprising one or more interconnects 125 (para [0018] - "TIVs 125") and an elastomer layer 124 (para [0011] - "a redistribution layer (RDL) structure 110 (not fully illustrated in FIG. 1 but fully illustrated below with respect to FIG. 4) may be formed on the carrier 102…one or more dielectric layers 124"; para [0012] - "In some embodiments, the dielectric layer 104 is formed of a photo-sensitive material...polyimide (PI)...") comprising at least one conductor 126 (para [0011] - "one or more metallization patterns 126"), wherein the at least one conductor 126 is configured to couple at least one of the one or more interconnects 126 of the substrate to a circuit board 190, the at least one conductor 126 being formed by filling one or more holes (volume occupied by one or more metallization patterns 126 in the one or more dielectric layers 124) that pass through an elastomer body 124 from one of the interconnects 125 to a surface of the elastomer layer 124 (A limitation of “formed by filling” does not structurally distinguish the claimed substrate over the substrate taught by Lin, because it is directed to a process of how a substrate is made.” Lin teaches the one or more metallization patterns 126 that is embedded in the resin layer 124 and taking up space or hole in the resin layer 124.), the elastomer layer 124 comprising a compliant elastomer body 124 molded to surround the at least one conductor 126.
A limitation of “the compliant elastomer body comprising a predictable shape to provide predictable signal integrity performance at the substrate to an interface of the circuit board” does not structurally distinguish the claimed substrate over the substrate taught by Lin, because it is directed to an intended use of the compliant elastomer body 124.
Regarding claim 8, Lin teaches the one or more interconnects 126 at least partially extend into the elastomer layer 124 to form or to couple to the at least one conductor 126 of the elastomer layer 124.
Regarding independent claim 10, Lin teaches a method comprising:
forming a substrate T1, T2 comprising (i) one or more interconnects 125 (para [0018] - "TIVs 125"); and (ii) an elastomer layer 124 (para [0011] - "a redistribution layer (RDL) structure 110 (not fully illustrated in FIG. 1 but fully illustrated below with respect to FIG. 4) may be formed on the carrier 102…one or more dielectric layers 124"; para [0012] - "In some embodiments, the dielectric layer 104 is formed of a photo-sensitive material...polyimide (PI)..."), the elastomer layer comprising at least one conductor 126 (para [0011] - "one or more metallization patterns 126"), wherein the elastomer layer 124 is formed to couple at least one of the one or more interconnects 126 of the substrate T1, T2 to a circuit board 190 via the at least one conductor 126, the at least one conductor 126 being formed by filling one or more holes (volume occupied by one or more metallization patterns 126 in the one or more dielectric layers 124) that pass through an elastomer body 124 from one of the interconnects 125 to a surface of the elastomer layer 124 (A limitation of “formed by filling” does not structurally distinguish the claimed substrate over the substrate taught by Lin, because it is directed to a process of how a substrate is made.” Lin teaches the one or more metallization patterns 126 that is embedded in the resin layer 124 and taking up space or hole in the resin layer 124.), the elastomer layer 124 comprising a compliant elastomer body 124 molded to surround the at least one conductor 126.
A limitation of “the compliant elastomer body comprising a predictable shape to provide predictable signal integrity performance at the substrate to an interface of the circuit board” does not structurally distinguish the claimed substrate over the substrate taught by Lin, because it is directed to an intended use of the compliant elastomer body 124.
Regarding claim 11, Lin teaches the one or more interconnects 125 that comprise one or more solid pad connections 152 (para [0034] - "a plurality of bonding pads 152.").
Regarding claim 12, Lin teaches the one or more interconnects 125 at least partially extend into the elastomer layer 124 to form or to couple to the at least one conductor 126 of the elastomer layer 124, and wherein the elastomer layer 124 is formed on the one or more interconnects 125 to surround the one or more interconnects at least partially extending into elastomer layer 124.
Regarding claim 13, Lin teaches the at least one conductor 126 of the elastomer layer 124 at least partially extends form the non-conductive elastomer body 104 to coupled to the circuit board 190.
Regarding claim 14, Lin teaches the at least one conductor 126 of the elastomer layer 124 at least partially extends from the non-conductive elastomer body 104 to couple to the circuit board 190.
Regarding claim 18, Lin teaches the elastomer layer 124 that comprises a non-conductive elastomer body 104, and wherein the method further comprises:
coating at least a part of an outer surface of the non-conductive elastomer body 104 with the at least one conductor 170.
Regarding claim 20, Lin teaches the elastomer layer 124 that is formed on a surface of one or more first layers of the substrate T1, T2 as a body extending along an axis parallel to a plane defined by the surface of the one or more first layers of the substrate T1, T2.
C. Prior-art rejections based on Kawabata
Claim Rejections - 35 USC § 102
Claims 1, 4, 10 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kawabata (previously-cited Pub. No. US 2017/0311448 A1 to Kawabata).
Fig. 1 of Kawabata has been provided to support the rejections below:
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Regarding independent claim 1, Kawabata teaches a substrate comprising:
one or more interconnect 23 (para [0035] - "land patterns 23"); and
an elastomer layer 20 (para [0034] - "The substrate 20...may be any type of substrate including: a thermosetting resin based organic substrate...") comprising at least one conductor 25 or 25, 26 ((para [0035] - “internal wirings 25…external terminals 26”), wherein the at least one conductor 25 or 25, 26 is configured to couple at least one of the one or more interconnects 23 of the substrate to a circuit board (para [0035] - "Upon actual use, the electronic circuit package 11A is mounted on an unillustrated mother board, and land patterns on the mother board and the external terminals 26 of the electronic circuit package 11A are electrically connected."), the at least one conductor 25 being formed by filling holes (volumes occupied internal wirings 25 in the substrate 20) that pass through an elastomer body 20 from one of the interconnects 23 to a (bottom) surface of the elastomer layer 20 (A limitation of “formed by filling” does not structurally distinguish the claimed substrate over the substrate taught by Kawabata, because it is directed to a process of how a substrate is made.” Kawabata teaches the internal wirings 25 that are embedded in the substrate 20 and taking up space or hole in the substrate 20.), the elastomer layer 20 comprising a compliant elastomer body 20 molded to surround the at least one conductor 25 or 25, 26.
A limitation of “the compliant elastomer body comprising a predictable shape to provide predictable signal integrity performance at the substrate to an interface of the circuit board” does not structurally distinguish the claimed substrate over the substrate taught by Kawabata, because it is directed to an intended use of the compliant elastomer body 20.
Regarding claim 4, Kawabata teaches a non-conductive elastomer body 20, and wherein the at least one conductor 25 or 25, 26 of the elastomer layer 20 partially surrounds an outer surface of the non-conductive elastomer body 20.
Regarding independent claim 10, Kawabata teaches a method comprising:
forming a substrate comprising (i) one or more interconnects 23 (para [0035] - "land patterns 23") and (ii) an elastomer layer 20 (para [0034] - "The substrate 20...may be any type of substrate including: a thermosetting resin based organic substrate..."), the elastomer layer 20 comprising at least one conductor 25 or 25, 26 ((para [0035] - “internal wirings 25…external terminals 26”), wherein the elastomer layer 20 is formed to couple at least one of the one or more interconnects 23 of the substrate to a circuit board via the at least one conductor 25 or 26 (para [0035] - "Upon actual use, the electronic circuit package 11A is mounted on an unillustrated mother board, and land patterns on the mother board and the external terminals 26 of the electronic circuit package 11A are electrically connected."), the at least one conductor 25 or 25, 26 being formed by filling holes (volumes occupied internal wirings 25 in the substrate 20) that pass through an elastomer body 20 from one of the interconnects 23 to a (bottom) surface of the elastomer layer 20 (A limitation of “formed by filling” does not structurally distinguish the claimed substrate over the substrate taught by Kawabata, because it is directed to a process of how a substrate is made.” Kawabata teaches the internal wirings 25 that are embedded in the substrate 20 and taking up space or hole in the substrate 20.), the elastomer layer 20 comprising a compliant elastomer body 20 molded to surround the at least one conductor 25 or 25, 26.
A limitation of “the compliant elastomer body comprising a predictable shape to provide predictable signal integrity performance at the substrate to an interface of the circuit board” does not structurally distinguish the claimed substrate over the substrate taught by Kawabata, because it is directed to an intended use of the compliant elastomer body 20.
Regarding claim 19, wherein the elastomer layer 20 comprises a non-conductive elastomer body 20, and wherein the method further comprises:
coating the at least one of the one or more interconnects 23 with a conductive material 24 (para [0034] - "solder 24");
coating at least part of an outer surface of the non-conductive elastomer body 20 with the at least one conductor 25, 26; and
forming the elastomer layer 20 on the at least one of the one or more interconnects 23 by coupling the at least one conductor 25, 26 of the elastomer layer 20 to the at least one of the one or more interconnects 23 coated with the conductive material 24.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached 8:30 A.M. to 7 P.M.
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/MICHAEL JUNG/Primary Examiner, Art Unit 2895 06 February 2026