DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention of Group I, Claims 1-10 and 19-20, in the reply filed on 10/10/2025 is acknowledged.
Claims 11-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/10/2025.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jo et al. (US 2015/0162265).
Regarding claim 1, Jo et al. discloses, as shown in Figures 1-16, 25 and 33, a semiconductor device comprising:
a composite structure (1000,1000a-1000n) comprising:
a first semiconductor device (100, 100-1), the first semiconductor device having a top surface, a bottom surface, side surfaces extending between the top surface and the bottom surface, and one or more first interface components (132) extending at least from one or more portions of the top surface, wherein edges between the top surface and the side surfaces define a first lateral perimeter, the first lateral perimeter defining a first area; and
a second semiconductor device (200, 100-2), the second semiconductor device having a top surface, a bottom surface, side surfaces extending between the top surface and the bottom surface, and one or more second interface components (240) extending at least from one or more portions of the bottom surface, wherein edges between the bottom surface and the side surfaces define a second lateral perimeter, the second lateral perimeter defining a second area, the second area being different in size than the first area, the first and second semiconductor devices forming a stacked configuration with the second semiconductor device being disposed on or over the first semiconductor device and with each of the one or more first interface components bonded with a corresponding one of the one or more second interface components; and
a sealant material (500) that is disposed along one or more surface portions of the composite structure to cover a region comprising at least portions of side surfaces of the composite structure that extend from below the top surface of the first semiconductor device to above the bottom surface of the second semiconductor device.
Regarding claim 2, Jo et al. discloses the composite structure is formed on a semiconductor wafer among a plurality of composite structures that is formed in an array on the semiconductor wafer, wherein the side surfaces of the composite structure have surface features after separation from each of one or more adjacent composite structures among the plurality of composite structures that are formed on the semiconductor wafer (Figure 22).
It is noted that the term “after separation from each of one or more adjacent composite structures among the plurality of composite structures that are formed on the semiconductor wafer” is method recitation in a device claimed. “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).
Regarding claim 3, Jo et al. discloses the surface features comprise at least one of one or more cracks, one or more signs of chipping, one or more grooves, or one or more portions characteristic of delamination of the second semiconductor device from the first semiconductor device, wherein the sealant material fills in and seals the at least one of the one or more cracks, the one or more signs of chipping, the one or more grooves, or the one or more portions characteristic of delamination ([0110],[0200],etc.)
Regarding claim 4, Jo et al. discloses the sealant material comprises at least one of adhesive, thermoset resin, thermal conductive adhesive, mold compound, epoxy, or silicon dioxide-based material ([0111]).
Regarding claim 5, Jo et al. discloses the composite structure further comprises a mold region (400, 400a-400d,400-1 or 400-2) that fills in a region, other than a space occupied by the smaller of the first semiconductor device or the second semiconductor device, the region being either:
(i) above the first area that extends from the top surface of the first semiconductor device to the top surface of the second semiconductor device and that extends from an interior edge of the first lateral perimeter to other interior edges of the first lateral perimeter when the second area is smaller than the first area; or
(ii) below the second area that extends from the bottom surface of the first semiconductor device to the bottom surface of the second semiconductor device and that extends from an interior edge of the second lateral perimeter to other interior edges of the second lateral perimeter when the second area is larger than the first area. (Figures 1-16, 25 and 33).
Regarding claim 6, Jo et al. discloses the mold region comprises a first material comprising at least one of adhesive, thermoset resin, thermal conductive adhesive, mold compound, epoxy, silicon dioxide-based material, or a dielectric material ([0098]).
Regarding claim 10, Jo et al. discloses wherein:
the second area is smaller than the first area (Figures 1-16, 25 and 33, [0133]);
the first semiconductor device further comprises a plurality of protruding electrical contact terminals (140,140-1) extending at least from one or more portions of the bottom surface of the first semiconductor device;
a top surface of the composite structure is defined by at least one of the top surface of the second semiconductor device (200) or a top surface of the mold region;
the side surfaces of the composite structure are defined by one of:
the side surfaces of the first semiconductor device (100, 100a, 100-1) and side surfaces of the mold region (400,400a-400d,400-1 or 400-2); or
the side surfaces of the first semiconductor device, one or more of the side surfaces of the mold region, and one or more of the side surfaces of the second semiconductor device; and
the region of the composite structure that is covered by the sealant material (500) comprises one of:
the side surfaces of the composite structure (1000,1000a-1000n);
a combination of the top surface of the composite structure and the side surfaces of the composite structure (1000,1000a-1000n);
a combination of the bottom surface of the first semiconductor device (100, 100a, 100-1), portions of pillar portions of each of the plurality of protruding electrical contact terminals (140,140-1), and the side surfaces of the composite structure (1000,1000a-1000n);
a combination of the top surface of the composite structure, the bottom surface of the first semiconductor device, the portions of pillar portions of each of the plurality of protruding electrical contact terminals, and the side surfaces of the composite structure;
portions of each side surface of the composite structure extending from the top surface of the second semiconductor device to a portion below the top surface of the first semiconductor device but not to the bottom surface of the first semiconductor device; or
a combination of the top surface of the composite structure and the portions of each side surface of the composite structure extending from the top surface of the second semiconductor device to a portion below the top surface of the first semiconductor device but not to the bottom surface of the first semiconductor device (Figures 1-16, 25 and 33).
Allowable Subject Matter
Claims 7-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 19-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Applicant' s claims 7-9 and 19-20 are allowable over the references of record because none of these references disclose or can be combined to yield the claimed semiconductor device comprising the composite structure further comprises at least one dummy die that is disposed within and replaces at least one portion of the mold region, as recited in claim 7; none of these references disclose or can be combined to yield the claimed semiconductor device comprising at least one dummy die that is smaller than the first semiconductor device and that is disposed on or over and bonded to the first semiconductor device, a mold region that fills in a first region, other than a space occupied by the second semiconductor device and each of the at least one dummy die, that extends from a top surface of the first semiconductor device to a top surface of the second semiconductor device or a top surface of the at least one dummy die and that extends from an interior edge of a lateral perimeter of the first semiconductor device to other interior edges of the lateral perimeter of the first semiconductor device, and a sealant material that is disposed along one or more surface portions of the composite structure to cover a second region comprising at least portions of side surfaces of the composite structure that extend from below the top surface of the first semiconductor device to above a bottom surface of the second semiconductor device, in combination with the remaining claimed limitations of claim 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNG K VU whose telephone number is (571)272-1666. The examiner can normally be reached Monday - Friday: 7am - 5pm.
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/HUNG K VU/ Primary Examiner, Art Unit 2897
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