DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 12/05/2025 have been fully considered but they are either not persuasive or moot in view of the new grounds of rejection as necessitated by Applicant’s claim amendments as detailed below. Applicant argues on page 10 with respect to the obviousness rejection over “Jhothiraman” (U.S. 2021/0134736) in view of “Nagashima” (U.S. 10,002,880) that Jhorhiraman’s contact 240 is electrically connected to one of the conductive structures 206 as indicated by the arrow 240 and therefore fails to teach the contact structure electrically separated from the conductive materials as required by the amended claims. Applicant’s analysis is partially correct in that the reference number 240 identifies multiple different contacts including a word line contact 244 that forms a landed-on to one of the steps 220 (¶ [0052]) and is not electrically separated from the conductive materials 206. However, Jhothiraman teaches additional contacts 240 including source/drain contacts 248 that may be formed to land in contact with the source/drain regions of transistors (e.g., string driver transistors) within the base material (¶ [0053]) and are separate from the conductive materials 206 as pictured which satisfies the amended language.
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Therefore, the obviousness rejection over Jhothiraman in view of Nagashima is updated in view of the amended claims and maintained as detailed below. Applicant argues on page 11 that Jhothiraman and Nagashima teaches devices and structures that are not analogous which is not persuasive as both are directed to contacts within and proximate staircase regions of vertical memory devices and Applicant has not given sufficient detail as to how the structures are non-analogous.
Although not currently claimed, structural distinctions exist between Applicant’s disclosure and the teachings of Jhothiraman including, for example, Applicant’s FIG. 3G shows the liner (333L) at a slanted angle relative to the substrate at the contact structure (344) together with the contact structure does not extend through the tiers. That is, the contact (248) of Jhothiraman which does not extend through the staircase (234 or 236) contacts the liner (238) on planar upper surface of the surface of base (210) rather a slanted angle as Applicant teaches. See also citation of pertinent art in Conclusion section.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1,2,4-7 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2015/0255385 A1 to Lee et al., “Lee”, in view of U.S. Patent Application Publication Number 2021/0134736 A1 to Jhothiraman et al., “Jhothiraman”.
Regarding claim 1, Lee discloses an apparatus (e.g. FIG. 2F) comprising:
tiers (25/22a) located one over another, the tiers including conductive materials (25, ¶ [0050]) that form part of respective control gates for memory cells of the apparatus;
a staircase structure (as pictured) formed in the tiers, the conductive materials (25) including respective portions that collectively form a part of the staircase structure, the staircase structure including a sidewall (left side) on a side of the staircase structure;
a dielectric liner (23, ¶ [0046]) formed on the sidewall;
recesses (from FIG. 2C undercuts UC1, ¶ [0045]) formed in respective tiers and adjacent the sidewall such that respective portions of the dielectric liner (23) are located in the recesses (¶ [0046]).
Although Lee discloses a contact structure (26 on far left, ¶ [0051]) extending through a portion of the dielectric liner, wherein the portions of the dielectric liner (23) are (laterally) between the contact structure (26 on far left) and the conductive materials (25), Lee fails to clearly teach wherein the contact structure is electrically separated from the conductive materials.
Jhothiraman teaches (FIG. 2) contact structures (240) including a contact structure (e.g. 248) which extends through a portion of a dielectric liner (FIG. 2 liner 238, ¶ [0049], from FIG. 5 liner 504, ¶ [0062]-[0064]) and is electrically separated from conductive materials (206).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the apparatus of Lee by including source/drain contact structures as taught by Jhothiraman in order to perform the required writing, reading, and erasing operations (Jhothiraman ¶ [0004]).
Regarding claim 2, Lee in view of Jhothiraman yields the apparatus of claim 1, and Lee further discloses wherein the portions of the dielectric liner (23) include silicon dioxide (¶ [0046]).
Regarding claim 4, Lee in view of Jhothiraman yields the apparatus of claim 1, and Jhothiraman further teaches (FIG. 2) a conductive contact (244) adjacent the contact structure (248) and contacting one of the conductive materials (206), wherein the conductive contact (244) and the contact structure (248) have different lengths (as pictured).
Regarding claim 5, Lee in view of Jhothiraman yields the apparatus of claim 1, and Jhothiraman further teaches wherein the contact structure (248) includes a conductive core (248) and a dielectric liner (contact liner 242 surrounding 248, ¶ [0073]) adjacent the conductive core, wherein the conductive core (248) and the dielectric liner (242 surrounding 248) of the contact structure extend through the portion of the dielectric liner (238, as pictured at bottom of 248).
Regarding claim 6, Lee in view of Jhothiraman yields the apparatus of claim 5, and Jhothiraman as applied to Lee further yields wherein the dielectric liner (Jhothiraman 244 surrounding 248) of the contact structure has a same material (e.g. Jhothiraman teaches a dielectric oxide ¶ [0051]) as the portions of the dielectric liner in the recesses (Lee teaches 23 may include an oxide material ¶ [0046]).
Regarding claim 7, Lee in view of Jhothiraman yields the apparatus of claim 1, and Jhothiraman further teaches wherein the apparatus comprises a memory device (¶ [0001]-[0005],[0011],[0015],[0041]), the memory device including circuitry located under the tiers (¶ [0053] “source/drain regions of transistors (e.g., string driver transistors) within the base material 210”) , and the contact structure (248) is coupled to the circuitry (¶ [0053]).
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Number 10,002,880 B1 to Nagashima, “Nagashima”, in view of U.S. Patent Application Publication Number 2021/0134736 A1 to Jhothiraman et al., “Jhothiraman”.
Regarding claim 1, Nagashima discloses an apparatus (FIG. 25 as applied to the overall memory structure of e.g. FIG. 4 stacked portion 2) comprising:
tiers located one over another, the tiers including conductive materials (70, column 2 line 65 to column 3 line 4) that form part of respective control gates for memory cells of the apparatus;
a staircase structure (left side) formed in the tiers, the conductive materials (70) including respective portions that collectively form a part of the staircase structure, the staircase structure including a sidewall on a side of the staircase structure;
a dielectric liner (80, column 5 lines 34-40) formed on the sidewall;
recesses (from FIG. 17A recesses 90, column 9 lines 32-41) formed in respective tiers and adjacent the sidewall such that respective portions of the dielectric liner are located in the recesses.
Although Nagashima teaches a contact structure (cc on left, column 6 lines 51-65) extending through a portion of the dielectric liner, wherein the portions of the dielectric liner are (laterally) between the contact structure (left side cc) and the conductive materials (70), Nagashima fails to clearly teach wherein the contact structure is electrically separated from the conductive materials.
Jhothiraman teaches (FIG. 2) contact structures (240) including a contact structure (e.g. 248) which extends through a portion of a dielectric liner (FIG. 2 liner 238, ¶ [0049], from FIG. 5 liner 504, ¶ [0062]-[0064]) and is electrically separated from conductive materials (206).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the apparatus of Nagashima by including source/drain contact structures as taught by Jhothiraman in order to perform the required writing, reading, and erasing operations (Jhothiraman ¶ [0004]) and connecting with external circuits in the substrate (Nagashima column 6 lines 61-63).
Regarding claim 2, Nagashima in view of Jhothiraman yields the apparatus of claim 1, and Nagashima further discloses wherein the portions of the dielectric liner include silicon dioxide (81, column 9 lines 46-47).
Regarding claim 3, Nagashima in view of Jhothiraman yields the apparatus of claim 1, and Nagashima further discloses wherein the dielectric liner includes: silicon dioxide (81, column 9 lines 46-47), and the portions of the dielectric liner are part of the silicon dioxide; and silicon nitride (82, column 9 lines 47-48) adjacent the silicon dioxide, and the contact structure extending through the silicon nitride (82) and the silicon dioxide (81).
Regarding claim 4, Nagashima in view of Jhothiraman yields the apparatus of claim 1, and Nagashima further discloses a conductive contact (cc on far left, similar to Jhothiraman’s contact 244) adjacent the contact structure (when applying teachings of Jhothiraman) and contacting one of the conductive materials (70), wherein the conductive contact and the contact structure have different lengths (as pictured in Jhothiraman).
Regarding claim 5, Nagashima in view of Jhothiraman yields the apparatus of claim 1, and Jhothiraman further teaches wherein the contact structure (248) includes a conductive core (248) and a dielectric liner (contact liner 242 surrounding 248, ¶ [0073]) adjacent the conductive core, wherein the conductive core (248) and the dielectric liner (242 surrounding 248) of the contact structure extend through the portion of the dielectric liner (238, as pictured at bottom of 248).
Regarding claim 6, Nagashima in view of Jhothiraman yields the apparatus of claim 5, and Jhothiraman as applied to Nagashima further yields wherein the dielectric liner (Jhothiraman 244 surrounding 248) of the contact structure has a same material (e.g. Jhothiraman teaches a dielectric oxide ¶ [0051]) wherein the dielectric liner of the contact structure has a same material as the portions of the dielectric liner in the recesses (Nagashima teaches wherein liner 80 in the recesses comprises 81 which is silicon oxide, column 5 lines 51-52).
Regarding claim 7, Nagashima in view of Jhothiraman yields the apparatus of claim 1, and Jhothiraman further teaches wherein the apparatus comprises a memory device (¶ [0001]-[0005],[0011],[0015],[0041]), the memory device including circuitry located under the tiers (¶ [0053] “source/drain regions of transistors (e.g., string driver transistors) within the base material 210”) , and the contact structure (248) is coupled to the circuitry (¶ [0053]).
Claims 8-14 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2021/0134736 A1 to Jhothiraman et al., “Jhothiraman”, in view of U.S. Patent Number 10,002,880 B1 to Nagashima, “Nagashima”.
Regarding claim 8, Jhothiraman discloses an apparatus (e.g. FIG. 2) comprising:
tiers (212,214, ¶ [0043]) located one over another, the tiers including conductive materials (206, ¶ [0042]);
a staircase structure (from FIG. 4 staircase 404, ¶ [0061]) formed in the tiers, the conductive materials including respective portions that collectively form a part of the staircase structure, the staircase structure including a first sidewall (e.g. left side of opening 402) on a first side of the staircase, and a second sidewall (e.g. right side of opening 402) on a second side opposite the first side of the staircase;
a first dielectric liner (portion of FIG. 2 liner 238 on left, ¶ [0049], from FIG. 5 liner 504, ¶ [0062]-[0064]) formed on the first sidewall;
a second dielectric liner (portion of FIG. 2 liner 238 on right, ¶ [0049], from FIG. 5 liner 504, ¶ [0062]-[0064]) formed on the second sidewall;
a first contact structure (e.g. FIG. 2 contact 248 near 228, see Examiner-annotated figure below, ¶ [0053]) extending through a portion of the first dielectric liner (238/504), wherein the portions of the first dielectric liner are between the first contact structure (248) and a first portion of the conductive materials (206); and
a second contact structure (e.g. 238 towards the right, see Examiner-annotated figure below, ¶ [0053]) extending through a portion of the second dielectric liner, wherein the portions of the second dielectric liner (238/504) are between the second contact structure (248 toward right, see Examiner-annotated figure below) and a second portion of the conductive materials (uppermost 206 on right).
Jhothiraman fails to clearly teach first recesses formed in respective tiers and adjacent the first sidewall such that respective portions of the first dielectric liner are located in the first recesses, and second recesses formed in respective tiers and adjacent the second sidewall such that respective portions of the second dielectric liner are located in the second recesses;
Nagashima teaches (FIG. 25 as applied to the overall memory structure of e.g. FIG. 4 stacked portion 2), recesses (FIG. 17A recesses 90, column 9 lines 32-41) formed in multiple tiers and adjacent to a sidewall such that portions of a dielectric liner (80, column 5 lines 34-40) are located in the recesses.
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Jhothiraman by recessing both the first and second sidewalls and filling with the dielectric liner as taught by Nagashima in order to prevent dielectric breakdown at the end surface (e.g. Nagashima FIG. 26 end 82a) thereby achieving a higher breakdown voltage (Nagashima column 13 lines 19-32).
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Regarding claim 9, Jhothiraman in view of Nagashima yields the apparatus of claim 8, and Jhothiraman further teaches (FIG. 2) wherein the first and second contact structures have a same length (length of entire stack 202 as pictured).
Regarding claim 10, Jhothiraman in view of Nagashima yields the apparatus of claim 8, and Nagashima as applied to Jhothiraman further yields wherein the dielectric liner includes: silicon dioxide (Nagashima 81, column 9 lines 46-47) adjacent the first portion of the conductive materials (70), and the portions of the second dielectric liner (applying Nagashima’s liner 81 to both sides) include silicon dioxide adjacent the second portion of the conductive materials.
Regarding claim 11, Jhothiraman in view of Nagashima yields the apparatus of claim 10, and Nagashima further teaches wherein: the first dielectric liner includes silicon nitride (82, column 9 lines 47-48) adjacent the silicon dioxide (81, column 9 lines 46-47) of the first dielectric liner; and the second dielectric liner (when applying Nagashima to Jhothiraman) includes silicon nitride (Nagashima’s 82) adjacent the silicon dioxide (Nagashima’s 81) of the second dielectric liner.
Regarding claim 12, Jhothiraman in view of Nagashima yields the apparatus of claim 11, and Jhothiraman in view of Nagashima further teaches wherein: the first contact structure (Jhothiraman contact 248, see Examiner-annotated figure with claim 8 above) extends through the liner (242) which when applying the teachings of Nagashima includes the silicon nitride (Nagashima’s 82) and the silicon dioxide (Nagashima’s 81) of the first dielectric liner; and
the second contact structure (Jhothiraman another contact 248, see Examiner-annotated figure with claim 8 above) extends through the liner (242) which when applying the teachings of Nagashima includes the silicon nitride (Nagashima’s 82) and the silicon dioxide (Nagashima’s 81) of the second dielectric liner.
Regarding claim 13, Jhothiraman in view of Nagashima yields the apparatus of claim 8, and Jhothiraman further teaches a third contact structure (e.g. 250) adjacent the second contact structure and having a length (length is entire height of stack) in a same direction with respective lengths of the first and second contact structures.
Jhothiraman fails to clearly teach wherein the third contact structure is adjacent the first contact structure.
However, Jhothiraman teaches in FIG. 1 wherein three plurality of contact structures (116 in middle) have a same length (equivalent to height of the stack 102), including a configuration with first, second, and third contact structures (see Examiner-annotated figure below), the third contact structure adjacent the first contact structure:
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It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Jhothiraman in view of Nagashima with a plurality of equal height contacts between the staircase structures as taught by Jhothiraman in order to perform the required writing, reading, and erasing operations (Jhothiraman ¶ [0004]) and connecting with external circuits in the substrate (Nagashima column 6 lines 61-63).
Regarding claim 14, Jhothiraman in view of Nagashima yields the apparatus of claim 13, and Jhothiraman further teaches (FIG. 1) wherein the first, second, and third contact structures (see Examiner-annotated figure with claim 13 above) have a same length (length is entire height of stack 202 when applied to FIG. 2).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
U.S. Patent Application Publication Number 2023/0232629 A1 to Ma et al. teaches (e.g. FIG. 7E) a staircase liner (e.g. 730) and a plurality of contacts (514c, ¶ [0090],[0091]) passing through the liner into the substrate structure (522) which includes control circuitry and the like (¶ [0061],[0062]);
U.S. Patent Application Publication Number 2021/0020658 A1 to Eom teaches (e.g. FIG. 6F) a staircase liner (233, ¶ [0106]) and a plurality of contacts (295, ¶ [0141]) extending through the liner;
U.S. Patent Application Publication Number 2020/0144380 A1 to Hwang et al. teaches (e.g. FIG. 2B) a plurality of contacts (DVS on the far right) extending through a staircase liner (25);
U.S. Patent Application Publication Number 2020/0152654 A1 to Hwang et al. teaches (e.g. FIG. 8) a plurality of contacts (PPLG, ¶ [0090]) extending through a staircase liner (25 or 37, ¶ [0089]);
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Eric A. Ward/Primary Examiner, Art Unit 2891
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