DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II (claims 6-20), which also includes newly added claims 21-25, in the reply filed on 12/02/2025 is acknowledged.
Claims 1-5, drawn to non-elected Group I, have been cancelled by the Applicant in the response dated 12/02/2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 6-9, 11-17 and 19-25 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Tsai et al. (US 2021/0125875) hereinafter “Tsai”.
Regarding claim 6, Figs. 9, 10A-10C and 13 of Tsai teaches a method comprising: fabricating on a substrate (Item 20) a device comprising a first transistor in a first active region (See Picture 1 below), a second transistor in a second active region (See Picture 1 below) and a sacrificial gate structure (Combination of Items 34, 32 and 25) at a boundary (See Picture 1 below) between the first active region and the second active region; each of the first transistor, the second transistor and the sacrificial gate structure comprises (a) a fin channel (Items 24 or 25) extending from the substrate (Item 20) and (b) one or more gate layers (Items 34 and 32) over the fin channel (Items 24 or 25), each of the first transistor and the second transistor further comprises source/drain feature (Item 42); and forming a tapered trench (Fig. 13 Item 56 which includes both air and Item 54) at the boundary between the first active region and the second active region, wherein said forming comprises continuously etching the one or more gate layers (Items 34 and 32) of the sacrificial gate structure, the fin channel (Item 25) underneath the one or more gate layers of the sacrificial gate structure and a portion of the substrate (Paragraph 0048 where the trench extends into the substrate) at the boundary between the first active region and the second active region, wherein a width of the trench (Item 56 which includes both air and Item 54) at a top of the fin channel (Item 25) is greater than a width of the trench at a bottom of the one or more gate layers (Items 34 and 32) of the sacrificial gate structure (Paragraph 0041).
PNG
media_image1.png
517
543
media_image1.png
Greyscale
Picture 1 (Labeled version of Tsai Fig. 9)
Regarding claim 7, Tsai further teaches where the etching is dry etching (Paragraph 0040).
Regarding claim 8, Tsai further teaches where the one or more gate layers (Items 34 and 32) over the fin channel (Item 25) of the sacrificial gate structure comprise a metal gate layer (Item 34; Paragraph 0024) and a dielectric gate layer (Item 32; Paragraph 0024) and wherein the continuously etching comprises etching the metal gate layer (Item 34) and the dielectric gate layer (Item 32).
Regarding claim 9, Fig. 13 of Tsai further teaches where a portion of the metal gate layer (Item 34) and the dielectric gate layer (Item 32) along a tapered wall of the trench remains intact upon the etching.
Regarding claim 11, Tsai further teaches filling the tapered trench (Item 56) with a dielectric material (Item 60’; Paragraph 0049).
Regarding claim 12, Tsai further teaches where the dielectric material (Item 60’) is silicon nitride (Paragraph 0049).
Regarding claim 13, Tsai further teaches where each of the first transistor and the second transistor (See Picture 1 above) comprises a FinFET transistor (Paragraph 0005).
Regarding claim 14, Figs. 9, 10A-10C and 13 of Tsai teaches a method of fabricating a semiconductor device, comprising: providing a sacrificial structure (Combination of Items 34, 32 and 25) on a substrate (Item 20), the sacrificial structure comprises (a) a fin channel (Item 25) extending from the substrate (Item 20) and (b) one or more gate layers (Items 34 and 32) wrapping over the fin channel (Item 25), the sacrificial structure (Combination of Items 34, 32 and 25) is disposed at an active edge adjacent to an active region, and continuously etching the one or more gate layers (Items 34 and 32) of the sacrificial structure, the fin channel (Item 25) of the sacrificial structure and a portion of the substrate (Paragraph 0048 where the trench extends into the substrate) underneath the sacrificial gate structure to form a trench (Item 56 which includes both air and Item 54) having a tapered profile, so that a width of the trench (Item 56 which includes both air and Item 54) at a top of the fin channel (Item 25) is greater than a width of the trench at a bottom of the one or more gate layers (Items 34 and 32) (Paragraph 0041), and wherein the etching does not damage a source/drain feature (Item 42) within the adjacent active region.
Regarding claim 15, Tsai further teaches where the etching is dry etching (Paragraph 0040).
Regarding claim 16, Tsai further teaches where the one or more gate layers (Items 34 and 32) over the fin channel (Item 25) of the sacrificial gate structure comprise a metal gate layer (Item 34; Paragraph 0024) and a dielectric gate layer (Item 32; Paragraph 0024) and wherein the continuously etching comprises etching the metal gate layer (Item 34) and the dielectric gate layer (Item 32).
Regarding claim 17, Fig. 13 of Tsai further teaches where a portion of the metal gate layer (Item 34) and the dielectric gate layer (Item 32) along a tapered wall of the trench remains intact upon the etching.
Regarding claim 19, Tsai further teaches filling the trench (Item 56) with a dielectric material (Item 60’; Paragraph 0049).
Regarding claim 20, Tsai further teaches where the dielectric material (Item 60’) is silicon nitride (Paragraph 0049).
Regarding claim 21, Figs. 9, 10A-10C and 13 of Tsai teaches a method comprising: fabricating on a substrate (Item 20) a device comprising a first transistor in a first active region (See Picture 1 above), a second transistor in a second active region (See Picture 1 above) and a sacrificial gate structure (Combination of Items 34, 32 and 25) at a boundary (See Picture 1 above) between the first active region and the second active region; each of the first transistor, the second transistor and the sacrificial gate structure comprises (a) a fin channel (Items 24 or 25) extending from the substrate (Item 20) and (b) one or more gate layers (Items 34 and 32) over the fin channel (Items 24 or 25), each of the first transistor and the second transistor further comprises source/drain feature (Item 42); and forming a tapered trench (Fig. 13 Item 56 which includes both air and Item 54) at the boundary between the first active region and the second active region, wherein said forming comprises continuously etching the one or more gate layers (Items 34 and 32) of the sacrificial gate structure, the fin channel (Item 25) underneath the one or more gate layers of the sacrificial gate structure and a portion of the substrate (Paragraph 0048 where the trench extends into the substrate) at the boundary between the first active region and the second active region, wherein an angle between a tapered wall of the tapered trench (Item 56 which includes air and Item 54) and a first direction (Left to right across the page) perpendicular to a second direction (Up and down across the page) in which the fin channel protrudes from the substrate (Item 20) is from about 45 degrees to less than about 90 degrees (Paragraph 0041).
Regarding claim 22, Tsai further teaches where a width of the trench (Item 56) at a top of the fin channel (Item 25) is greater than a width of the trench at a bottom of the one or more gate layers (Combination of Items 34 and 32) of the sacrificial gate structure (Paragraph 0041).
Regarding claim 23, Tsai further teaches where the angle between the tapered wall of the tapered trench (Item 56 which includes air and Item 54) and the first direction is from about 45 degrees to about 80 degrees (Paragraph 0041).
Regarding claim 24, Tsai further teaches where the trench (Item 56 which includes air and Item 54) has a tapered wall (Paragraph 0041) having a tapered portion, wherein an angle between the tapered portion of the tapered wall of the trench and a first direction (Left to right across the page) perpendicular to a second direction (Up and down across the page) in which the fin channel (Item 25) protrudes from the substrate (Item 20) is from about 45 degrees to less than about 90 degrees (Paragraph 0041).
Regarding claim 25, Tsai further teaches where the angle between the tapered portion of of the tapered wall of the trench (Item 56 which includes air and Item 54) and the first direction is from about 45 degrees to about 80 degrees (Paragraph 0041).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US 2021/0125875) hereinafter “Tsai” in view of Tsai et al. (US 2020/0035800) hereinafter “Tsai2”.
Regarding claim 10, Tsai teaches all of the elements of the claimed invention as stated above except where the dielectric gate layer comprises a high-k dielectric gate layer.
Tsai2 teaches where a dielectric gate layer is made of a high-k dielectric material (Paragraph 0034).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the dielectric gate layer comprise a high-k dielectric layer because this material is known to act as a dummy gate dielectric material in a replacement gate process (Paragraph 0034) and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Regarding claim 18, Tsai teaches all of the elements of the claimed invention as stated above except where the dielectric gate layer comprises a high-k dielectric gate layer.
Tsai2 teaches where a dielectric gate layer is made of a high-k dielectric material (Paragraph 0034).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the dielectric gate layer comprise a high-k dielectric layer because this material is known to act as a dummy gate dielectric material in a replacement gate process (Paragraph 0034) and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC K ASHBAHIAN whose telephone number is (571)270-5187. The examiner can normally be reached 8-5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891