DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment dated 02/02/2026, in which claims 17-22, 30, 35 amended, claims 1-16, 25-26 were cancelled, claims 37-38 were added, claim 33 was withdrawn, has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ozaki et al. (US Pat. 5164803) in view of Yang et al. (US Pub. 20210273096) and Niimi et al. (US Pub. 20160351566) and.
Regarding claim 17, Ozaki et al. discloses in Fig. 2, Figs. 4D-4L a method, comprising:
providing a substrate [1] having an N well [25] abutting a P well [26] along a boundary [Fig. 4D];
forming an active region [14] over the substrate, the active region extending across the boundary [Fig. 4E];
forming a dielectric layer [16] over the substrate and the active region [Fig. 4F];
forming a gate electrode [17] over the dielectric layer [16][Fig. 4F];
patterning the gate electrode [17] and the dielectric layer [16] to form a plurality of gate structures [11] having a uniform gate pitch, wherein the plurality of gate structures [11] comprise a first gate structure over the P well [26], a second gate structure over the N well [25] and a third gate structure disposed directly over the boundary [Fig. 4H];
forming N-type source/drain features [6] over the P well [26] and P-type source/drain features [27] over the N well [25].
Ozaki et al. fails to disclose
the plurality of gate structures comprises a plurality of first gate structures and a plurality of second gate structures.
replacing the plurality of gate structures with a plurality of gate stacks.
Niimi et al. discloses in Fig. 1A, Fig. 2D-2E, paragraph [0030]-[0031]
the plurality of gate structures comprises a plurality of first gate structures [140n] and a plurality of second gate structures [140p].
replacing the plurality of gate structures [140n and 140p] with a plurality of gate stacks [150n, 150p].
In addition, “mere duplication of parts has no patentable significance unless a new and unexpected result is produced”. MPEP 2144.04 VI B.
Yang et al. discloses in Fig. 7-Fig. 16D, paragraph [0010], [0011], [0056]-[0060]
replacing the plurality of gate structures [76 and 70] with a plurality of gate stacks [96 and 98].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Niimi et al. and Yang et al. into the method of Ozaki et al. to include the plurality of gate structures comprises a plurality of first gate structures and a plurality of second gate structures; replacing the plurality of gate structures with a plurality of gate stacks. The ordinary artisan would have been motivated to modify Ozaki et al. in the above manner for the purpose of forming integrated circuit having increased packing density and improved device performance; forming HK/MG replacement gate and improving device performance [paragraph [0006]-[0007], [0030] of Niimi et al., paragraph [0018] of Yang et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 18, Ozaki et al. discloses in Fig. 2
wherein the gate structure [11] is disposed between one of the N-type source/drain features [6] and one of the P-type source/drain features [27].
Ozaki et al. fails to disclose
wherein the forming of the N-type source/drain features and P-type source/drain features comprises:
recessing, by using the plurality of gate structures as an etch mask, the active region to form a plurality of first trenches over the P well and a plurality of second trenches over the N well;
epitaxially form N-type source/drain features in the plurality of first trenches; and
epitaxially form P-type source/drain features in the plurality of second trenches.
Yang et al. discloses in Fig. 8A-11B, paragraph [0014], [0026]-[0027], [0045]-[0049]
wherein the forming of the N-type source/drain features [90 in region 50A] and P-type source/drain features [90 in region 50B] comprises:
recessing, by using the plurality of gate structures [76 and 70] as an etch mask, the active region to form a plurality of first trenches [84 in region 50A] over the P well [p Well in region 50A] and a plurality of second trenches [84 in region 50B] over the N well [n well in region 50B];
epitaxially form N-type source/drain features [90 in region 50A] in the plurality of first trenches [84 in region 50A]; and
epitaxially form P-type source/drain features in the plurality of second trenches [84 in region 50B].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Yang et al. into the method of Ozaki et al. to include wherein the forming of the N-type source/drain features and P-type source/drain features comprises: recessing, by using the plurality of gate structures as an etch mask, the active region to form a plurality of first trenches over the P well and a plurality of second trenches over the N well; epitaxially form N-type source/drain features in the plurality of first trenches; and epitaxially form P-type source/drain features in the plurality of second trenches. The ordinary artisan would have been motivated to modify Ozaki et al. in the above manner for the purpose of providing suitable alternative method for forming source/drain features to exert stress in the channel layers, thereby improving performance [paragraph [0045] of Yang et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claims 19-20, Ozaki et al. fails to disclose
wherein the forming of the active region comprises:
forming a vertical stack of alternating channel layers and sacrificial layers over the substrate; and
patterning the vertical stack and a portion of the substrate to form the active region;
wherein the replacing of the plurality of gate structures comprises:
performing a first etching process to remove the plurality of gate structures to form first plurality of openings;
selectively removing the sacrificial layers to form second plurality of openings; and
forming the plurality of gate stacks in the first plurality of openings and the second plurality of openings,
wherein one of the plurality of gate stacks is disposed directly over the boundary. Yang et al. discloses in Fig. 2-Fig. 3, Fig. 13B-16D
wherein the forming of the active region [55] comprises:
forming a vertical stack [54 and 52] of alternating channel layers and sacrificial layers over the substrate [50 and 51]; and
patterning the vertical stack [54 and 52] and a portion of the substrate [50 and 51] to form a fin-shaped active region [55];
wherein the replacing of the plurality of gate structures [76 and 70] comprises:
performing a first etching process to remove the plurality of gate structures [76 and 70] to form first plurality of openings [94][paragraph [0053]];
selectively removing the sacrificial layers to form second plurality of openings [paragraph [0054]-[0055]]; and
forming the plurality of gate stacks [96 and 98] in the first plurality of openings and the second plurality of openings [paragraph [0056]].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Yang et al. into the method of Ozaki et al. to include wherein the forming of the active region comprises: forming a vertical stack of alternating channel layers and sacrificial layers over the substrate; and patterning the vertical stack and a portion of the substrate to form a fin-shaped active region; wherein the replacing of the plurality of gate structures comprises: performing a first etching process to remove the plurality of gate structures to form first plurality of openings; selectively removing the sacrificial layers to form second plurality of openings; and forming the plurality of gate stacks in the first plurality of openings and the second plurality of openings. The ordinary artisan would have been motivated to modify Ozaki et al. in the above manner for the purpose of providing nanostructure field-effect transistors having reduced leakage and improved performance [paragraph [0008], [0018], [0025] of Yang et al.].
Ozaki et al. discloses in Fig. 2, one of the gate structures [11] is disposed directly over the boundary. Yang et al. suggests replacing the gate structures [76 and 70] with the gate stacks [96 and 98]. Thus, the combination of Ozaki et al. and Yang et al. result to “one of the gate stacks is disposed directly over the boundary”.
Claims 21-24, 27 are rejected under 35 U.S.C. 103 as being unpatentable over Ishikawa (US Pat. 5841185) in view of Ching et al. (US Pub. 20150303197).
Regarding claims 21-22, Ishikawa discloses in Fig. 5, Fig. 6A, Fig. 7A-7G, Fig. 11 a method, comprising:
forming a first-doped region [102] in a substrate [101], the first-doped region [102] comprising a first dopant having a first doping polarity [p type];
forming a second-doped region [103] in the substrate [101] and abutting the first doped region [102] at a boundary, the second-doped region [103] comprising a second dopant having a second doping polarity [n type] different from the first doping polarity [p type];
forming an active region [upper region of 101] over the substrate [101] and extending lengthwise across the boundary;
forming a plurality of first gate structures [123 and 121] over the first-doped region [102] and straddling the active region [upper region of 101];
forming a plurality of second gate structure [121 and 124] over the second-doped region [103] and straddling the active region [upper region of 101];
forming a third gate structure [121 and 122] disposed between the plurality of first gate structures [123 and 121] and the plurality of second gate structures [121 and 124], wherein the third gate structure [121 and 122] extends over the boundary, wherein the third gate structure [121 and 122] comprises a gate dielectric layer [121] and a gate electrode [122] over the gate dielectric layer [121];
forming a plurality of first source/drain features [105 and 153] over the first-doped region [102]; and
forming a plurality of second source/drain features [154 and 108] over the second-doped region [103];
wherein the forming of the plurality of second gate structures [121 and 124], and the forming of the third gate structure [121 and 122] are performed simultaneously [Fig. 7C, column 10, lines 54-67].
Ishikawa fails to disclose
the active region comprises a fin;
after forming the plurality of first gate structures, forming the plurality of second gate structure;
after forming the plurality of first gate structures, forming the third gate structure.
Ching et al. discloses in Fig. 2, Fig. 9B, Fig. 14B, paragraph [0003], [0018], [0037]-[0039], [0045]-[0046]
the active region comprises a fin;
after forming the plurality of first gate structures [348], forming the plurality of second gate structure [248];
Ishikawa discloses the forming of the plurality of second gate structures [121 and 124], and the forming of the third gate structure [121 and 122] are performed simultaneously. Thus, the combination of Ishikawa and Ching et al. would result to “after forming the plurality of first gate structures, forming the plurality of second gate structure and the third gate structure.”
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Ching et al. into the method of Ishikawa to include the active region comprises a fin; after forming the plurality of first gate structures, forming the plurality of second gate structure; after forming the plurality of first gate structures, forming the third gate structure. The ordinary artisan would have been motivated to modify Ishikawa in the above manner for the purpose of providing suitable order for performing the steps of forming the plurality of first gate structures, forming the plurality of second gate structure and forming the third gate structure and providing device having improved performance; [paragraph [0002]-[0003] of Ching et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 23, Ishikawa discloses in Fig. 5, Fig. 6A and Fig.7G
wherein a center line of the third gate structure [121 and 122] is aligned with the boundary.
Regarding claim 24, Ishikawa discloses in Fig. 5, Fig. 6A
wherein a gate pitch of the plurality of first gate structures [123 and 121] is equal to a gate pitch of the plurality of second gate structures [124 and 121].
Regarding claim 27, Ishikawa discloses in Fig. 5, Fig. 6A
wherein the plurality of first source/drain features [105 and 153] comprise the second dopant [n type], and the plurality of the second source/drain features [108 and 154] comprise the first dopant [p type], and wherein, in a top view, one [153] of the plurality of first source/drain features [105 and 153] and one [154] of the plurality of second source/drain features [108 and 154] are disposed immediately adjacent to the third gate structure [121 and 122].
Claim 21-24, 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US Pub. 20190386000) in view of Ishikawa (US Pat. 5841185) and Smith et al. (US Pub. 20170345914) and Ching et al. (US Pub. 20150303197).
Regarding claims 21, 22 and 27, Chen et al. discloses in Fig. 3B, Fig. 9
forming a first-doped region [108] in a substrate [101], the first-doped region [108 in region D1] comprising a first dopant having a first doping polarity [n type];
forming a second-doped region [108 in region D2] in the substrate [101] and abutting the first doped region [108 in region D1] at a boundary [boundary between D1 and D2 or between 302 and 304];
forming a fin [106] over the substrate and extending lengthwise across the boundary;
forming a plurality of first gate structures [112 in region D1] over the first-doped region [108 in region D1] and straddling the fin [106];
forming a plurality of second gate structure [112 in region D2] over the second-doped region [108 in region D2] and straddling the fin [106];
forming a third gate structure [114] disposed between the plurality of first gate structures [112 in region D1] and the plurality of second gate structures [112 in region D2], wherein the third gate structure [114] extends over the boundary;
forming a plurality of first source/drain features [126 and 128] over the first-doped region [108 in region D1]; and
forming a plurality of second source/drain features [126 and 128] over the second-doped region [108 in region D2],
wherein, in a top view, one [128] of the plurality of first source/drain features and one [126] of the plurality of second source/drain features are disposed immediately adjacent to the third gate structure [114].
Chen et al. fails to disclose
the second-doped region comprising a second dopant having a second doping polarity different from the first doping polarity;
wherein the plurality of first source/drain features comprise the second dopant, and the plurality of the second source/drain features comprise the first dopant.
Ishikawa discloses in Fig. 5, Fig. 6A, Fig. 7A-7G,
the second-doped region [103] comprising a second dopant having a second doping polarity [n type] different from the first doping polarity [p type];
wherein the plurality of first source/drain features [105 and 153] comprise the second dopant [n type], and the plurality of the second source/drain features [108 and 154] comprise the first dopant [p type], and
wherein, in a top view, one [153] of the plurality of first source/drain features [105 and 153] and one [154] of the plurality of second source/drain features [108 and 154] are disposed immediately adjacent to the third gate structure [121 and 122].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Ishikawa into the method of Chen et al. to include the second-doped region comprising a second dopant having a second doping polarity different from the first doping polarity; wherein the plurality of first source/drain features comprise the second dopant, and the plurality of the second source/drain features comprise the first dopant. The ordinary artisan would have been motivated to modify Chen et al. in the above manner for the purpose of providing suitable dopant and conductivity of the second-doped region to form a CMOS circuit on the same active layer. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Chen et al. fails to disclose
after forming the plurality of first gate structures, forming the plurality of second gate structure;
after forming the plurality of first gate structures, forming the third gate structure;
wherein the forming of the plurality of second gate structures, and the forming of the third gate structure are performed simultaneously.
Ching et al. discloses in Fig. 2, Fig. 9B, Fig. 14B, paragraph [0003], [0018], [0037]-[0039], [0045]-[0046]
after forming the plurality of first gate structures [348], forming the plurality of second gate structure [248];
Ishikawa discloses in Fig. 7C, column 10, lines 54-67
wherein the forming of the plurality of first gate structures [123 and 121], the forming of the plurality of second gate structures [121 and 124], and the forming of the third gate structure [121 and 122] are performed simultaneously.
Thus, the combination of Ishikawa and Ching et al. would result to “after forming the plurality of first gate structures, forming the plurality of second gate structure and the third gate structure.”
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Ishikawa and Ching et al. into the method of Chen et al. to include after forming the plurality of first gate structures, forming the plurality of second gate structure; after forming the plurality of first gate structures, forming the third gate structure; wherein the forming of the plurality of second gate structures, and the forming of the third gate structure are performed simultaneously. The ordinary artisan would have been motivated to modify Ishikawa in the above manner for the purpose of providing suitable order for performing the steps of forming the plurality of first gate structures, forming the plurality of second gate structure and forming the third gate structure and providing device having improved performance; [paragraph [0002]-[0003] of Ching et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Chen et al. fails to disclose
wherein the third gate structure comprises a gate dielectric layer and a gate electrode over the gate dielectric layer.
Smith et al. discloses in Fig. 9, paragraph [0076], [0082]
wherein the third gate structure [609] comprises a gate dielectric layer [401] and a gate electrode [501] over the gate dielectric layer [401].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Smith et al. into the method of Chen et al. to include wherein the third gate structure comprises a gate dielectric layer and a gate electrode over the gate dielectric layer. The ordinary artisan would have been motivated to modify Chen et al. in the above manner for the purpose of providing suitable alternative configuration of a dummy gate structure that may be used for providing an electrical insulation between N-channel transistors and P-channel transistors [paragraph [0076], [0082] of Smith et al.].
Regarding claims 23-24, Chen et al. discloses in Fig. 9
wherein a center line of the third gate structure [114] is aligned with the boundary.
wherein a gate pitch of the plurality of first gate structures [112 in region D1] is equal to a gate pitch of the plurality of second gate structures [112 in region D2].
Ishikawa also discloses in Fig. 5, Fig. 6A and Fig.7G
wherein a center line of the third gate structure [121 and 122] is aligned with the boundary;
wherein a gate pitch of the plurality of first gate structures [123 and 121] is equal to a gate pitch of the plurality of second gate structures [124 and 121].
Regarding claim 28, Chen et al. fails to disclose
forming first gate vias electrically coupled to one or more of the plurality of first gate structures and second gate vias electrically coupled to one or more of the plurality of second gate structures without forming a gate via electrically coupled to the third gate structure.
Chen et al. and Smith et al. both discloses the plurality of first gate structures and the plurality of second gate structures are active gate structures of active device while the third gate structure is an inactive/dummy gate structure.
Smith et al. further discloses in Fig. 9
forming first gate vias [910] electrically coupled to one or more of the plurality of first gate structures [902] and second gate vias [712] electrically coupled to one or more of the plurality of second gate structures [606] without forming a gate via electrically coupled to the third gate structure [609].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Smith et al. into the method of Chen et al. to include forming first gate vias electrically coupled to one or more of the plurality of first gate structures and second gate vias electrically coupled to one or more of the plurality of second gate structures without forming a gate via electrically coupled to the third gate structure. The ordinary artisan would have been motivated to modify … in the above manner for the purpose of forming electrical connections to active first and second gate structures while ensuring the third gate remain inactive.
Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US Pub. 20190386000) in view of Ishikawa (US Pat. 5841185) and Smith et al. (US Pub. 20170345914) and Ching et al. (US Pub. 20150303197) as applied to claim 21 above and further in view of Kim et al. (US Pub. 20200035705).
Regarding claim 29, Chen et al. fails to disclose
wherein the fin comprises a vertical stack of alternating channel layers and sacrificial layers, and the method further comprises:
selectively removing the sacrificial layers, wherein each gate structure of the plurality of first gate structures, the plurality of second gate structures, and the third gate structure wraps around the channel layers.
Kim et al. discloses in Fig. 1, Fig. 8A, Fig. 12A-B, Fig. 17A-B, Fig. 18
wherein the fin comprises a vertical stack of alternating channel layers and sacrificial layers, and the method further comprises:
selectively removing the sacrificial layers, wherein each gate structure of the plurality of first gate structures [GE in LC1], the plurality of second gate structures [GE in LC2], and the third gate structure [GEd] wraps around the channel layers.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Kim et al. into the method of Chen et al. to include wherein the fin comprises a vertical stack of alternating channel layers and sacrificial layers, and the method further comprises: selectively removing the sacrificial layers, wherein each gate structure of the plurality of first gate structures, the plurality of second gate structures, and the third gate structure wraps around the channel layers. The ordinary artisan would have been motivated to modify Chen et al. in the above manner for the purpose of providing method for forming nanostructure FETs to improve device performance [paragraph [0003] of Kim et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claims 30-32, 34-36 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US Pub. 20190386000) in view of Ishikawa (US Pat. 5841185), Mehandru et al. (US Pub. 20200006559) and Smith et al. (US Pub. 20170345914).
Regarding claim 30, Chen et al. discloses in Fig. 3B, Fig. 9 a method, comprising:
receiving an intermediate structure comprising a substrate, the substrate comprising an n- type well [108 in region D1] and a second well [108 in region D2] disposed laterally adjacent to the n-type well [108 in region D1] along a first direction;
forming a fin [106] protruding from the substrate, the fin extending lengthwise along the first direction and extending across a boundary between the n-type well [108 in region D1] and the second well [108 in region D2],
forming a dummy gate stack [dummy gate for forming 112 and 114] over the fin [106] and extending lengthwise along a second direction different from the first direction, wherein the dummy gate stack is disposed over both the n-type well [108 in D1] and the p-type well second well [108 in region D2][paragraph [0027] “dummy gates are first formed by deposition and patterning, in which the patterning further includes lithography process and etching. Afterward, a subset of the dummy gates is replaced to form gates 112 by depositing a gate dielectric layer and a gate electrode while the rest of the dummy gates are replaced to form dielectric gates 114 by depositing only dielectric material(s)”].
Chen et al. fails to disclose
the second well comprises a p-type well.
Ishikawa discloses in Fig. 5, Fig. 6A, Fig. 7A-7G,
the second well [102] comprises a p-type well.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Ishikawa into the method of Chen et al. to include the second well comprises a p-type well. The ordinary artisan would have been motivated to modify Chen et al. in the above manner for the purpose of providing suitable dopant and conductivity of the second-doped region to form a CMOS circuit on the same active layer. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Chen et al. fails to disclose
wherein the fin comprises a vertical stack of alternating channel layers and sacrificial layers;
recessing the fin to form a first trench over the n-type well and a second trench over the p-type well, the first trench and the second trench being disposed on opposite sides of the dummy gate stack;
forming a p-type epitaxial feature in the first trench and an n-type epitaxial feature in the second trench;
selectively removing the sacrificial layers and the dummy gate stack to form openings;
forming a gate structure in the openings and wrapping around the channel layers, wherein the channel layers extend from the p-type epitaxial feature to the n-type epitaxial feature.
Mehandru et al. discloses in Fig. 3-Fig. 10A,
wherein the fin comprises a vertical stack of alternating channel layers and sacrificial layers;
recessing the fin to form a first trench over a first region [right region] and a second trench over a second region [left region], the first trench and the second trench being disposed on opposite sides of the dummy gate stack [320][Fig. 5A];
forming a first epitaxial feature [360 in right region] in the first trench and a second epitaxial feature [360 in left region] in the second trench [Fig. 7A];
selectively removing the sacrificial layers [311] and the dummy gate stack [320] to form openings [Fig. 8A];
forming a gate structure [380] in the openings and wrapping around the channel layers [315], wherein the channel layers extend from the first epitaxial feature [360 in right region] to the second epitaxial feature [360 in left region][Fig. 10A, Fig. 13A, paragraph [0034]].
Ishikawa discloses the first region comprises an N well and the second region comprises a P well. Ishikawa further discloses the first feature comprises P-type feature and the second feature comprises n-type feature.
Thus, the combination of Mehandru et al. and Ishikawa would result to “recessing the fin to form a first trench over the n-type well and a second trench over the p-type well; forming a p-type epitaxial feature in the first trench and an n-type epitaxial feature in the second trench; wherein the channel layers extend from the p-type epitaxial feature to the n-type epitaxial feature.”
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Mehandru et al. and Ishikawa into the method of Chen et al. to include wherein the fin comprises a vertical stack of alternating channel layers and sacrificial layers; recessing the fin to form a first trench over the n-type well and a second trench over the p-type well, the first trench and the second trench being disposed on opposite sides of the dummy gate stack; forming a p-type epitaxial feature in the first trench and an n-type epitaxial feature in the second trench; selectively removing the sacrificial layers and the dummy gate stack to form openings; forming a gate structure in the openings and wrapping around the channel layers, wherein the channel layers extend from the p-type epitaxial feature to the n-type epitaxial feature. The ordinary artisan would have been motivated to modify Chen et al. in the above manner for the purpose of providing method for forming CMOS circuit comprising GAA transistors to improve device performance [paragraph [0001]-[0002] of Mehandru et al.]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Chen et al. fails to disclose
wherein the gate structure comprises a gate dielectric layer and a gate electrode over the gate dielectric layer and wherein the gate structure is electrically floating.
Mehandru et al. discloses in paragraph [0073], [0082]-[0083],
the gate structure [380] comprises a gate dielectric [334] and a gate electrode [336] over the gate dielectric layer [334].
Smith et al. discloses in Fig. 9, paragraph [0076], [0082]
wherein the gate structure [609] comprises a gate dielectric layer [401] and a gate electrode [501] over the gate dielectric layer [401], and wherein the gate structure [609] is electrically floating.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Mehandru et al. and Smith et al. into the method of Chen et al. to include wherein the gate structure comprises a gate dielectric layer and a gate electrode over the gate dielectric layer, and wherein the gate structure is electrically floating. The ordinary artisan would have been motivated to modify Chen et al. in the above manner for the purpose of providing suitable alternative configuration of a dummy gate structure that may be used for providing an electrical insulation between N-channel transistors and P-channel transistors [paragraph [0076], [0082] of Smith et al.].
Regarding claim 31, Mehandru et al. discloses in Fig. 6A, Fig. 10A
after the recessing of the fin, forming inner spacers [350] disposed between the first epitaxial feature and the gate structure [380] and between the second epitaxial feature and the gate structure [380].
Ishikawa further discloses the first feature comprises P-type feature and the second feature comprises n-type feature.
Thus, the combination of Mehandru et al. and Ishikawa would result to “after the recessing of the fin, forming inner spacers disposed between the p-type epitaxial feature and the gate structure and between the n-type epitaxial feature and the gate structure.”
Regarding claim 32, Chen et al. discloses in Fig. 9
forming p-type transistors over the n-type well [108 in region D1]; and
forming second transistors over the second well [108 in region D1], wherein, in a top view, active regions of the p-type transistors and active regions of the second transistors are portions of a continuous active region that includes the first feature and the second feature.
Ishikawa discloses the second transistors comprise n-type transistors; the second region comprises a P well; the first feature comprises P-type feature and the second feature comprises n-type feature.
Mehandru et al. discloses the first feature comprises the first epitaxial structure and the second feature comprises the second epitaxial structure.
Thus, the combination of Chen et al., Ishikawa and Mehandru et al. result to limitation of claim 32 “forming p-type transistors over the n-type well; and forming n-type transistors over the p-type well, wherein, in a top view, active regions of the p-type transistors and active regions of the n- type transistors are portions of a continuous active region that includes the p-type epitaxial feature and the n-type epitaxial feature.”
Regarding claim 34, Ishikawa discloses in Fig. 6A, Fig. 7F
wherein the p-type feature and source/drain features of the p-type transistors are formed simultaneously, and the n-type feature and source/drain features of the n-type transistors are formed simultaneously.
Mehandru et al. discloses in Fig. 7A
wherein the first epitaxial feature and source/drain features of the first transistors are formed simultaneously, and the second epitaxial feature and source/drain features of the second transistors are formed simultaneously.
Thus, the combination of Chen et al., Ishikawa, Mehandru et al. result to “wherein the p-type epitaxial feature and source/drain features of the p-type transistors are formed simultaneously, and the n-type epitaxial feature and source/drain features of the n-type transistors are formed simultaneously.”
Regarding claims 35-36, Mehandru et al. discloses in paragraph [0073], [0082]-[0083],
the gate electrode 336 comprises a p-type work function metal layer [work function layer of] over the gate dielectric layer [334];
forming a gate spacer [332] extending along a sidewall surface of the dummy gate stack [320], wherein a dielectric constant [high-k dielectrics] of the gate dielectric layer [334] is greater than a dielectric constant [a low dielectric constant] of the gate spacer [332][paragraph [0057], [0078]-[0079]].
Claims 37-38 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US Pub. 20190386000) in view of Ishikawa (US Pat. 5841185) and Smith et al. (US Pub. 20170345914) and Ching et al. (US Pub. 20150303197) as applied to claim 21 above and further in view of Niimi et al. (US Pub. 20160351566).
Regarding claim 37, Chen et al. appears to disclose in paragraph [0031]
wherein the plurality of first gate structures comprise a number of M1 first gate structures, the plurality of second gate structures comprise a number of M2 second gate structures, M1 is an integer and is no less than 3, and M2 is an integer and is no less than 3 [“Each standard cell includes at least one gate 112”].
For further support, Niimi et al. is cited.
Niimi et al. discloses in Fig. 1A, Fig. 2F
wherein the plurality of first gate structures comprise a number of M1 first gate structures [140n], the plurality of second gate structures [140p] comprise a number of M2 second gate structures, M1 is an integer and is no less than 3, and M2 is an integer and is no less than 3.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Niimi et al. into the method of Chen et al. to include wherein the plurality of first gate structures comprise a number of M1 first gate structures, the plurality of second gate structures comprise a number of M2 second gate structures, M1 is an integer and is no less than 3, and M2 is an integer and is no less than 3. The ordinary artisan would have been motivated to modify Chen et al. in the above manner for the purpose of forming integrated circuit having increased packing density and improved device performance. In addition, “mere duplication of parts has no patentable significance unless a new and unexpected result is produced”. MPEP 2144.04 VI B.
Regarding claim 38, Chen et al. fails to disclose
wherein the third gate structure is electrically floating, wherein at least two of the number of M1 first gate structures adjacent to the third gate structure are electrically floating, and at least two of the number of M2 second gate structures adjacent to the third gate structure are electrically floating.
Chen et al. suggests in Fig. 1B, Fig. 2B, Fig. 4B, Fig. 5B
the number of dummy gates between a first gate structure and a second gate structure can be adjusted.
Smith et al. discloses in Fig. 9
the third gate structure/dummy gate structure is electrically floating to provide isolation between active NMOS and PMOS devices.
Niimi et al. discloses in Fig. 1A, Fig. 2F
the plurality of first gate structures [140p] comprise at least 3 first gate structures the plurality of second gate structures [140n] comprise at least 3 second gate structures.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Chen et al., Smith et al., Niimi et al. to include wherein the third gate structure is electrically floating, wherein at least two of the number of M1 first gate structures adjacent to the third gate structure are electrically floating, and at least two of the number of M2 second gate structures adjacent to the third gate structure are electrically floating. The ordinary artisan would have been motivated to modify Chen et al., Smith et al., Niimi et al. in the above manner for the purpose of obtaining desired isolation between active NMOS and PMOS devices and obtaining standard cells having desired active devices [paragraph [0064] of Chen et al.].
Response to Arguments
Applicant’s arguments with respect to claims 17-24, 27-32, 34-38 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made FINAL.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SOPHIA T NGUYEN/ Primary Examiner, Art Unit 2893
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