DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The IDS filed on 07/29/2022 and 11/04/2025 have been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Package substrate having an undercut region between facing surfaces of a dielectric layer and a protection layer and semiconductor package including the same.
Claim Objections
Claims 6 and 16 are objected to because of the following informalities:
In claim 6, line 2, “about 0.7 time” should be --about 0.7 times--.
Claim 16 recites “the fourth opening” in line 5, there is insufficient antecedent basis for this limitation in the claim, however claim 16 recites “a fourth opening” in line 6. Therefore, it is suggested that the limitation as recited in lines 5-7 of claim 16 should be rephase as --an upper plating pattern on the upper conductive pad, the upper protection layer including a fourth opening that exposes the upper plating pattern on the upper conductive pad-- in order to improve clarity.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6, 7, and 10-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (U.S. Pub. 2021/0392757).
In re claim 1, Chen discloses a package substrate 10 (see paragraph [0023] and figs. 1-4), comprising: a dielectric layer 111 (see paragraphs [0021], [0022] and figs. 1-4); a conductive pad 16 (see paragraph [0023] and figs. 1-4, notes that the claims are given the broadest reasonable interpretation (In re Hyatt, 211 F. 3d 1367, 1372, 54 USPQ2d 1664, 1667 (Fed. Cir. 2000)), therefore, since element 16 is a conductive structure for electrically connecting various wiring layers, it constitutes as a conductive pad) and a wiring pattern 12 (including portions 123,125) on the dielectric layer 111 (see paragraphs [0018], [0020] and figs. 1-4); a protection layer 40 (solder resist layer) on the dielectric layer 111 (see paragraphs [0024], [0025], [0026] and figs. 1-4), the protection layer 40 covering the wiring pattern 12; and an undercut region between facing surfaces of the dielectric layer 111 and the protection layer 40 (see paragraphs [0021], [0023], [0025], [0026] and figs. 3-4), the undercut region exposing a sidewall of the wiring pattern (see paragraphs [0027], [0028], [0029] and figs. 3-4, note that, the undercut region exposing sidewalls of portion 125 of the wiring pattern 12).
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Chen is silent to wherein a width of the undercut region being less than a width of the wiring pattern.
However, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to optimize the width of the undercut region with respect to the width of the wiring pattern so that the width of the undercut region being less than the width of the wiring pattern since it is respectfully submitted that the configuration regarding about width of the undercut region and the width of the wiring pattern was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration was significant (In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966)). Furthermore, a change in size is generally recognized as being within the level of ordinary skill in the art. See In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955), Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), and MPEP 2144.04.
In re claim 2, as applied to claim 1 above, Chen discloses wherein the protection layer 40 has a first opening 41 that exposes a portion of the dielectric layer 111, and the undercut region is connected to the first opening 41 (see paragraphs [0027], [0028], [0029] and figs. 3-4).
In re claim 3, as applied to claim 1 above, Chen discloses wherein the width of the undercut region decreases with increasing distance from the wiring pattern 125 (see paragraphs [0027], [0028] and fig. 3).
In re claim 4, as applied to claim 1 above, Chen is silent to wherein a portion of the protection layer facing the undercut region has a rounded sidewall.
However, it is respectfully submitted that the configuration regarding about shape of the portion of the protection layer was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration was significant (In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966)).
In re claim 6, as applied to claim 1 above, Chen is silent to wherein the width of the undercut region is about 0.2 times to about 0.7 time the width of the wiring pattern.
However, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to optimize the width of the undercut region to be about 0.2 times to about 0.7 times the width of the wiring pattern since it is respectfully submitted that the configuration regarding about width of the undercut region and the width of the wiring pattern was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration was significant (In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966)). Furthermore, a change in size is generally recognized as being within the level of ordinary skill in the art. See In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955), Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), and MPEP 2144.04.
In re claim 7, as applied to claim 1 above, Chen is silent to wherein the width of the wiring pattern is in a range of about 15 µm to about 25 µm.
However, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to optimize the width of the wiring pattern to be in a range of about 15 µm to about 25 µm because where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See in re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955).
In re claim 10, Chen discloses a package substrate 10 (see paragraph [0023] and figs. 1-4), comprising: a dielectric layer 111; a lower conductive pad (bottom element 16 (see paragraph [0023] and figs. 1-4, notes that the claims are given the broadest reasonable interpretation (In re Hyatt, 211 F. 3d 1367, 1372, 54 USPQ2d 1664, 1667 (Fed. Cir. 2000)), therefore, since element 16 is a conductive structure for electrically connecting various wiring layers, it constitutes as a lower conductive pad) and a lower wiring pattern (lower wiring pattern 12) (including lower elements 123,125) on a bottom surface of the dielectric layer 111 (see paragraphs [0018], [0020] and figs. 1-4); an upper conductive pad (upper element 16) and an upper wiring pattern (upper wiring pattern 12) (including upper elements 123,125) on a top surface of the dielectric layer 111 (see paragraphs [0018], [0020] and figs. 1-4); a lower protection layer (bottom element 40) on the bottom surface of the dielectric layer 111, the lower protection layer covering the lower wiring pattern and having a first opening (lower opening 41) that exposes a portion of the bottom surface of the dielectric layer 111 (see paragraphs [0021], [0023], [0025], [0026] and figs. 3-4); an upper protection layer (upper element 40) on the top surface of the dielectric layer 111, the upper protection layer covering the upper wiring pattern and having a second opening (upper opening 41) that exposes a portion of the top surface of the dielectric layer 111; a lower undercut region between the dielectric layer 111 and the lower protection layer (lower element 40), the lower undercut region extending from the first opening (lower opening 41) to expose a sidewall of the lower wiring pattern (see paragraphs [0027], [0028], [0029] and figs. 3-4, note that, the lower undercut region exposing sidewalls of portion 125 of the lower wiring pattern); and an upper undercut region between the dielectric layer 111 and the upper protection layer (upper element 40), the upper undercut region extending from the second opening (upper opening 41) to expose a sidewall of the upper wiring pattern (see paragraphs [0027], [0028], [0029] and figs. 3-4, note that, the upper undercut region exposing sidewalls of portion 125 of the upper wiring pattern).
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Chen is silent to wherein a width of the lower undercut region being less than a width of the lower wiring pattern.
However, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to optimize the width of the lower undercut region with respect to the width of the lower wiring pattern so that the width of the lower undercut region being less than the width of the lower wiring pattern since it is respectfully submitted that the configuration regarding about width of the lower undercut region and the width of the lower wiring pattern was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration was significant (In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966)). Furthermore, a change in size is generally recognized as being within the level of ordinary skill in the art. See In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955), Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), and MPEP 2144.04.
In re claim 11, as applied to claim 10 above, Chen is silent to wherein a width of the upper undercut region is less than a width of the upper wiring pattern.
However, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to optimize the width of the upper undercut region with respect to the width of the upper wiring pattern so that the width of the upper undercut region being less than the width of the upper wiring pattern since it is respectfully submitted that the configuration regarding about width of the upper undercut region and the width of the upper wiring pattern was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration was significant (In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966)). Furthermore, a change in size is generally recognized as being within the level of ordinary skill in the art. See In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955), Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), and MPEP 2144.04.
In re claim 12, as applied to claim 10 above, Chen discloses wherein the width of the lower undercut region gradually decreases in a direction toward the first opening from the sidewall of the lower wiring pattern (see paragraphs [0027], [0028] and fig. 3).
In re claim 13, as applied to claim 10 above, Chen is silent to wherein a portion of the lower protection layer facing the lower undercut region has a rounded sidewall.
However, it is respectfully submitted that the configuration regarding about shape of the portion of lower the protection layer was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration was significant (In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966)).
In re claim 14, as applied to claim 10 above, Chen discloses wherein the lower protection layer and the upper protection layer include a solder resist (see paragraphs [0025], [0026]).
Claim(s) 5 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (U.S. Pub. 2021/0392757), as applied to claims 1 and 10 above, respectively, and further in view of Aoki (U.S. Pub. 2019/0326224).
In re claim 5, as applied to claim 1 above, Chen is silent to wherein the wiring pattern has a same thickness as the conductive pad, and the wiring pattern includes a same material as the conductive pad.
However, Aoki discloses in a same field of endeavor, a package substrate, including, inter-alia, wherein the wiring pattern 32b has a same thickness as the conductive pad 32a, and the wiring pattern 32b includes a same material (copper) as the conductive pad 32a (see paragraph [0049] and figs. 1A-B).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the teaching as taught by Aoki into the package substrate of Chen in order to enable wherein the wiring pattern has a same thickness as the conductive pad, and the wiring pattern includes a same material as the conductive pad in Chen to be formed in order to improve the connection reliability between wiring patterns in the package substrate (see paragraph [0104] of Aoki).
In re claim 15, as applied to claim 10 above, Chen discloses wherein each of the lower wiring pattern and the upper wiring pattern includes copper (see paragraph [0043]) but is silent to wherein each of the lower conductive pad and the upper conductive pad includes copper.
However, Aoki discloses in a same field of endeavor, a package substrate, including, inter-alia, wherein each of the lower conductive pad, the upper conductive pad, the lower wiring pattern, and the upper wiring pattern includes copper (see paragraph [0049] and figs. 1A-B).
Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the teaching as taught by Aoki into the package substrate of Chen in order to enable wherein each of the lower conductive pad and the upper conductive pad includes copper in Chen to be formed since it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Allowable Subject Matter
Claims 18-20 are allowed over prior art of record.
Claims 8, 9, 16, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons For Allowance
The following is an examiner’s statement of reasons for allowance:
It is determined that the prior art of record neither anticipates nor renders obvious the claimed subject matter of independent claim 18 as a whole taken alone or in combination, in particular, prior art of record does not teach “a molding layer on the package substrate, the molding layer covering the semiconductor chip, a lower plating patterns on the lower conductive pads, upper plating patterns on the upper conductive pads", as recited in independent claim 18.
Claims 19 and 20 also allowed as being directly or indirectly dependent of the allowed independent base claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kitajo et al. (U.S. Pub. 2019/0230791) discloses a package substrate 10 (see paragraph [0026] and fig. 1A), comprising: a dielectric layer (41,43) (see paragraph [0031] and fig. 1A); a conductive pad P2 and a wiring pattern 44 on the dielectric layer (41,43) (see paragraph [0035] and fig. 1A); and a protection layer 60 on the dielectric layer (41,43), the protection layer 60 covering the wiring pattern 44 (see paragraph [0035] and fig. 1A).
Ueda et al. (U.S. Pub. 2009/0236135) discloses a package substrate 10 (see paragraph [0022] and fig. 1), comprising: a dielectric layer (12,13) (see paragraph [0023] and fig. 1); a conductive pad 20 and a wiring pattern 18 on the dielectric layer (12,13) (see paragraph [0025] and fig. 1); and a protection layer 21 on the dielectric layer (12,13) (see paragraph [0026] and fig. 1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)272-1865. The examiner can normally be reached Monday-Friday 8:00 AM - 6:00 PM.
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/KHIEM D NGUYEN/Primary Examiner, Art Unit 2892