DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 09/16/2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 6-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hu et al. (U.S. Publication No. 2021/0005760 A1; hereinafter Hu)
With respect to claim 1, Hu discloses an electronic device, comprising: a semiconductor substrate [102] and a semiconductor surface layer [108] having a first conductivity type [P-type], the semiconductor surface layer over the semiconductor substrate and having a top surface; a buried layer [104] having an opposite second conductivity type [N-type] between the semiconductor surface layer and the semiconductor substrate; a deep trench structure [120], including: a trench [121] that extends through the semiconductor surface layer and into the buried layer, a dielectric liner [123,124,125] on a sidewall of the trench from the semiconductor surface layer to the buried layer, and polysilicon [126] that extends on the dielectric liner and fills the trench to the side of the semiconductor surface layer; and a shallow trench isolation [118] structure that extends into the semiconductor surface layer (See Figure 1), the shallow trench isolation structure in contact with the deep trench structure (See Figure 16).
With respect to claim 2, Hu discloses a deep doped region [122] having the second conductivity type, the deep doped region extending from the semiconductor surface layer to the buried layer (See Figure 1).
With respect to claim 3, Hu discloses wherein the deep doped region surrounds the trench at a top surface of the semiconductor surface layer (see Figure 1).
With respect to claim 4, Hu discloses wherein the polysilicon has the first conductivity type (See Figure 1).
With respect to claim 6, Hu discloses wherein the trench extends through the buried layer and into the semiconductor substrate under the buried layer (see Figure 1).
With respect to claim 7, Hu discloses wherein the polysilicon has the first conductivity type (See Figure 1).
With respect to claim 8, Hu discloses wherein the trench extends through the buried layer and into the semiconductor substrate under the buried layer (see Figure 1).
With respect to claim 9, Hu discloses wherein the trench extends through the shallow trench isolation structure (See ¶[0016]).
With respect to claim 10, Hu discloses a transistor [101] in or over the semiconductor surface layer and spaced apart from the deep trench structure (See Figure 1).
With respect to claim 11, Hu discloses wherein the semiconductor surface layer has the first conductivity type (See Figure 1).
With respect to claim 12, Hu discloses an electronic device, comprising: a semiconductor substrate [102] having a first conductivity type [p-type]; a semiconductor surface layer [108] over the semiconductor substrate and having the first conductivity type; a buried layer [104] having an opposite second conductivity type between the semiconductor surface layer and the semiconductor substrate; a shallow trench isolation structure [118] that extends into the semiconductor surface layer; and a deep trench structure [120] that extends through the shallow trench isolation structure, through the semiconductor surface layer, and into the buried layer, a top surface of the deep trench structure extending above a top surface of the shallow trench isolation structure (See Figure 1).
With respect to claim 13, Hu discloses a deep doped region [122] that extends from the semiconductor surface layer to the buried layer.
With respect to claim 14, Hu discloses wherein the deep doped region surrounds the deep trench structure at a top surface of the semiconductor surface layer (see Figure 1).
With respect to claim 15, Hu discloses wherein the deep trench structure extends through the buried layer and into the semiconductor substrate under the buried layer (See Figure 1).
With respect to claim 16, Hu discloses wherein the deep trench structure comprises: a trench [121] through the semiconductor surface layer and into the buried layer; a dielectric liner [123,124,125] on a sidewall of the trench from the semiconductor surface layer to the buried layer; and polysilicon [126] that extends on the dielectric liner and fills the trench to the side of the semiconductor surface layer (see Figure 1).
Claim(s) 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cai (U.S. Publication No. 2016/0043217 A1)
With respect to claim 17, Cai discloses a method of fabricating an electronic device, the method comprising: forming a shallow trench isolation structure [752] that extends into a semiconductor surface layer [722] (see ¶[0033]; Figures 6-7); and forming a deep trench structure [754,756,758] through the shallow trench isolation structure, through the semiconductor surface layer, and into a buried layer [714] (see Figure 7 and ¶[0035]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu in view of Pendharkar et al. (U.S. Patent No. 9,431,286 B1; hereinafter Pendharkar)
With respect to claim 5, Hu discloses wherein the trench extends through the buried layer and into the semiconductor substrate under the buried layer, (see Figure 1) but fails to disclose the polysilicon is connected to the semiconductor substrate by an implanted contact at a bottom of the trench, however does disclose alternative methods of connection (see ¶[0022]). In the same field of endeavor, Pendharkar teaches a deep trench wherein the polysilicon [660,662] is connected to the semiconductor substrate by an implanted contact [658] at a bottom of the trench (see Figure 6). Implementation of implanted contacts for the deep trench structures, as taught by Pendharkar within the trench structure of Hu allows for alternative connections to those disclosed by Hu (see Pendharkar Column 8, lines 5-22). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Aghoram et al. (U.S. Publication No. 2019/0103471 A1) discloses an LDMOS with deep trench structures.
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/JONATHAN HAN/Primary Examiner, Art Unit 2818