DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
Applicant's amendment to the claims, filed on September 16th, 2025, is acknowledged. Entry of amendment is accepted and made of record.
Response to Arguments/Remarks
Applicant's response filed on September 16th, 2025 is acknowledged and isanswered as follows.
Applicant's arguments, see pgs. 6-7, with respect to the rejections of claims under 35 U.S.C 102 (a)(1) and/or 35 U.S.C 103(a) have been considered but are moot in view of the new ground(s) of rejection.
Claim Objections
Claim 13 is objected to because of the following informalities: claim 13 recites “a trench through the dielectric isolation structure” in line 4 which missing an action verb and should be amended to “a trench extends through the dielectric isolation structure” for avoiding confusion. Appropriate correction is required.
Claim 22 is objected to under 37 CFR 1.75 as being a substantial duplicate of claim 12. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 8 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over OTSUBO et al. (Pub. No.: US 2020/0403072 A1), hereinafter as Otsubo in view of MUN et al. (Pub. No.: US 2022/0384588 A1), hereinafter as Mun.
Regarding claim 1, Otsubo discloses an electronic device in Figs. 1-3, comprising: a semiconductor substrate (substrate 5 and 1) and a semiconductor surface layer (second semiconductor layer 2) having a first conductivity type (n type), the semiconductor surface layer over the semiconductor substrate and having a top surface (top surface of layer 2) (see Fig. 2 and [0028], [0031]); a buried layer (layer 3) having an opposite second conductivity type (p type) between the semiconductor surface layer and the semiconductor substrate (see [0031-0032]); a dielectric isolation layer (isolation portion 19) that extends over and into the semiconductor surface layer (see Fig. 2 and [0039]); a deep trench structure (left buried electrode 59) that extends through the dielectric isolation layer into the semiconductor surface layer (see Fig. 2 and [0047]); a dielectric layer (insulating film 30) that extends between the top surface of the deep trench structure and conductive routing structures (source electrodes 34s, 35s and 36s, drain electrodes 34d, 35d and 36d, and electrodes 37) (see Fig. 2 and [0048], [0060]).
Otsubo fails to disclose a silicide blocking layer under the dielectric layer and on the top surface of a deep trench structure.
Mun discloses an electronic device in Fig. 9A comprising a silicide blocking layer (passivation liner 118) under a dielectric layer (IMD layer 17) and on a top surface of a deep trench structure (deep trench 216 and/or isolation structure 128) (see [0034], [0037], [0067] and [0071]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the silicide blocking layer of Mun into the electronic device of Otsubo for being under the dielectric layer and on the top surface of the deep trench structure because the modified structure would enhance device reliability, stability and performance by having the passivation liner as barrier protection from moisture and residues and further reducing defect between interlayer dielectric and semiconductor layer surface.
Regarding claim 2, the combination of Otsubo and Mun discloses he electronic device of claim 1, wherein the top surface is higher than a top side of the semiconductor surface layer (semiconductor layer 2) (see Fig. 2 of Otsubo).
Regarding claim 3, the combination of Otsubo and Mun discloses he electronic device of claim 1, wherein the silicide blocking layer (passivation liner 118) extends over a polysilicon core of the deep trench structure (see Fig. 9A of Mun).
Regarding claim 4, the combination of Otsubo and Mun discloses he electronic device of claim 1, wherein the deep trench structure extends through the buried layer and touches the semiconductor substrate (extends through layer 3 and touches layer 1) (see Fig. 2 of Otsubo).
Regarding claim 8, the combination of Otsubo and Mun discloses he electronic device of claim 1, wherein: the deep trench structure includes a trench (trench 56 of the left isolation structure 8 in Fig. 3 of Otsubo) through the semiconductor surface layer and into the buried layer (see Otsubo and [0056]), a dielectric liner (insulating film 58) on a sidewall of the trench from the semiconductor surface layer to the buried layer, and polysilicon (buried electrode 59 includes doped polysilicon) that extends on the dielectric liner and fills the trench (see Fig. 2-3 and [0057] of Otsubo); and the silicide blocking layer (passivation liner 118 of Mun being incorporated into Fig. 2-3 of Otsubo) covers the dielectric liner of the deep trench structure (cover insulating film 58 in the top view) and does not cover a portion of the polysilicon of the deep trench structure (not covering a portion of an upper surface of buried electrode 59 that having the metal plug 32 formed there) (see Fig. 1 of Salman, [0020] and Fig. 9A of Mun).
Regarding claim 10, the combination of Otsubo and Mun discloses he electronic device of claim 1, wherein: the deep trench structure includes a trench (trench 56 of the left isolation structure 8 in Fig. 3 of Otsubo) through the semiconductor surface layer and into the buried layer (see Otsubo and [0056]), a dielectric liner (insulating film 58) on a sidewall of the trench from the semiconductor surface layer to the buried layer, and polysilicon (buried electrode 59 includes doped polysilicon) that extends on the dielectric liner and fills the trench (see Fig. 3 and [0057] of Otsubo); and the silicide blocking layer (passivation liner 118 of Mun being incorporated into Fig. 2-3 of Otsubo) covers the dielectric liner of the deep trench structure and covers the polysilicon of the deep trench structure (cover in the top view) (see Fig. 9A of Mun and Figs. 2-3 of Otsubo).
Regarding claim 11, the combination of Otsubo and Mun discloses he electronic device of claim 1, wherein the dielectric isolation layer is a shallow trench isolation layer (STI structure 51/isolation portion 19) (see Otsubo, Figs. 2-3 and [0052]).
Claims 6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over OTSUBO et al. (Pub. No.: US 2020/0403072 A1), hereinafter as Otsubo in view of MUN et al. (Pub. No.: US 2022/0384588 A1), hereinafter as Mun, as applied to claims 1 and 8 above, and further in view of Salman et al. (Pub. No.: US 2020/0328204 A1), hereinafter as Salman.
Regarding claim 6, the combination of Otsubo and Mun discloses the electronic device of claim 1, wherein the deep trench structure is a first deep trench structure having a first polysilicon core (left buried electrode 59 of Otsubo in Fig. 2) and the silicide blocking layer is a first silicide blocking layer (one portion of passivation liner 118 of Mun in Fig. 9A), and further comprising a second deep trench structure having a second polysilicon core (middle buried electrode 59 of Otsubo in Fig. 2) and a second silicide blocking layer (another portion of passivation liner 118 in Fig. 9A).
But Otsubo fails to disclose wherein: a metal silicide layer covers the first polysilicon core.
Salman discloses an electronic device in Fig. 1 comprising a deep trench structure (deep trench structure 122/region 131) that extends through a dielectric isolation layer (isolation structures 126) into a semiconductor surface layer (layer 110), a metal silicide layer (silicide not shown) covers the first polysilicon core (top surface of DT 122) (see [0019-0025]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the p doping region and the metal silicide on the top surface of the deep trench structure because the modified structure would provide reduce contact resistance for making a good ohmic contact for reducing power consumption.
Regarding claim 9, the combination of Otsubo and Mun discloses he electronic device of claim 8, and a metal contact (metal plug 32) on the portion of the polysilicon of the deep trench structure (see Otsubo, Fig. 2 and [0047]).
But Otsubo fails to disclose the metal contact contacts a metal silicide on the portion of the polysilicon of the deep trench structure (see Otsubo, Fig. 2 and [0047]).
Salman discloses an electronic device in Fig. 1 comprising a deep trench structure (deep trench structure 122/region 131) that extends through a dielectric isolation layer (isolation structures 126) into a semiconductor surface layer (layer 110); a metal silicide layer (silicide not shown) on the portion of polysilicon of the deep trench structure (top surface of layer 131/ DT 122) (see [0019-0025]); a metal contact (contacts 132) that contacts the metal silicide on the portion of the polysilicon of the deep trench structure (see [0019-0025]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the p doping region and the metal silicide on the top surface of the deep trench structure because the modified structure would provide reduce contact resistance for making a good ohmic contact for reducing power consumption.
Claims 7, 12, 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over OTSUBO et al. (Pub. No.: US 2020/0403072 A1), hereinafter as Otsubo in view of MUN et al. (Pub. No.: US 2022/0384588 A1), hereinafter as Mun, as applied to claim 1 above, and further in view of Park et al. (Pub. No.: US 2012/0104514 A1), hereinafter as Park.
Regarding claim 7, the combination of Otsubo and Mun discloses the electronic device of claim 1, but fails to disclose the silicide blocking layer includes nitrogen.
Park discloses an electronic device in Fig. 1 comprising a silicide blocking layer (insulating layer 143) includes nitrogen (silicon nitride) (see [0029] and [0043]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the material of the silicide blocking layer of Park for making the silicide blocking layer of Otsubo and Mun includes nitrogen because the disclosure of Park showing silicon nitride can be material choice of manufacturing desire for effectively forming passivation liner and/or insulating protection for the electronic device from moisture and reduce device defects.
Regarding claim 12, the combination of Otsubo and Mun discloses the electronic device of claim 1, but fails to disclose wherein the silicide blocking layer includes a nitrogen-containing dielectric material.
Park discloses an electronic device in Fig. 1 comprising a silicide blocking layer (insulating layer 143) includes a nitrogen-containing dielectric material (silicon nitride) (see [0029] and [0043]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the material of the silicide blocking layer of Park for making the silicide blocking layer of Otsubo and Mun includes nitrogen-containing dielectric material because the disclosure of Park showing silicon nitride can be material choice of manufacturing desire for effectively forming passivation liner and/or insulating protection for the electronic device from moisture and reduce device defects.
Regarding claim 21, the combination of Otsubo and Mun discloses the electronic device of claim 1, but fails to disclose wherein the silicide blocking layer is a thermally grown silicon oxide layer.
Park discloses an electronic device in Fig. 1 comprising a silicide blocking layer (insulating layer 143) is silicon oxide layer (silicon oxide) (see [0029] and [0043]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the silicon oxide material of the silicide blocking layer of Park for making the silicide blocking layer of Otsubo and Mun because the disclosure of Park showing silicon oxide can be material choice of manufacturing desire for effectively forming passivation liner and/or insulating protection for the electronic device from moisture and reduce device defects.
The combination of Otsubo, Mun and Park fails to disclose the silicon oxide layer is thermally grown. However, it should be known that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Since claim 21 is directed to a device, the method of forming silicon oxide is not germane to the issue of patentability of the device itself. Therefore, the limitation of “…thermally grown” stated in claim 21 has not been given any patentable weight. MPEP 2113 [R-1].
Regarding claim 22, the combination of Otsubo and Mun discloses the electronic device of claim 1, but fails to disclose wherein the silicide blocking layer comprises a nitrogen-containing dielectric material.
Park discloses an electronic device in Fig. 1 comprising a silicide blocking layer (insulating layer 143) comprises a nitrogen-containing dielectric material (silicon nitride) (see [0029] and [0043]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the material of the silicide blocking layer of Park for making the silicide blocking layer of Otsubo and Mun includes nitrogen-containing dielectric material because the disclosure of Park showing silicon nitride can be material choice of manufacturing desire for effectively forming passivation liner and/or insulating protection for the electronic device from moisture and reduce device defects.
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for the indication of allowable subject matter: the prior art made of record does not teach or fairly suggest the following: wherein the deep trench structure is a first deep trench structure and further comprising a second deep trench structure that extends through the dielectric isolation layer and into the buried layer, wherein the first deep trench structure includes a first polysilicon core that touches the semiconductor substrate and the second deep trench structure includes a second polysilicon core that is conductively isolated from the semiconductor substrate as recited in claim 5.
Claims 13-15 and 23-24 will be allowed over prior art of record if claim 13 rewritten and/or amend to overcome the objection as set forth in the office action above.
The following is an examiner' s statement of reason for allowance: the prior art made of record does not teach or fairly suggest the following: a trench through the dielectric isolation structure and having a sidewall along within the semiconductor surface layer and the dielectric isolation layer, a pre-metal dielectric (PMD) layer that extends between a conductive routing structure and the dielectric isolation structure as recited in claim 13; and a second deep trench structure that extends through the dielectric isolation layer, into the buried layer, and is conductively isolated from the semiconductor substrate; and a silicide blocking layer on a top surface of the first and second deep trench structures as recited in claim 24. Claims 14-15, and 23, depend on claim 13, and therefore also include said claimed limitation.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000
/CUONG B NGUYEN/Primary Examiner, Art Unit 2818