DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Amendment filed December 19, 2025 is acknowledged. Claims 8 and 20 have been cancelled. Claim 1 has been amended. Claims 1, 4-5, 9-10 and 12-19 are pending.
Action on merits of claims 1, 4-5, 9-10 and 12-19 follows.
Claim Objections
Amended Claim 1 is objected to because of the following informalities:
The current amendment underlined some of the previously amended limitations of independent Claim 1.
Some of the ions species such as “phosphorus (P) and aluminum (Al)” were deleted, and does not include in the current amendment as removed limitation(s), i.e., crossed out.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1, 4-5, 9-10 and 12-19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There does not appear to be a written description of the claim limitation “wherein an ion implantation dose of the ion implantation step is between 1013 cm-2 and 1016 cm-2” (amended claim 1) (emphasis added) in the application as filed.
Applicant must cancel the un-support new matters in response to the Office Action.
Although “1013 cm-2 ” is a value within 1012 cm-2 and 1016 cm-2, however, the inventors does not specifically possesses the claimed range of “1013 cm-2 and 1016 cm-2”.
By eliminate the starting range of “1012 cm-2” and replacing it with the currently claim range of “1013 cm-2 and 1016 cm-2” the Applicant has inject new matter into the claims, in which the inventors, at the time the application was filed, do not have possession of the claimed invention.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 4, 9-10, 12, 14-15 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over KOYAMA et al. (US. Pub. No. 2019/0237548) in view of BALIGA et al. (US. Patent No. 5,436,174) both of record.
With respect to claim 1, As best understood by the Examiner, KOYAMA teaches a method for stabilizing breakdown voltages of floating guard ring (5), which is applicable to a high power device including a semiconductor substrate layer (2) made of a wide bandgap semiconductor material (SiC), wherein the high power device is selected from a group consisting of a Vertical Double Diffused Metal Oxide Semiconductor Field Effect Transistor (VDMOSFET) and an Insulated Gate Bipolar Transistor (IGBT), and at least one floating guard ring (5) is formed at a termination (RT) of the high power device, as claimed, the method comprising:
forming a hard mask (not shown) on an upper surface of the high power device, such that the hard mask covers an active region (RE) of the high power device without covering the termination (RT) where the at least one floating guard ring (5) is formed so as to expose the at least one floating guard ring (5);
performing an ion implantation step (S30), which encompasses the termination (RT) where the at least one floating guard ring (5) is formed, wherein the ion implantation step is performed by a pre-amorphization implant (PAI) process, and the ion implantation step is performed by using ions such as helium or hydrogen, so the ion implantation step turns the semiconductor substrate layer (2) into an amorphous state, and wherein an ion implantation dose of the ion implantation step is between 1012 cm-2 and 1013 cm-2;
removing the hard mask and forming a field oxide layer (7a), wherein the field oxide layer (7a) is formed by a thermal oxidation process and such that a defect layer (63) is formed underneath the field oxide layer (7a), and a defect density of the defect layer (63) is between 1013 cm-3 and 1016 cm-3; and
fixing an interface potential level between the field oxide layer (7a) and the semiconductor substrate layer (2) at a certain potential value by employing the defect layer (63) (See FIGs. 13, 17, 20, 22, 39, 41).
Regarding the limitation: “fixing an interface potential level between the field oxide layer and the semiconductor substrate layer at a certain potential value”, the “fixing an interface potential level …” is a direct result of “employing the defect layer being formed by ion implantation”.
Since the high power device of KOYAMA being formed with the defect layer (63) between the field oxide layer and the semiconductor substrate layer, the limitation is met.
Regarding the limitation: “wherein an ion implantation dose of the ion implantation step is between 1013 cm-2 and 1016 cm-2”, the implantation dose of KOYAMA ‘548 is in the range of 1012 cm-2 and 1013 cm-2 , thus meet the alleged low end of the claimed range of “1013 cm-2 ”.
It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
Thus, KOYAMA is shown to teach all the features of the claim with the exception of explicitly disclosing the ion implantation step is performed by using ions such as argon (Ar), xenon (Xe), silicon (Si), or oxygen (O).
However, BALIGA teaches a method including:
forming a hard mask (12) on an upper surface of a high power device;
performing an ion implantation step, wherein the ion implantation step is performed by a pre-amorphization implant (PAI) process, and the ion implantation step is performed by using ions (14) such as helium, hydrogen, argon, silicon, or other ions, so the ion implantation step turns the semiconductor substrate layer (11) into an amorphous state (11b), and wherein an ion implantation dose of the ion implantation step is 1015 cm-2 . (See Summary of the Invention; FIGs. 1A-C, EXAMPLE).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the defect layer of KOYAMA utilizing the ions such as argon, silicon, or other ions, beside hydrogen or helium, as taught by BALIGA for the same intended purpose of turning the semiconductor substrate layer into the amorphous state and forming the defect layer under the field oxide layer.
Moreover, given a finite number of materials and their compounds, it is obvious to try without undue experimentation.
Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416., 125 USPQ 416.
Regarding the limitation: “wherein the field oxide layer is formed by a thermal oxidation process and such that a defect layer is formed underneath the field oxide layer, and a defect density of the defect layer is between 1013 cm-3 and 1016 cm-3 ”, the defect density of “1013 cm-3 to 1016 cm-3 ” is a direct result of ion implantation of the ions with the implanting dose of between 1013 cm-2 and 1016 cm-2.
Although KOYAMA and BALIGA do not disclose the defect density of the defect layer, however, KOYAMA and BALIGA explicitly disclosing the doping dose of the ion implantation that turns the semiconductor substrate layer into the amorphous state being in the range of 1012 cm-2 and 1013 cm-2 by KOYAMA and 1015 cm-2 by BALIGA.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the defect density of the defect layer of KOYAMA in the range of 1013 cm-3 and 1016 cm-3 by implanting the ion with the implanting dose of 1012 cm-2 and 1013 cm-2; or 1015 cm-2 by BALIGA. Same process same result.
With respect to claim 4, a process temperature of the thermal oxidation process of KOYAMA is between 1000 and 1200 Celsius degrees, thus, within the claimed range of 1000 to 1300 °C.
With respect to claim 9, an ion implantation energy of the ion implantation step (S30) of KOYAMA is between 30 keV and 700 keV, thus within the claimed range of 10 keV and 1000 keV.
With respect to claim 10, the wide bandgap semiconductor material of KOYAMA comprises silicon carbide (SiC), gallium oxide (Ga2O3), aluminum nitride (AlN), and diamond.
With respect to claim 12, the hard mask (not shown) of KOYAMA comprises a barrier layer, which is made of silicon nitride (Si3N4), silicon dioxide (SiO2) or a material that can be selectively removed from the wide bandgap semiconductor material.
With respect to claim 14, a thickness of the defect layer of KOYAMA is between 200 nm and 1 µm or less, or 400 nm by BALIGA, thus, overlaps the range of 50 and 500 nm.
It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
With respect to claim 15, after the defect layer is formed, the method of KOYAMA further comprising: forming a gate oxide layer (21) on the active region of the high power device; forming a gate conductive layer (20) on the gate oxide layer (21) and further depositing a dielectric layer (17) on the gate conductive layer (20); and forming at least one contact window (18) which extends through the dielectric layer (17) and the gate oxide layer, and electrically connected to the semiconductor substrate layer of the high power device for providing electrical paths. (See FIG. 35).
With respect to claim 17, the semiconductor substrate layer (2) of the high power device of KOYAMA comprises an N-type semiconductor substrate (1), an N-type epitaxial layer (2), a first N-type heavily doped region (14), a second N-type heavily doped region (14), a first P- type heavily doped region (13), a second P-type heavily doped region (13), a first P-type body region (11), and a second P-type body region (11), the N-type epitaxial layer (2) is disposed on the N-type semiconductor substrate (1), the first P-type body region (11) and the second P-type body region (11) are formed in the N-type epitaxial layer (2), the first P-type heavily doped region (13) is disposed on one side of the first N-type heavily doped region (14), and the first P-type heavily doped region (13) and the first N-type heavily doped region (14) are commonly disposed in the first P-type body region (11), the second P-type heavily doped region (13) is disposed on one side of the second N-type heavily doped region (14), and the second P-type heavily doped region (13) and the second N-type heavily doped region (14) are commonly disposed in the second P-type body region (11).
With respect to claim 18, the first N-type heavily doped region (14) and the second N-type heavily doped region (14) of KOYAMA are formed by using a source ion implantation in the N-type epitaxial layer (2).
With respect to claim 19, the N-type semiconductor substrate of KOYAMA is an N-type silicon carbide (SiC) substrate.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over KOYAMA ‘548 and BALIGA’ 174, as applied to claim 1 above, and further in view of DAS et al. (US. Patent No. 6,972,436) of record.
KOYAMA, in view of BALIGA, teaches the method as described in claim 1 above including the field oxide layer is formed by thermal oxidation process.
Thus, KOYAMA is shown to teach all the features of the claim with the exception of explicitly disclosing the duration of the thermal oxidation process.
However DAS teaches a method for growing a layer of oxide may be carry out for a process time from 15 minutes to about 3 hours or longer.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the field oxide layer of KOYAMA by thermal oxidation process duration as taught by DAS to achieve the desire thickness.
Note that, the duration of the thermal oxidation process depends on the desire thickness.
Claims 13 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over KOYAMA ‘548 and BALIGA ‘174 as applied to claims 12 and 15 above, and further in view of TAMAKI et al. (US. Pub. No. 2016/0190235) of record.
With respect to claim 13, KOYAMA, in view of BALIGA, teaches the method as described in claim 12 above including the hard mask comprises a barrier layer, which is made of silicon nitride (Si3N4), silicon dioxide (SiO2) or a material that can be selectively removed from the wide bandgap semiconductor material.
Thus, KOYAMA and BALIGA are shown to teach all the features of the claim with the exception of explicitly disclosing the hard mask further comprising a pad oxide layer which is configured between the barrier layer and the upper surface of the high power device.
However, TAMAKI teaches a method including: a hard mask comprises a barrier layer, which is made of silicon nitride (Si3N4), silicon dioxide (SiO2) or a material that can be selectively removed from wide bandgap semiconductor material (1),
wherein the hard mask further comprising a pad oxide layer (16) which is configured between the barrier layer (26) and the upper surface of the high power device, the pad oxide layer (16) is made of silicon dioxide (SiO2), and the barrier layer (25) is further made of another material that can be selectively removed from the pad oxide layer. (See FIG. 15).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the hard mask of KOYAMA including the pad oxide and the barrier layer as taught by TAMAKI for the same intended purpose of blocking the selected regions from ions implantation.
Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416., 125 USPQ 416.
With respect to claim 16, in the step of forming the gate conductive layer (20) of KOYAMA, further comprising: using a chemical vapor deposition (CVD) process to deposit a polysilicon (20); and using an etch back process to etch back the polysilicon (20), so as to form the gate conductive layer (20).
In view of TAMAKI, using LPCVD process to deposit polysilicon (11) is well known in the art. (See FIG. 19).
Response to Arguments
Applicant's arguments filed December 19, 2025 have been fully considered but they are not persuasive.
Applicant asserts: “According to the currently amended Claim 1, it is believed that a thermal oxidation process is used to form the field oxide layer (303) first”.
However, this statement is counter intuitive. Under the thermal oxidation, every element within the substrate is simultaneously affected.
Applicant asserts:
And subsequently, referring to Fig. 3F of the present invention, it should be apparent that a layer damaged by the aforementioned ion implantation (that is, the ion implantation step is being performed by using ions such as argon (Ar), xenon (Xe), silicon (Si), or oxygen (O)) will be effectively formed underneath the formed field oxide layer (303). And, since the substrate layer (for instance, the SiC layer) has not turned into an amorphous state and thus will not grow into silicon dioxide, it is believed that the damages which had been generated due to the foregoing pre-ion implantation step, will not be completely healed by the high temperature in the process when forming the field oxide layer in a thermal oxidation process. As a result, it can be obtained that a defect laver (308) can be effectively formed underneath the field oxide layer (303) as illustrated in Fig. 3F. (Emphasis added).
Applicant has removed two ions species, phosphorus (P) and aluminum (Al) previously claimed. As previously discussed, all ions implanted into a substrate would inherently amorphized the substrate’ surface or turns the substrate’ surface into an amorphous state.
Upon the thermal oxidation, at 1000 °C to 1300 °C (claim 4) and duration 1 to 24 hours (claim 5), the amorphized surface would have easily oxidized into field oxide. This is the facts.
As shown in FIG. 20, KOYAMA clearly shows that the defect layer 63 exists and being formed under the field oxide layer.
Applicant statement “since the substrate layer (for instance, the SiC layer) has not turned into an amorphous state” is incorrect.
Claim 1 explicitly claimed “so the ions implantation step turns the semiconductor substrate layer into an amorphous state”.
Regarding the amended implantation dose of “1013 cm-2 and 1016 cm-2”, as indicated in the objection above, Applicant intentionally removed the dose of 1012 cm-2 as previously claimed. There is no support for this limitation.
The specification explicitly discloses the effective dose of “1012 cm-2 and 1016 cm-2” not “1013 cm-2 and 1016 cm-2”.
KOYAMA, explicitly teaches the damage region 63 being formed with the dose in the range of “1012 cm-2 and 1013 cm-2”, at the implantation energy of 30 keV and 700 keV, which is within the range of “10 keV and 1000 keV” (claim 9).
Again, FIG. 20 of KOYAMA, clearly shows the defect layer 63 being formed under the field oxide.
Applicant, however, fails to provide any evidence that the method and the resulting structure of KOYAMA does not function as claimed: “fixing an interface potential level between the field oxide layer and the semiconductor substrate layer at a certain potential value by employing the defect layer”
The claimed method is nothing more than “cause and effect”. The cause: “such that a defect layer is formed underneath the field oxide layer” and the effect “fixing an interface potential level between the field oxide layer and the semiconductor substrate layer at a certain potential value by employing the defect layer”.
KOYAMA explicitly teaching the cause, therefore, implicitly teaching the effect.
The remaining argument directed to the subject matters that do not claimed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Email: Anh.Mai2@uspto.gov). The examiner can normally be reached 10:00-4:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue A Purvis can be reached on 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANH D MAI/Primary Examiner, Art Unit 2893
Prosecution Insights