DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 27, 2026 has been entered.
Status of the Claims
Amendment filed May 27, 2026 is acknowledged. Claim 1 has been amended. Claims 1, 4-5, 9-10 and 12-19 are pending.
Action on merits of claims 1, 4-5, 9-10 and 12-19 follows.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1, 4-5, 9-10 and 12-19 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There does not appear to be a written description of the claim limitation “the ion implantation step is performed by using non-halogen ions such as … (amended claim 1) (emphasis added) in the application as filed.
Applicant must cancel the un-support new matters in response to the Office Action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 4-5, 9-10 and 12-19 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “the ion implantation step is performed by using non-halogen ions such as …” is a negative limitation that rendered the claim indefinite because it was an attempt to claim the invention by excluding what the inventor did not invent rather than distinctly and particularly pointing out what they did invent. See In re Schechter, 205 F.2d 185, 98 USPQ 144 (CCPA 1953). (See MPEP 2173.05(i)). Any negative limitation or exclusionary proviso must have basis in the original disclosure. See In re Johnson, 558 F.2d 1008, 1019, 194 USPQ 187, 196 (CCPA 1977).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 4, 9-10, 12, 14-15 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over KOYAMA et al. (US. Pub. No. 2019/0237548) in view of BALIGA et al. (US. Patent No. 5,436,174) both of record.
With respect to claim 1, As best understood by the Examiner, KOYAMA teaches a method for stabilizing breakdown voltages of floating guard ring, which is applicable to a high power device including a semiconductor substrate layer () made of a wide bandgap semiconductor material, wherein the high power device is selected from a group consisting of a Vertical Double Diffused Metal Oxide Semiconductor Field Effect Transistor (VDMOSFET) and an Insulated Gate Bipolar Transistor (IGBT), and at least one floating guard ring (5) is formed at a termination (RT) of the high power device, as claimed, the method comprising:
forming a hard mask (not shown) on an upper surface of the high power device, such that the hard mask covers an active region (RE) of the high power device without covering the termination (RT) where the at least one floating guard ring (5) is formed so as to expose the at least one floating guard ring;
performing an ion implantation step (S30), which encompasses the termination (RT) where the at least one floating guard ring (5) is formed, wherein the ion implantation step is performed by a pre- amorphization implant (PAI) process, and the ion implantation step is performed by using ions to generate a physical lattice damage, so the ion implantation step turns the semiconductor substrate layer into an amorphous state, and wherein an ion implantation dose of the ion implantation step is between 1012 cm-2 or more;
removing the hard mask (not shown) and forming a field oxide layer (7a), wherein the field oxide layer (7a) is formed by a thermal oxidation process (S41) and a defect layer (5h, 61) is formed underneath the field oxide layer (7a), wherein the defect layer formed by the physical lattice damage is substantially retained underneath the field oxide layer after the thermal oxidation process without being completely removed, and a defect density of the defect layer is between 1013cm-3 and 1016 cm-3; and
fixing an interface potential level between the field oxide layer and the semiconductor substrate layer at a certain potential value by employing the defect layer. (See FIGs. 13, 17, 20, 22, 39, 41).
Regarding the limitation: “the ion implantation step is performed by using ions … to generate a physical lattice damage, so the ion implantation step turns the semiconductor substrate layer into an amorphous state”, the ions (all ions species) implantation is inherently, well-known in the art, caused physical lattice damage or turn the substrate layer into amorphous state, hence pre-amorphization. Thus, the limitation is met.
Regarding the limitation: “wherein the defect layer formed by the physical lattice damage is substantially retained underneath the field oxide layer after the thermal oxidation process without being completely removed”, KOYAMA ‘548, [0093], teaches: “It should be noted that, in Embodiment 4, the heat treatment for forming the thermal oxide film 7a does not serve as a step of recovering damaged crystallinity attributed to ion implantation of the halogen family atoms”. Thus, the limitation is met.
Regarding the limitation: “a defect density of the defect layer is between 1013 cm-3 and 1016 cm-3”, the defect density is a direct result of the implantation dose of 1012 cm-2 and 1016cm-2 , since the ions implantation dose of KOYAMA ‘548 is in the range of 1012 cm-2 or more, within the claimed range, thus, the limitation is met.
It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
Regarding the limitation: “fixing an interface potential level between the field oxide layer and the semiconductor substrate layer at a certain potential value”, the “fixing an interface potential level …” is a direct result of “employing the defect layer being formed by ion implantation”.
Since the high power device of KOYAMA being formed with the defect layer between the field oxide layer and the semiconductor substrate layer, the limitation is met.
Thus, KOYAMA is shown to teach all the features of the claim with the exception of explicitly disclosing the ion implantation step is performed by using non-halogen ions such as argon (Ar), xenon (Xe), silicon (Si), or oxygen (O).
However, BALIGA teaches a method including:
to generate a physical lattice damage, performing an ion implantation step, wherein the ion implantation step is performed by a pre-amorphization implant (PAI) process, and the ion implantation step is performed by using non-halogen ions (14) such as helium, hydrogen, argon, silicon, or other ions, so the ion implantation step turns the semiconductor substrate layer (11) into an amorphous state (11b), and wherein an ion implantation dose of the ion implantation step is 1015 cm-2 . (See Summary of the Invention; FIGs. 1A-C, EXAMPLE).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to perform the ion implantation step of KOYAMA to generate the physical lattice damage utilizing the non-halogen ions such as argon, silicon, or other ions, as taught by BALIGA for the same intended purpose of turning the semiconductor substrate layer into the amorphous state and forming the defect layer under the field oxide layer.
Moreover, given a finite number of materials and their compounds, it is obvious to try without undue experimentation.
Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416., 125 USPQ 416.
Regarding the limitation: “wherein the field oxide layer is formed by a thermal oxidation process and such that a defect layer is formed underneath the field oxide layer, and a defect density of the defect layer is between 1012 cm-3 and 1016 cm-3 ”, the defect density of “1013 cm-3 to 1016 cm-3 ” is a direct result of ion implantation of the ions with the implanting dose of between 1013 cm-2 and 1016 cm-2.
Although KOYAMA and BALIGA do not disclose the defect density of the defect layer, however, KOYAMA and BALIGA explicitly disclosing the doping dose of the ion implantation that turns the semiconductor substrate layer into the amorphous state being in the range of 1012 cm-2 or more by KOYAMA and 1015 cm-2 by BALIGA, hence within the claimed range.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the defect density of the defect layer of KOYAMA in the range of 1013 cm-3 and 1016 cm-3 by implanting the ion with the implanting dose of 1012 cm-2 or more; or 1015 cm-2 by BALIGA. Same process same result.
With respect to claim 4, a process temperature of the thermal oxidation process of KOYAMA is between 1000 and 1200 Celsius degrees, thus, within the claimed range of 1000 to 1300 °C.
With respect to claim 9, an ion implantation energy of the ion implantation step (S30) of KOYAMA is between 30 keV and 700 keV, thus within the claimed range of 10 keV and 1000 keV.
With respect to claim 10, the wide bandgap semiconductor material of KOYAMA comprises silicon carbide (SiC), gallium oxide (Ga2O3), aluminum nitride (AlN), and diamond.
With respect to claim 12, the hard mask (not shown) of KOYAMA comprises a barrier layer, which is made of silicon nitride (Si3N4), silicon dioxide (SiO2) or a material that can be selectively removed from the wide bandgap semiconductor material.
With respect to claim 14, a thickness of the defect layer of KOYAMA is between 200 nm and 1 µm or less, or 400 nm by BALIGA, thus, overlaps the range of 50 and 500 nm.
It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
With respect to claim 15, after the defect layer is formed, the method of KOYAMA further comprising: forming a gate oxide layer (21) on the active region of the high power device; forming a gate conductive layer (20) on the gate oxide layer (21) and further depositing a dielectric layer (17) on the gate conductive layer (20); and forming at least one contact window (18) which extends through the dielectric layer (17) and the gate oxide layer, and electrically connected to the semiconductor substrate layer of the high power device for providing electrical paths. (See FIG. 35).
With respect to claim 17, the semiconductor substrate layer (2) of the high power device of KOYAMA comprises an N-type semiconductor substrate (1), an N-type epitaxial layer (2), a first N-type heavily doped region (14), a second N-type heavily doped region (14), a first P- type heavily doped region (13), a second P-type heavily doped region (13), a first P-type body region (11), and a second P-type body region (11), the N-type epitaxial layer (2) is disposed on the N-type semiconductor substrate (1), the first P-type body region (11) and the second P-type body region (11) are formed in the N-type epitaxial layer (2), the first P-type heavily doped region (13) is disposed on one side of the first N-type heavily doped region (14), and the first P-type heavily doped region (13) and the first N-type heavily doped region (14) are commonly disposed in the first P-type body region (11), the second P-type heavily doped region (13) is disposed on one side of the second N-type heavily doped region (14), and the second P-type heavily doped region (13) and the second N-type heavily doped region (14) are commonly disposed in the second P-type body region (11).
With respect to claim 18, the first N-type heavily doped region (14) and the second N-type heavily doped region (14) of KOYAMA are formed by using a source ion implantation in the N-type epitaxial layer (2).
With respect to claim 19, the N-type semiconductor substrate of KOYAMA is an N-type silicon carbide (SiC) substrate.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over KOYAMA ‘548 and BALIGA’ 174, as applied to claim 1 above, and further in view of DAS et al. (US. Patent No. 6,972,436) of record.
KOYAMA, in view of BALIGA, teaches the method as described in claim 1 above including the field oxide layer is formed by thermal oxidation process.
Thus, KOYAMA is shown to teach all the features of the claim with the exception of explicitly disclosing the duration of the thermal oxidation process.
However DAS teaches a method for growing a layer of oxide may be carry out for a process time from 15 minutes to about 3 hours or longer.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the field oxide layer of KOYAMA by thermal oxidation process duration as taught by DAS to achieve the desire thickness.
Note that, the duration of the thermal oxidation process depends on the desire thickness.
Claims 13 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over KOYAMA ‘548 and BALIGA ‘174 as applied to claims 12 and 15 above, and further in view of TAMAKI et al. (US. Pub. No. 2016/0190235) of record.
With respect to claim 13, KOYAMA, in view of BALIGA, teaches the method as described in claim 12 above including the hard mask comprises a barrier layer, which is made of silicon nitride (Si3N4), silicon dioxide (SiO2) or a material that can be selectively removed from the wide bandgap semiconductor material.
Thus, KOYAMA and BALIGA are shown to teach all the features of the claim with the exception of explicitly disclosing the hard mask further comprising a pad oxide layer which is configured between the barrier layer and the upper surface of the high power device.
However, TAMAKI teaches a method including: a hard mask comprises a barrier layer, which is made of silicon nitride (Si3N4), silicon dioxide (SiO2) or a material that can be selectively removed from wide bandgap semiconductor material (1),
wherein the hard mask further comprising a pad oxide layer (16) which is configured between the barrier layer (26) and the upper surface of the high power device, the pad oxide layer (16) is made of silicon dioxide (SiO2), and the barrier layer (25) is further made of another material that can be selectively removed from the pad oxide layer. (See FIG. 15).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the hard mask of KOYAMA including the pad oxide and the barrier layer as taught by TAMAKI for the same intended purpose of blocking the selected regions from ions implantation.
Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416., 125 USPQ 416.
With respect to claim 16, in the step of forming the gate conductive layer (20) of KOYAMA, further comprising: using a chemical vapor deposition (CVD) process to deposit a polysilicon (20); and using an etch back process to etch back the polysilicon (20), so as to form the gate conductive layer (20).
In view of TAMAKI, using LPCVD process to deposit polysilicon (11) is well known in the art. (See FIG. 19).
Response to Arguments
Applicant's arguments filed May 27, 2026 have been fully considered but they are not persuasive.
Applicant asserts:
Specifically, the present disclosure is related to a method for stabilizing breakdown voltages of floating guard ring. More particularly, the present Application is related to a process method which is aimed to form a defect layer by forming a field oxide layer subsequently after performing a pre-ion implantation step, in order to stabilize breakdown voltages of the floating guard ring.
By employing the disclosed process techniques of the present invention, it should be clear that a field oxide layer is formed, wherein the field oxide layer is formed by a thermal oxidation process such that a defect layer can be formed underneath the field oxide layer. (refer to Claim 1 of this current Application).
However, KOYAMA clearly teaches that the defect layer, crystal damage, 5h or 61 is formed underneath the field oxide 7a.
Thus, the limitation is met.
Applicant argues: Claim 1 is currently amended to explicitly recite that the ion implantation step is performed by using non-halogen ions such as …
Note that, the limitation: “the ion implantation step is performed by using non-halogen ions …” constitute un-support new matter and indefinite.
Moreover, as clearly indicated in the rejection above, all ion implantation inherently cause crystal damage, hence defect layer.
Regarding the “negative charges” of the halogen ions species, the instant invention also includes ions such as phosphorous and aluminum, which can generate both negative and positive charges, hence not pure physical lattice damage.
Note that, the obviousness can be shown by pointing to the teaching of in the specification that includes the subject matter that does not claim. In this case, there is no teaching of excluding non-halogen ions species; and the specification also support for utilizing ions such as phosphorous (n-type) and aluminum (p-type) to form the crystal damage layer.
In view of BALIGA, non-halogen ions such as Ar, Si, C and other ions, can be used to amorphized SiC substrate. Applicant does not argue the teaching of BALIGA.
Thus, Claim 1 is obvious over KOYAMA and BALIGA.
Applicant does not provide a meaningful argument regarding claims 5, 13 and 16.
Based on the above, the rejections of claim 1 and all dependent claims are maintained.
Conclusion
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/ANH D MAI/Primary Examiner, Art Unit 2893
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